Patent
US 8,593,180CIRCUIT INCLUDING A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE HAVING A GRAPHENE CHANNEL, AND METHOD OF OPERATING THE CIRCUIT
Shu-Jen Han
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 8,593,180Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a block diagram of a circuit 100 including a negative differential 10 resistance (NDR) device 110, according to an exemplary aspect of the present invention;
Figure 2A illustrates the NDR device 110 having a back-gate configuration, according to an exemplary aspect of the present invention;
Figure 2 B illustrates the NDR device 110 having a front-gate configuration, according to an exemplary aspect of the present invention; 15
Figure 3 illustrates a method 300 of making a circuit, according to an exemplary aspect of the present invention;
Figure 4 provides a graph illustrating characteristics of the NDR device 110, according to an exemplary aspect of the present invention;
Figure 5 provides a graph that plots results of some experiments conducted with the NDR 20 device 110 for a plurality of bias voltages (e.g., drain bias voltages), according to an exemplary aspect of the present invention;
Figure 6 illustrates current-voltage characteristics of the NDR device 110, according to an exemplary aspect of the present invention;
Figure 7 provides a graph illustrating the negative differential resistance behavior of the 25 NDR device 110, according to an exemplary aspect of the present invention;
Figure 8 illustrates output conductance, g DS, (e.g., m o deled o utput co ndu c tance) a s a function of drain voltage, VDS, for different gate voltages (e.g., VG = OV, I V, 2V, 3V and 4V), assuming amin/K = 0.5, in the NDR device 110, according to an exemplary aspect of the present invention; 30
Figure 9 shows the corresponding drain current, ID, as a function of drain voltage, VD S, for different gate voltages (e.g., V G = OV, 1V, 2V, 3V and 4V), in the NDR device 110, according to 4 YO R₉₂₀ 11 0566US 1 an exemplary aspect of the present invention;
Figure 10 illustrates a circuit 1000 including an NDR device 1010, according to an exemplary aspect of the present invention; and
Figure 11 illustrates a method 1100 of operating a circuit which includes a negative 5 differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source, according to an exemplary aspect of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A circuit comprising: a first circuit portion including a resistance; and a second circuit portion including: a three-terminal negative differential resistance (NDR) device which includes a gate, a graphene channel and source and drain electrodes contacting the graphene channel; and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance which cancels out at least a portion of the resistance of the first circuit portion. currently amended
The circuit of claim 1, wherein the NDR device further comprises: a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric, wherein the source and drain electrodes contact the gate dielectric.
The circuit of claim 1, wherein the circuit comprises one of an amplifier circuit, an oscillator circuit, a mixer circuit, an impedance cancellation circuit, a memory circuit and a logic circuit.
The circuit of claim 1, wherein the NDR device comprises one of a back gate configuration and a front gate configuration.
canceled
(Cu rr ently amended) A method of operating a circuit, the method comprising: providing a first circuit portion including a resistance, and a second circuit portion including in a three-terminal negative differential resistance (NDR) device which includes a gate, a graphene channel and source and drain electrodes contacting the graphene channel, modulating a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance which cancels out at least a portion of the resistance of the first circuit portion.
The method of claim 16, wherein the NDR device further comprises a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric, wherein the source and drain electrodes contact the gate dielectric, and the circuit comprises the NDR device, a gate voltage source and a bias voltage source, and wherein the method further comprises: modulating a bias voltage between the source and drain electrodes, by using the bias voltage source.
The method of claim 16, wherein the gate voltage satisfies the following: SVG 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634688.8.872.841.1487.973.svg 0.44 2.05 Graph Black and white where: ami n is a minimum conductivity of the graphene channel of the NDR device; C is a capacitance of the gate; and is a mobility of carriers in the graphene channel.
A circuit comprising: a negative differential resistance (NDR) device comprising: a gate; a graphene channel including a carrier mobility in a range from 100 (cm 2/Vs) to 1 Docket No. Y O R₉₂₀ 11 0566US₁ 6 Serial No. 13/418,066 YOR.868 million (cm 2/Vs); a gate dielectric contacting the gate and including a thickness in a range from 0.5 nm to 50 nm and a dielectric constant in a range from 2 to 50, the graphene channel contacting the gate dielectric; and source and drain electrodes contacting the gate dielectric and the graphene channel; a gate voltage source which modulates a gate voltage on the gate such that an electric curr ent through the graphene channel exhibits negative differential resistance; and a bias voltage source which modulates a bias voltage between the source and drain electrodes, wherein the bias voltage comprises a range of bias voltages, and the gate voltage source modulates the gate voltage on the gate such that the electric current through the graphene channel exhibits negative differential resistance over the range of bias voltages, and wherein the gate voltage source modulates the gate voltage such that the gate voltage satisfies the following: SVG 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634689.19.908.1682.1526.1812.svg 0.433 2.06 Chemistry Black and white where: ami n is a minimum conductivity of the graphene channel of the NDR device; C is a capacitance of the gate; and is a mobility of carriers in the graphene channel.
The circuit of claim 22, wherein a conductivity, a, of the graphene channel is given by Equation (1): SVG 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634689.25.867.2474.1572.2583.svg 0.363 2.35 Maths Black and white where: K is a slope factor which is given by K =C-(C being a capacitance of the gate, and being a mobility of ca rr iers in the graphene channel); VG is gate v o ltage; ami n is a minimum conductivity of the graphene channel; and VNP is gate v o ltage correspo nding to the minimum conductivity of the graphene Docket No. Y O R₉₂₀ 11 0566US 1 7 Serial No. 13/418,066 YOR.868 source-drain bias voltage, and VN P is a gate v o ltage o f minimal curr ent when VDS appr o aches zero.
A method of operating a circuit which includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source, the method comprising: modulating a gate voltage on the gate such that an electric cu rr ent through the graphene channel exhibits negative differential resistance, wherein the NDR device further comprises a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric, and source and drain electrodes contacting the gate dielectric and the graphene channel, wherein a thickness of the gate dielectric is in a range from 0.5 nm to 50 nm, a dielectric constant of the gate dielectric is in a range from 2 to 50, and a ca rr ier mobility of the graphene channel is in a range from 100 (cm 2/Vs) to 1 million (cm 2/Vs), wherein the circuit further comprises a bias voltage source which modulates a bias voltage between the source and drain electrodes, wherein the bias voltage comprises a range of bias voltages, and the gate voltage source modulates the gate voltage on the gate such that the electric current through the graphene channel exhibits negative differential resistance over the range of bias voltages, and wherein the gate voltage source modulates the gate voltage such that the gate voltage satisfies the 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634690.26.908.2450.1526.2589.svg Chemistry Black and white where: ami n is a the NDR device; C is a capacitance of the gate; and channel. following: SVG 0.463 2.06 minimum conductivity of the graphene channel of is a mobility of carriers in the graphene
Layer stacks claimed or described, ordered top of device to substrate.
three-terminal negative differential resistance (NDR) device with graphene channel
NDR device with graphene channel, gate dielectric (0.5-50 nm, dielectric constant 2-50), carrier mobility 100-1e6 cm2/Vs
Materials described outside the worked examples.
graphene
C
gate dielectric
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2A illustrates the NDR device 110 having a back-gate configuration, according to an exemplary aspect of the present invention;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 100–1000000 | C |
Thickness | 0.5–50 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,593,180Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a block diagram of a circuit 100 including a negative differential 10 resistance (NDR) device 110, according to an exemplary aspect of the present invention;
Figure 2A illustrates the NDR device 110 having a back-gate configuration, according to an exemplary aspect of the present invention;
Figure 2 B illustrates the NDR device 110 having a front-gate configuration, according to an exemplary aspect of the present invention; 15
Figure 3 illustrates a method 300 of making a circuit, according to an exemplary aspect of the present invention;
Figure 4 provides a graph illustrating characteristics of the NDR device 110, according to an exemplary aspect of the present invention;
Figure 5 provides a graph that plots results of some experiments conducted with the NDR 20 device 110 for a plurality of bias voltages (e.g., drain bias voltages), according to an exemplary aspect of the present invention;
Figure 6 illustrates current-voltage characteristics of the NDR device 110, according to an exemplary aspect of the present invention;
Figure 7 provides a graph illustrating the negative differential resistance behavior of the 25 NDR device 110, according to an exemplary aspect of the present invention;
Figure 8 illustrates output conductance, g DS, (e.g., m o deled o utput co ndu c tance) a s a function of drain voltage, VDS, for different gate voltages (e.g., VG = OV, I V, 2V, 3V and 4V), assuming amin/K = 0.5, in the NDR device 110, according to an exemplary aspect of the present invention; 30
Figure 9 shows the corresponding drain current, ID, as a function of drain voltage, VD S, for different gate voltages (e.g., V G = OV, 1V, 2V, 3V and 4V), in the NDR device 110, according to 4 YO R₉₂₀ 11 0566US 1 an exemplary aspect of the present invention;
Figure 10 illustrates a circuit 1000 including an NDR device 1010, according to an exemplary aspect of the present invention; and
Figure 11 illustrates a method 1100 of operating a circuit which includes a negative 5 differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source, according to an exemplary aspect of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A circuit comprising: a first circuit portion including a resistance; and a second circuit portion including: a three-terminal negative differential resistance (NDR) device which includes a gate, a graphene channel and source and drain electrodes contacting the graphene channel; and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance which cancels out at least a portion of the resistance of the first circuit portion. currently amended
The circuit of claim 1, wherein the NDR device further comprises: a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric, wherein the source and drain electrodes contact the gate dielectric.
The circuit of claim 1, wherein the circuit comprises one of an amplifier circuit, an oscillator circuit, a mixer circuit, an impedance cancellation circuit, a memory circuit and a logic circuit.
The circuit of claim 1, wherein the NDR device comprises one of a back gate configuration and a front gate configuration.
canceled
(Cu rr ently amended) A method of operating a circuit, the method comprising: providing a first circuit portion including a resistance, and a second circuit portion including in a three-terminal negative differential resistance (NDR) device which includes a gate, a graphene channel and source and drain electrodes contacting the graphene channel, modulating a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance which cancels out at least a portion of the resistance of the first circuit portion.
The method of claim 16, wherein the NDR device further comprises a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric, wherein the source and drain electrodes contact the gate dielectric, and the circuit comprises the NDR device, a gate voltage source and a bias voltage source, and wherein the method further comprises: modulating a bias voltage between the source and drain electrodes, by using the bias voltage source.
The method of claim 16, wherein the gate voltage satisfies the following: SVG 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634688.8.872.841.1487.973.svg 0.44 2.05 Graph Black and white where: ami n is a minimum conductivity of the graphene channel of the NDR device; C is a capacitance of the gate; and is a mobility of carriers in the graphene channel.
A circuit comprising: a negative differential resistance (NDR) device comprising: a gate; a graphene channel including a carrier mobility in a range from 100 (cm 2/Vs) to 1 Docket No. Y O R₉₂₀ 11 0566US₁ 6 Serial No. 13/418,066 YOR.868 million (cm 2/Vs); a gate dielectric contacting the gate and including a thickness in a range from 0.5 nm to 50 nm and a dielectric constant in a range from 2 to 50, the graphene channel contacting the gate dielectric; and source and drain electrodes contacting the gate dielectric and the graphene channel; a gate voltage source which modulates a gate voltage on the gate such that an electric curr ent through the graphene channel exhibits negative differential resistance; and a bias voltage source which modulates a bias voltage between the source and drain electrodes, wherein the bias voltage comprises a range of bias voltages, and the gate voltage source modulates the gate voltage on the gate such that the electric current through the graphene channel exhibits negative differential resistance over the range of bias voltages, and wherein the gate voltage source modulates the gate voltage such that the gate voltage satisfies the following: SVG 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634689.19.908.1682.1526.1812.svg 0.433 2.06 Chemistry Black and white where: ami n is a minimum conductivity of the graphene channel of the NDR device; C is a capacitance of the gate; and is a mobility of carriers in the graphene channel.
The circuit of claim 22, wherein a conductivity, a, of the graphene channel is given by Equation (1): SVG 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634689.25.867.2474.1572.2583.svg 0.363 2.35 Maths Black and white where: K is a slope factor which is given by K =C-(C being a capacitance of the gate, and being a mobility of ca rr iers in the graphene channel); VG is gate v o ltage; ami n is a minimum conductivity of the graphene channel; and VNP is gate v o ltage correspo nding to the minimum conductivity of the graphene Docket No. Y O R₉₂₀ 11 0566US 1 7 Serial No. 13/418,066 YOR.868 source-drain bias voltage, and VN P is a gate v o ltage o f minimal curr ent when VDS appr o aches zero.
A method of operating a circuit which includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source, the method comprising: modulating a gate voltage on the gate such that an electric cu rr ent through the graphene channel exhibits negative differential resistance, wherein the NDR device further comprises a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric, and source and drain electrodes contacting the gate dielectric and the graphene channel, wherein a thickness of the gate dielectric is in a range from 0.5 nm to 50 nm, a dielectric constant of the gate dielectric is in a range from 2 to 50, and a ca rr ier mobility of the graphene channel is in a range from 100 (cm 2/Vs) to 1 million (cm 2/Vs), wherein the circuit further comprises a bias voltage source which modulates a bias voltage between the source and drain electrodes, wherein the bias voltage comprises a range of bias voltages, and the gate voltage source modulates the gate voltage on the gate such that the electric current through the graphene channel exhibits negative differential resistance over the range of bias voltages, and wherein the gate voltage source modulates the gate voltage such that the gate voltage satisfies the 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634690.26.908.2450.1526.2589.svg Chemistry Black and white where: ami n is a the NDR device; C is a capacitance of the gate; and channel. following: SVG 0.463 2.06 minimum conductivity of the graphene channel of is a mobility of carriers in the graphene
Layer stacks claimed or described, ordered top of device to substrate.
three-terminal negative differential resistance (NDR) device with graphene channel
NDR device with graphene channel, gate dielectric (0.5-50 nm, dielectric constant 2-50), carrier mobility 100-1e6 cm2/Vs
Materials described outside the worked examples.
graphene
C
gate dielectric
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2A illustrates the NDR device 110 having a back-gate configuration, according to an exemplary aspect of the present invention;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 100–1000000 | C |
Thickness | 0.5–50 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,593,180Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a block diagram of a circuit 100 including a negative differential 10 resistance (NDR) device 110, according to an exemplary aspect of the present invention;
Figure 2A illustrates the NDR device 110 having a back-gate configuration, according to an exemplary aspect of the present invention;
Figure 2 B illustrates the NDR device 110 having a front-gate configuration, according to an exemplary aspect of the present invention; 15
Figure 3 illustrates a method 300 of making a circuit, according to an exemplary aspect of the present invention;
Figure 4 provides a graph illustrating characteristics of the NDR device 110, according to an exemplary aspect of the present invention;
Figure 5 provides a graph that plots results of some experiments conducted with the NDR 20 device 110 for a plurality of bias voltages (e.g., drain bias voltages), according to an exemplary aspect of the present invention;
Figure 6 illustrates current-voltage characteristics of the NDR device 110, according to an exemplary aspect of the present invention;
Figure 7 provides a graph illustrating the negative differential resistance behavior of the 25 NDR device 110, according to an exemplary aspect of the present invention;
Figure 8 illustrates output conductance, g DS, (e.g., m o deled o utput co ndu c tance) a s a function of drain voltage, VDS, for different gate voltages (e.g., VG = OV, I V, 2V, 3V and 4V), assuming amin/K = 0.5, in the NDR device 110, according to an exemplary aspect of the present invention; 30
Figure 9 shows the corresponding drain current, ID, as a function of drain voltage, VD S, for different gate voltages (e.g., V G = OV, 1V, 2V, 3V and 4V), in the NDR device 110, according to 4 YO R₉₂₀ 11 0566US 1 an exemplary aspect of the present invention;
Figure 10 illustrates a circuit 1000 including an NDR device 1010, according to an exemplary aspect of the present invention; and
Figure 11 illustrates a method 1100 of operating a circuit which includes a negative 5 differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source, according to an exemplary aspect of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A circuit comprising: a first circuit portion including a resistance; and a second circuit portion including: a three-terminal negative differential resistance (NDR) device which includes a gate, a graphene channel and source and drain electrodes contacting the graphene channel; and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance which cancels out at least a portion of the resistance of the first circuit portion. currently amended
The circuit of claim 1, wherein the NDR device further comprises: a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric, wherein the source and drain electrodes contact the gate dielectric.
The circuit of claim 1, wherein the circuit comprises one of an amplifier circuit, an oscillator circuit, a mixer circuit, an impedance cancellation circuit, a memory circuit and a logic circuit.
The circuit of claim 1, wherein the NDR device comprises one of a back gate configuration and a front gate configuration.
canceled
(Cu rr ently amended) A method of operating a circuit, the method comprising: providing a first circuit portion including a resistance, and a second circuit portion including in a three-terminal negative differential resistance (NDR) device which includes a gate, a graphene channel and source and drain electrodes contacting the graphene channel, modulating a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance which cancels out at least a portion of the resistance of the first circuit portion.
The method of claim 16, wherein the NDR device further comprises a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric, wherein the source and drain electrodes contact the gate dielectric, and the circuit comprises the NDR device, a gate voltage source and a bias voltage source, and wherein the method further comprises: modulating a bias voltage between the source and drain electrodes, by using the bias voltage source.
The method of claim 16, wherein the gate voltage satisfies the following: SVG 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634688.8.872.841.1487.973.svg 0.44 2.05 Graph Black and white where: ami n is a minimum conductivity of the graphene channel of the NDR device; C is a capacitance of the gate; and is a mobility of carriers in the graphene channel.
A circuit comprising: a negative differential resistance (NDR) device comprising: a gate; a graphene channel including a carrier mobility in a range from 100 (cm 2/Vs) to 1 Docket No. Y O R₉₂₀ 11 0566US₁ 6 Serial No. 13/418,066 YOR.868 million (cm 2/Vs); a gate dielectric contacting the gate and including a thickness in a range from 0.5 nm to 50 nm and a dielectric constant in a range from 2 to 50, the graphene channel contacting the gate dielectric; and source and drain electrodes contacting the gate dielectric and the graphene channel; a gate voltage source which modulates a gate voltage on the gate such that an electric curr ent through the graphene channel exhibits negative differential resistance; and a bias voltage source which modulates a bias voltage between the source and drain electrodes, wherein the bias voltage comprises a range of bias voltages, and the gate voltage source modulates the gate voltage on the gate such that the electric current through the graphene channel exhibits negative differential resistance over the range of bias voltages, and wherein the gate voltage source modulates the gate voltage such that the gate voltage satisfies the following: SVG 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634689.19.908.1682.1526.1812.svg 0.433 2.06 Chemistry Black and white where: ami n is a minimum conductivity of the graphene channel of the NDR device; C is a capacitance of the gate; and is a mobility of carriers in the graphene channel.
The circuit of claim 22, wherein a conductivity, a, of the graphene channel is given by Equation (1): SVG 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634689.25.867.2474.1572.2583.svg 0.363 2.35 Maths Black and white where: K is a slope factor which is given by K =C-(C being a capacitance of the gate, and being a mobility of ca rr iers in the graphene channel); VG is gate v o ltage; ami n is a minimum conductivity of the graphene channel; and VNP is gate v o ltage correspo nding to the minimum conductivity of the graphene Docket No. Y O R₉₂₀ 11 0566US 1 7 Serial No. 13/418,066 YOR.868 source-drain bias voltage, and VN P is a gate v o ltage o f minimal curr ent when VDS appr o aches zero.
A method of operating a circuit which includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source, the method comprising: modulating a gate voltage on the gate such that an electric cu rr ent through the graphene channel exhibits negative differential resistance, wherein the NDR device further comprises a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric, and source and drain electrodes contacting the gate dielectric and the graphene channel, wherein a thickness of the gate dielectric is in a range from 0.5 nm to 50 nm, a dielectric constant of the gate dielectric is in a range from 2 to 50, and a ca rr ier mobility of the graphene channel is in a range from 100 (cm 2/Vs) to 1 million (cm 2/Vs), wherein the circuit further comprises a bias voltage source which modulates a bias voltage between the source and drain electrodes, wherein the bias voltage comprises a range of bias voltages, and the gate voltage source modulates the gate voltage on the gate such that the electric current through the graphene channel exhibits negative differential resistance over the range of bias voltages, and wherein the gate voltage source modulates the gate voltage such that the gate voltage satisfies the 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634690.26.908.2450.1526.2589.svg Chemistry Black and white where: ami n is a the NDR device; C is a capacitance of the gate; and channel. following: SVG 0.463 2.06 minimum conductivity of the graphene channel of is a mobility of carriers in the graphene
Layer stacks claimed or described, ordered top of device to substrate.
three-terminal negative differential resistance (NDR) device with graphene channel
NDR device with graphene channel, gate dielectric (0.5-50 nm, dielectric constant 2-50), carrier mobility 100-1e6 cm2/Vs
Materials described outside the worked examples.
graphene
C
gate dielectric
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2A illustrates the NDR device 110 having a back-gate configuration, according to an exemplary aspect of the present invention;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 100–1000000 | C |
Thickness | 0.5–50 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,593,180Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a block diagram of a circuit 100 including a negative differential 10 resistance (NDR) device 110, according to an exemplary aspect of the present invention;
Figure 2A illustrates the NDR device 110 having a back-gate configuration, according to an exemplary aspect of the present invention;
Figure 2 B illustrates the NDR device 110 having a front-gate configuration, according to an exemplary aspect of the present invention; 15
Figure 3 illustrates a method 300 of making a circuit, according to an exemplary aspect of the present invention;
Figure 4 provides a graph illustrating characteristics of the NDR device 110, according to an exemplary aspect of the present invention;
Figure 5 provides a graph that plots results of some experiments conducted with the NDR 20 device 110 for a plurality of bias voltages (e.g., drain bias voltages), according to an exemplary aspect of the present invention;
Figure 6 illustrates current-voltage characteristics of the NDR device 110, according to an exemplary aspect of the present invention;
Figure 7 provides a graph illustrating the negative differential resistance behavior of the 25 NDR device 110, according to an exemplary aspect of the present invention;
Figure 8 illustrates output conductance, g DS, (e.g., m o deled o utput co ndu c tance) a s a function of drain voltage, VDS, for different gate voltages (e.g., VG = OV, I V, 2V, 3V and 4V), assuming amin/K = 0.5, in the NDR device 110, according to an exemplary aspect of the present invention; 30
Figure 9 shows the corresponding drain current, ID, as a function of drain voltage, VD S, for different gate voltages (e.g., V G = OV, 1V, 2V, 3V and 4V), in the NDR device 110, according to 4 YO R₉₂₀ 11 0566US 1 an exemplary aspect of the present invention;
Figure 10 illustrates a circuit 1000 including an NDR device 1010, according to an exemplary aspect of the present invention; and
Figure 11 illustrates a method 1100 of operating a circuit which includes a negative 5 differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source, according to an exemplary aspect of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A circuit comprising: a first circuit portion including a resistance; and a second circuit portion including: a three-terminal negative differential resistance (NDR) device which includes a gate, a graphene channel and source and drain electrodes contacting the graphene channel; and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance which cancels out at least a portion of the resistance of the first circuit portion. currently amended
The circuit of claim 1, wherein the NDR device further comprises: a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric, wherein the source and drain electrodes contact the gate dielectric.
The circuit of claim 1, wherein the circuit comprises one of an amplifier circuit, an oscillator circuit, a mixer circuit, an impedance cancellation circuit, a memory circuit and a logic circuit.
The circuit of claim 1, wherein the NDR device comprises one of a back gate configuration and a front gate configuration.
canceled
(Cu rr ently amended) A method of operating a circuit, the method comprising: providing a first circuit portion including a resistance, and a second circuit portion including in a three-terminal negative differential resistance (NDR) device which includes a gate, a graphene channel and source and drain electrodes contacting the graphene channel, modulating a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance which cancels out at least a portion of the resistance of the first circuit portion.
The method of claim 16, wherein the NDR device further comprises a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric, wherein the source and drain electrodes contact the gate dielectric, and the circuit comprises the NDR device, a gate voltage source and a bias voltage source, and wherein the method further comprises: modulating a bias voltage between the source and drain electrodes, by using the bias voltage source.
The method of claim 16, wherein the gate voltage satisfies the following: SVG 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634688.8.872.841.1487.973.svg 0.44 2.05 Graph Black and white where: ami n is a minimum conductivity of the graphene channel of the NDR device; C is a capacitance of the gate; and is a mobility of carriers in the graphene channel.
A circuit comprising: a negative differential resistance (NDR) device comprising: a gate; a graphene channel including a carrier mobility in a range from 100 (cm 2/Vs) to 1 Docket No. Y O R₉₂₀ 11 0566US₁ 6 Serial No. 13/418,066 YOR.868 million (cm 2/Vs); a gate dielectric contacting the gate and including a thickness in a range from 0.5 nm to 50 nm and a dielectric constant in a range from 2 to 50, the graphene channel contacting the gate dielectric; and source and drain electrodes contacting the gate dielectric and the graphene channel; a gate voltage source which modulates a gate voltage on the gate such that an electric curr ent through the graphene channel exhibits negative differential resistance; and a bias voltage source which modulates a bias voltage between the source and drain electrodes, wherein the bias voltage comprises a range of bias voltages, and the gate voltage source modulates the gate voltage on the gate such that the electric current through the graphene channel exhibits negative differential resistance over the range of bias voltages, and wherein the gate voltage source modulates the gate voltage such that the gate voltage satisfies the following: SVG 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634689.19.908.1682.1526.1812.svg 0.433 2.06 Chemistry Black and white where: ami n is a minimum conductivity of the graphene channel of the NDR device; C is a capacitance of the gate; and is a mobility of carriers in the graphene channel.
The circuit of claim 22, wherein a conductivity, a, of the graphene channel is given by Equation (1): SVG 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634689.25.867.2474.1572.2583.svg 0.363 2.35 Maths Black and white where: K is a slope factor which is given by K =C-(C being a capacitance of the gate, and being a mobility of ca rr iers in the graphene channel); VG is gate v o ltage; ami n is a minimum conductivity of the graphene channel; and VNP is gate v o ltage correspo nding to the minimum conductivity of the graphene Docket No. Y O R₉₂₀ 11 0566US 1 7 Serial No. 13/418,066 YOR.868 source-drain bias voltage, and VN P is a gate v o ltage o f minimal curr ent when VDS appr o aches zero.
A method of operating a circuit which includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source, the method comprising: modulating a gate voltage on the gate such that an electric cu rr ent through the graphene channel exhibits negative differential resistance, wherein the NDR device further comprises a gate dielectric contacting the gate, the graphene channel contacting the gate dielectric, and source and drain electrodes contacting the gate dielectric and the graphene channel, wherein a thickness of the gate dielectric is in a range from 0.5 nm to 50 nm, a dielectric constant of the gate dielectric is in a range from 2 to 50, and a ca rr ier mobility of the graphene channel is in a range from 100 (cm 2/Vs) to 1 million (cm 2/Vs), wherein the circuit further comprises a bias voltage source which modulates a bias voltage between the source and drain electrodes, wherein the bias voltage comprises a range of bias voltages, and the gate voltage source modulates the gate voltage on the gate such that the electric current through the graphene channel exhibits negative differential resistance over the range of bias voltages, and wherein the gate voltage source modulates the gate voltage such that the gate voltage satisfies the 13418066.07-15-2013.HJ₈S₇BMZPXXIFW2.CLM5634690.26.908.2450.1526.2589.svg Chemistry Black and white where: ami n is a the NDR device; C is a capacitance of the gate; and channel. following: SVG 0.463 2.06 minimum conductivity of the graphene channel of is a mobility of carriers in the graphene
Layer stacks claimed or described, ordered top of device to substrate.
three-terminal negative differential resistance (NDR) device with graphene channel
NDR device with graphene channel, gate dielectric (0.5-50 nm, dielectric constant 2-50), carrier mobility 100-1e6 cm2/Vs
Materials described outside the worked examples.
graphene
C
gate dielectric
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2A illustrates the NDR device 110 having a back-gate configuration, according to an exemplary aspect of the present invention;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 100–1000000 | C |
Thickness | 0.5–50 nm |
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Figure 4 provides a graph illustrating characteristics of the NDR device 110, according to an exemplary aspect of the present invention;
Figure 7 provides a graph illustrating the negative differential resistance behavior of the 25 NDR device 110, according to an exemplary aspect of the present invention;
Figure 8 illustrates output conductance, g DS, (e.g., m o deled o utput co ndu c tance) a s a function of drain voltage, VDS, for different gate voltages (e.g., VG = OV, I V, 2V, 3V and 4V), assuming amin/K = 0.5, in the NDR device 110, according to an exemplary aspect of the present invention; 30
Figure 9 shows the corresponding drain current, ID, as a function of drain voltage, VD S, for different gate voltages (e.g., V G = OV, 1V, 2V, 3V and 4V), in the NDR device 110, according to 4 YO R₉₂₀ 11 0566US 1 an exemplary aspect of the present invention;
Figure 11 illustrates a method 1100 of operating a circuit which includes a negative 5 differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source, according to an exemplary aspect of the present invention.
| — |
Thickness | 4–20 nm | — |
Voltage | 0–10 V | — |
NDR device-back-gate configuration
NDR device-front-gate configuration
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon oxide
SiO₂
yttrium oxide
Y₂O₃
zirconium oxide
ZrO₂
SrO
CaO
HfSiO₄
ZrSiO₄
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Figure 4 provides a graph illustrating characteristics of the NDR device 110, according to an exemplary aspect of the present invention;
Figure 7 provides a graph illustrating the negative differential resistance behavior of the 25 NDR device 110, according to an exemplary aspect of the present invention;
Figure 8 illustrates output conductance, g DS, (e.g., m o deled o utput co ndu c tance) a s a function of drain voltage, VDS, for different gate voltages (e.g., VG = OV, I V, 2V, 3V and 4V), assuming amin/K = 0.5, in the NDR device 110, according to an exemplary aspect of the present invention; 30
Figure 9 shows the corresponding drain current, ID, as a function of drain voltage, VD S, for different gate voltages (e.g., V G = OV, 1V, 2V, 3V and 4V), in the NDR device 110, according to 4 YO R₉₂₀ 11 0566US 1 an exemplary aspect of the present invention;
Figure 11 illustrates a method 1100 of operating a circuit which includes a negative 5 differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source, according to an exemplary aspect of the present invention.
| — |
Thickness | 4–20 nm | — |
Voltage | 0–10 V | — |
NDR device-back-gate configuration
NDR device-front-gate configuration
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon oxide
SiO₂
yttrium oxide
Y₂O₃
zirconium oxide
ZrO₂
SrO
CaO
HfSiO₄
ZrSiO₄
SiC
Figure 4 provides a graph illustrating characteristics of the NDR device 110, according to an exemplary aspect of the present invention;
Figure 7 provides a graph illustrating the negative differential resistance behavior of the 25 NDR device 110, according to an exemplary aspect of the present invention;
Figure 8 illustrates output conductance, g DS, (e.g., m o deled o utput co ndu c tance) a s a function of drain voltage, VDS, for different gate voltages (e.g., VG = OV, I V, 2V, 3V and 4V), assuming amin/K = 0.5, in the NDR device 110, according to an exemplary aspect of the present invention; 30
Figure 9 shows the corresponding drain current, ID, as a function of drain voltage, VD S, for different gate voltages (e.g., V G = OV, 1V, 2V, 3V and 4V), in the NDR device 110, according to 4 YO R₉₂₀ 11 0566US 1 an exemplary aspect of the present invention;
Figure 11 illustrates a method 1100 of operating a circuit which includes a negative 5 differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source, according to an exemplary aspect of the present invention.
| — |
Thickness | 4–20 nm | — |
Voltage | 0–10 V | — |
NDR device-back-gate configuration
NDR device-front-gate configuration
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon oxide
SiO₂
yttrium oxide
Y₂O₃
zirconium oxide
ZrO₂
SrO
CaO
HfSiO₄
ZrSiO₄
SiC
Figure 4 provides a graph illustrating characteristics of the NDR device 110, according to an exemplary aspect of the present invention;
Figure 7 provides a graph illustrating the negative differential resistance behavior of the 25 NDR device 110, according to an exemplary aspect of the present invention;
Figure 8 illustrates output conductance, g DS, (e.g., m o deled o utput co ndu c tance) a s a function of drain voltage, VDS, for different gate voltages (e.g., VG = OV, I V, 2V, 3V and 4V), assuming amin/K = 0.5, in the NDR device 110, according to an exemplary aspect of the present invention; 30
Figure 9 shows the corresponding drain current, ID, as a function of drain voltage, VD S, for different gate voltages (e.g., V G = OV, 1V, 2V, 3V and 4V), in the NDR device 110, according to 4 YO R₉₂₀ 11 0566US 1 an exemplary aspect of the present invention;
Figure 11 illustrates a method 1100 of operating a circuit which includes a negative 5 differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source, according to an exemplary aspect of the present invention.
| — |
Thickness | 4–20 nm | — |
Voltage | 0–10 V | — |