Patent
Atlas literature
Patent
US 10,361,196Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified flow chart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. The method …
FIG. 2E. According to some embodiments of the invention, the semiconductor device includes a substrate 201, a semiconductor fin 202 on the substrate, and a …
FIG. 3 is a FinFET includes a substrate 201, a semiconductor fin 202 on the substrate, and a catalytic material layer 204 covering the semiconductor fin. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor device, characterized by comprising: providing a substrate structure, the substrate structure having: a semiconductor substrate; and a semiconductor fin on the substrate; forming a catalytic material layer directly overlying an upper surface and sidewalls of the semiconductor [[fins]] f in; forming an isolation region covering the catalytic material layer in a lower portion of the semiconductor [[fins]] fin; forming a graphene nanoribbon on the catalytic material layer on an upper portion of the semiconductor fin covering the upper surface of the semiconductor fin; and forming a gate structure on the graphene nanoribbon. Currently amended
The method according to claim 1, wherein the semiconductor substrate and the semiconductor fin are configured as a back gate of the semiconductor device. Original
The method according to claim 1, wherein the substrate structure comprises a plurality of semiconductor fins. Currently amended
(Withdrawn, Currently Amended) The method according to claim 1, wherein forming [[an]] the isolation region comprises: depositing an insulating material to cover the semiconductor [[fins]] fin; planarizing the insulating material to expose a layer of the catalytic material on a the upper surface of the semiconductor fin; and etching an upper portion of the insulating material to expose the catalytic material layer [[in]] on the upper portion of the semiconductor fin. Currently amended
The method according to claim 1, wherein said catalytic material comprises a layer of aluminum oxide, hafnium oxide, or zirconium oxide. Original
(Withdrawn, Currently Amended) The method according to claim 1, wherein forming [[a]] the graphene nanoribbon comprises using a chemical vapor deposition by (CVD) process under the following conditions: [[the]] reaction gases include methane, hydrogen and carrier gas; [[the]] a reaction temperature is between about 600 0 C to about 1500 0 C; [[the]] a reaction time is 5-300 m in; wherein: [[the]] a carrier gas flow rate is at 0-10000 s c cm; a ratio of [[the]] a flow rate of methane and [[the]] a flow rate of the carrier gas is 0.05 %- 5 0%; and a ratio of [[the]] a flow rate of hydrogen and the flow rate of the carrier gas is 0.05 %-50%. Currently amended
(Withdrawn, Currently Amended) The method according to claim 1, wherein providing [[a]] the substrate structure comprises: providing an initial substrate; forming a patterned hard mask on the initial substrate; etching the initial substrate with the patterned hard mask as an etch mask to form the substrate, and [[a]] the semiconductor fin on the substrate. Currently amended
The method according to claim 1, wherein forming [[a]] the gate structure on the graphene nanoribbon comprises: forming a gate dielectric layer on the graphene nanoribbon; and forming a gate on the gate dielectric layer. Currently amended
The method according to claim 1, wherein the semiconductor substrate comprises silicon, and the semiconductor fin comprises silicon. Original
A semiconductor device, comprising: a substrate; a semiconductor fin on the substrate; a catalytic material layer directly on an upper surface and sidewalls of the semiconductor fin; an isolation region on a side surface of the semiconductor fin, the isolation region covering the catalytic material layer in a lower portion of the semiconductor fin; a graphene nanoribbon on the catalytic material layer on an upper portion of the semiconductor fin covering the upper surface of the semiconductor fin; and a gate structure on the graphene nanoribbon. Currently amended
The semiconductor device according to claim 12, wherein the substrate and the semiconductor fin are configured as a back gate. Original
The semiconductor device according to claim 12, wherein the semiconductor device comprises a plurality of semiconductor fins. Original
The semiconductor device according to claim 12, wherein the catalytic material comprises a layer of aluminum oxide, hafnium oxide, or zirconium oxide. Original
The semiconductor device according to claim 12, wherein the gate structure comprises: a gate dielectric layer on the graphene nanoribbon; and a gate on the gate dielectric layer. Original
The semiconductor device according to claim 12, wherein the substrate comprises silicon, and the semiconductor fin comprises silicon. Original
Layer stacks claimed or described, ordered top of device to substrate.
FinFET with graphene nanoribbon
Materials described outside the worked examples.
graphene nanoribbon
catalytic material layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2E. According to some embodiments of the invention, the semiconductor device includes a substrate 201, a semiconductor fin 202 on the substrate, and a …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,361,196Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified flow chart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. The method …
FIG. 2E. According to some embodiments of the invention, the semiconductor device includes a substrate 201, a semiconductor fin 202 on the substrate, and a …
FIG. 3 is a FinFET includes a substrate 201, a semiconductor fin 202 on the substrate, and a catalytic material layer 204 covering the semiconductor fin. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor device, characterized by comprising: providing a substrate structure, the substrate structure having: a semiconductor substrate; and a semiconductor fin on the substrate; forming a catalytic material layer directly overlying an upper surface and sidewalls of the semiconductor [[fins]] f in; forming an isolation region covering the catalytic material layer in a lower portion of the semiconductor [[fins]] fin; forming a graphene nanoribbon on the catalytic material layer on an upper portion of the semiconductor fin covering the upper surface of the semiconductor fin; and forming a gate structure on the graphene nanoribbon. Currently amended
The method according to claim 1, wherein the semiconductor substrate and the semiconductor fin are configured as a back gate of the semiconductor device. Original
The method according to claim 1, wherein the substrate structure comprises a plurality of semiconductor fins. Currently amended
(Withdrawn, Currently Amended) The method according to claim 1, wherein forming [[an]] the isolation region comprises: depositing an insulating material to cover the semiconductor [[fins]] fin; planarizing the insulating material to expose a layer of the catalytic material on a the upper surface of the semiconductor fin; and etching an upper portion of the insulating material to expose the catalytic material layer [[in]] on the upper portion of the semiconductor fin. Currently amended
The method according to claim 1, wherein said catalytic material comprises a layer of aluminum oxide, hafnium oxide, or zirconium oxide. Original
(Withdrawn, Currently Amended) The method according to claim 1, wherein forming [[a]] the graphene nanoribbon comprises using a chemical vapor deposition by (CVD) process under the following conditions: [[the]] reaction gases include methane, hydrogen and carrier gas; [[the]] a reaction temperature is between about 600 0 C to about 1500 0 C; [[the]] a reaction time is 5-300 m in; wherein: [[the]] a carrier gas flow rate is at 0-10000 s c cm; a ratio of [[the]] a flow rate of methane and [[the]] a flow rate of the carrier gas is 0.05 %- 5 0%; and a ratio of [[the]] a flow rate of hydrogen and the flow rate of the carrier gas is 0.05 %-50%. Currently amended
(Withdrawn, Currently Amended) The method according to claim 1, wherein providing [[a]] the substrate structure comprises: providing an initial substrate; forming a patterned hard mask on the initial substrate; etching the initial substrate with the patterned hard mask as an etch mask to form the substrate, and [[a]] the semiconductor fin on the substrate. Currently amended
The method according to claim 1, wherein forming [[a]] the gate structure on the graphene nanoribbon comprises: forming a gate dielectric layer on the graphene nanoribbon; and forming a gate on the gate dielectric layer. Currently amended
The method according to claim 1, wherein the semiconductor substrate comprises silicon, and the semiconductor fin comprises silicon. Original
A semiconductor device, comprising: a substrate; a semiconductor fin on the substrate; a catalytic material layer directly on an upper surface and sidewalls of the semiconductor fin; an isolation region on a side surface of the semiconductor fin, the isolation region covering the catalytic material layer in a lower portion of the semiconductor fin; a graphene nanoribbon on the catalytic material layer on an upper portion of the semiconductor fin covering the upper surface of the semiconductor fin; and a gate structure on the graphene nanoribbon. Currently amended
The semiconductor device according to claim 12, wherein the substrate and the semiconductor fin are configured as a back gate. Original
The semiconductor device according to claim 12, wherein the semiconductor device comprises a plurality of semiconductor fins. Original
The semiconductor device according to claim 12, wherein the catalytic material comprises a layer of aluminum oxide, hafnium oxide, or zirconium oxide. Original
The semiconductor device according to claim 12, wherein the gate structure comprises: a gate dielectric layer on the graphene nanoribbon; and a gate on the gate dielectric layer. Original
The semiconductor device according to claim 12, wherein the substrate comprises silicon, and the semiconductor fin comprises silicon. Original
Layer stacks claimed or described, ordered top of device to substrate.
FinFET with graphene nanoribbon
Materials described outside the worked examples.
graphene nanoribbon
catalytic material layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2E. According to some embodiments of the invention, the semiconductor device includes a substrate 201, a semiconductor fin 202 on the substrate, and a …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,361,196Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified flow chart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. The method …
FIG. 2E. According to some embodiments of the invention, the semiconductor device includes a substrate 201, a semiconductor fin 202 on the substrate, and a …
FIG. 3 is a FinFET includes a substrate 201, a semiconductor fin 202 on the substrate, and a catalytic material layer 204 covering the semiconductor fin. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor device, characterized by comprising: providing a substrate structure, the substrate structure having: a semiconductor substrate; and a semiconductor fin on the substrate; forming a catalytic material layer directly overlying an upper surface and sidewalls of the semiconductor [[fins]] f in; forming an isolation region covering the catalytic material layer in a lower portion of the semiconductor [[fins]] fin; forming a graphene nanoribbon on the catalytic material layer on an upper portion of the semiconductor fin covering the upper surface of the semiconductor fin; and forming a gate structure on the graphene nanoribbon. Currently amended
The method according to claim 1, wherein the semiconductor substrate and the semiconductor fin are configured as a back gate of the semiconductor device. Original
The method according to claim 1, wherein the substrate structure comprises a plurality of semiconductor fins. Currently amended
(Withdrawn, Currently Amended) The method according to claim 1, wherein forming [[an]] the isolation region comprises: depositing an insulating material to cover the semiconductor [[fins]] fin; planarizing the insulating material to expose a layer of the catalytic material on a the upper surface of the semiconductor fin; and etching an upper portion of the insulating material to expose the catalytic material layer [[in]] on the upper portion of the semiconductor fin. Currently amended
The method according to claim 1, wherein said catalytic material comprises a layer of aluminum oxide, hafnium oxide, or zirconium oxide. Original
(Withdrawn, Currently Amended) The method according to claim 1, wherein forming [[a]] the graphene nanoribbon comprises using a chemical vapor deposition by (CVD) process under the following conditions: [[the]] reaction gases include methane, hydrogen and carrier gas; [[the]] a reaction temperature is between about 600 0 C to about 1500 0 C; [[the]] a reaction time is 5-300 m in; wherein: [[the]] a carrier gas flow rate is at 0-10000 s c cm; a ratio of [[the]] a flow rate of methane and [[the]] a flow rate of the carrier gas is 0.05 %- 5 0%; and a ratio of [[the]] a flow rate of hydrogen and the flow rate of the carrier gas is 0.05 %-50%. Currently amended
(Withdrawn, Currently Amended) The method according to claim 1, wherein providing [[a]] the substrate structure comprises: providing an initial substrate; forming a patterned hard mask on the initial substrate; etching the initial substrate with the patterned hard mask as an etch mask to form the substrate, and [[a]] the semiconductor fin on the substrate. Currently amended
The method according to claim 1, wherein forming [[a]] the gate structure on the graphene nanoribbon comprises: forming a gate dielectric layer on the graphene nanoribbon; and forming a gate on the gate dielectric layer. Currently amended
The method according to claim 1, wherein the semiconductor substrate comprises silicon, and the semiconductor fin comprises silicon. Original
A semiconductor device, comprising: a substrate; a semiconductor fin on the substrate; a catalytic material layer directly on an upper surface and sidewalls of the semiconductor fin; an isolation region on a side surface of the semiconductor fin, the isolation region covering the catalytic material layer in a lower portion of the semiconductor fin; a graphene nanoribbon on the catalytic material layer on an upper portion of the semiconductor fin covering the upper surface of the semiconductor fin; and a gate structure on the graphene nanoribbon. Currently amended
The semiconductor device according to claim 12, wherein the substrate and the semiconductor fin are configured as a back gate. Original
The semiconductor device according to claim 12, wherein the semiconductor device comprises a plurality of semiconductor fins. Original
The semiconductor device according to claim 12, wherein the catalytic material comprises a layer of aluminum oxide, hafnium oxide, or zirconium oxide. Original
The semiconductor device according to claim 12, wherein the gate structure comprises: a gate dielectric layer on the graphene nanoribbon; and a gate on the gate dielectric layer. Original
The semiconductor device according to claim 12, wherein the substrate comprises silicon, and the semiconductor fin comprises silicon. Original
Layer stacks claimed or described, ordered top of device to substrate.
FinFET with graphene nanoribbon
Materials described outside the worked examples.
graphene nanoribbon
catalytic material layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2E. According to some embodiments of the invention, the semiconductor device includes a substrate 201, a semiconductor fin 202 on the substrate, and a …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,361,196Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified flow chart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. The method …
FIG. 2E. According to some embodiments of the invention, the semiconductor device includes a substrate 201, a semiconductor fin 202 on the substrate, and a …
FIG. 3 is a FinFET includes a substrate 201, a semiconductor fin 202 on the substrate, and a catalytic material layer 204 covering the semiconductor fin. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor device, characterized by comprising: providing a substrate structure, the substrate structure having: a semiconductor substrate; and a semiconductor fin on the substrate; forming a catalytic material layer directly overlying an upper surface and sidewalls of the semiconductor [[fins]] f in; forming an isolation region covering the catalytic material layer in a lower portion of the semiconductor [[fins]] fin; forming a graphene nanoribbon on the catalytic material layer on an upper portion of the semiconductor fin covering the upper surface of the semiconductor fin; and forming a gate structure on the graphene nanoribbon. Currently amended
The method according to claim 1, wherein the semiconductor substrate and the semiconductor fin are configured as a back gate of the semiconductor device. Original
The method according to claim 1, wherein the substrate structure comprises a plurality of semiconductor fins. Currently amended
(Withdrawn, Currently Amended) The method according to claim 1, wherein forming [[an]] the isolation region comprises: depositing an insulating material to cover the semiconductor [[fins]] fin; planarizing the insulating material to expose a layer of the catalytic material on a the upper surface of the semiconductor fin; and etching an upper portion of the insulating material to expose the catalytic material layer [[in]] on the upper portion of the semiconductor fin. Currently amended
The method according to claim 1, wherein said catalytic material comprises a layer of aluminum oxide, hafnium oxide, or zirconium oxide. Original
(Withdrawn, Currently Amended) The method according to claim 1, wherein forming [[a]] the graphene nanoribbon comprises using a chemical vapor deposition by (CVD) process under the following conditions: [[the]] reaction gases include methane, hydrogen and carrier gas; [[the]] a reaction temperature is between about 600 0 C to about 1500 0 C; [[the]] a reaction time is 5-300 m in; wherein: [[the]] a carrier gas flow rate is at 0-10000 s c cm; a ratio of [[the]] a flow rate of methane and [[the]] a flow rate of the carrier gas is 0.05 %- 5 0%; and a ratio of [[the]] a flow rate of hydrogen and the flow rate of the carrier gas is 0.05 %-50%. Currently amended
(Withdrawn, Currently Amended) The method according to claim 1, wherein providing [[a]] the substrate structure comprises: providing an initial substrate; forming a patterned hard mask on the initial substrate; etching the initial substrate with the patterned hard mask as an etch mask to form the substrate, and [[a]] the semiconductor fin on the substrate. Currently amended
The method according to claim 1, wherein forming [[a]] the gate structure on the graphene nanoribbon comprises: forming a gate dielectric layer on the graphene nanoribbon; and forming a gate on the gate dielectric layer. Currently amended
The method according to claim 1, wherein the semiconductor substrate comprises silicon, and the semiconductor fin comprises silicon. Original
A semiconductor device, comprising: a substrate; a semiconductor fin on the substrate; a catalytic material layer directly on an upper surface and sidewalls of the semiconductor fin; an isolation region on a side surface of the semiconductor fin, the isolation region covering the catalytic material layer in a lower portion of the semiconductor fin; a graphene nanoribbon on the catalytic material layer on an upper portion of the semiconductor fin covering the upper surface of the semiconductor fin; and a gate structure on the graphene nanoribbon. Currently amended
The semiconductor device according to claim 12, wherein the substrate and the semiconductor fin are configured as a back gate. Original
The semiconductor device according to claim 12, wherein the semiconductor device comprises a plurality of semiconductor fins. Original
The semiconductor device according to claim 12, wherein the catalytic material comprises a layer of aluminum oxide, hafnium oxide, or zirconium oxide. Original
The semiconductor device according to claim 12, wherein the gate structure comprises: a gate dielectric layer on the graphene nanoribbon; and a gate on the gate dielectric layer. Original
The semiconductor device according to claim 12, wherein the substrate comprises silicon, and the semiconductor fin comprises silicon. Original
Layer stacks claimed or described, ordered top of device to substrate.
FinFET with graphene nanoribbon
Materials described outside the worked examples.
graphene nanoribbon
catalytic material layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2E. According to some embodiments of the invention, the semiconductor device includes a substrate 201, a semiconductor fin 202 on the substrate, and a …
Related documents with shared materials, methods, properties, or citations.
silicon
Si
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
zirconium oxide
ZrO₂
boron nitride
BN
aluminum nitride
AlN
silicon oxide
SiO₂
amorphous silicon carbide
a-SiC
metal gate
polysilicon
silicon
Si
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
zirconium oxide
ZrO₂
boron nitride
BN
aluminum nitride
AlN
silicon oxide
SiO₂
amorphous silicon carbide
a-SiC
metal gate
polysilicon
silicon
Si
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
zirconium oxide
ZrO₂
boron nitride
BN
aluminum nitride
AlN
silicon oxide
SiO₂
amorphous silicon carbide
a-SiC
metal gate
polysilicon
silicon
Si
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
zirconium oxide
ZrO₂
boron nitride
BN
aluminum nitride
AlN
silicon oxide
SiO₂
amorphous silicon carbide
a-SiC
metal gate
polysilicon
