Patent
US 10,121,872Semiconductor Device and Manufacturing Method Therefor
Ming Zhou
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic flowchart of a method for manufacturing a semiconductor device; [0026]
FIG. 2 is schematic flowchart of another method for manufacturing a semiconductor device; [0027]
FIG. 3J illustrate schematically perspective views of several phases of a process of manufacturing a semiconductor device; and [0028]
FIG. 4G illustrate schematically perspective views of several phases of another process of manufacturing a semiconductor device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer on the first dielectric layer and the gate lines to cover the gate lines; planarizing the second dielectric layer to expose upper surfaces of the gate lines; forming an insulating buffer material layer on the second dielectric layer and the gate lines; patterning the insulating buffer material layer to form a patterned insulating buffer layer comprising multiple separate portions, each portion extending to intersect one or more gate lines; selectively growing a graphene layer on the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the second dielectric layer; and forming an upper gate electrode layer on the third dielectric layer. Original
The method according to claim 1, wherein the lower gate material layer comprises a polysilicon layer and a doped silicon germanium layer grown on the polysilicon layer. Original
The method according to claim 1, wherein the lower gate material layer comprises a polysilicon layer, and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron formed on the polysilicon layer. Original
The method according to claim 1, wherein the graphene layer is selectively grown on the patterned insulating buffer layer at a temperature of 900-1000 ° C by a chemical vapor deposition process using methane and hydrogen. Original
The method according to claim 1, wherein the insulating buffer material layer comprises an oxide of aluminum. Original
The method according to claim 1, wherein the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Original
The method according to claim 1, further comprising patterning the upper gate electrode layer to form an upper gate electrode. Original
A method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer on the first dielectric layer and the gate lines to cover the gate lines; planarizing the second dielectric layer to expose upper surfaces of the gate lines; forming an insulating buffer material layer on the second dielectric layer and the gate lines; patterning the insulating buffer material layer to form a patterned insulating buffer layer extending to intersect the gate lines; forming a patterned fourth dielectric layer, wherein the patterned fourth dielectric layer covers a portion of the patterned insulating buffer layer and exposes separate portions of the patterned insulating buffer layer, where each exposed portion of the patterned insulating buffer layer intersects one or more gate lines; selectively growing a graphene layer on the exposed portions of the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the fourth dielectric layer; and forming an upper gate electrode layer on the third dielectric layer. Original
The method according to claim 8, wherein the lower gate material layer comprises a polysilicon layer and a doped silicon germanium layer grown on the polysilicon layer, or a polysilicon layer, and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron formed on the polysilicon layer. Original
The method according to claim 8, wherein the graphene layer is selectively grown on the patterned insulating buffer layer at a temperature of 900-1000 ° C by a chemical vapor deposition process using methane and hydrogen. Original
The method according to claim 8, wherein the insulating buffer material layer comprises an oxide of aluminum and the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Original
The method according to claim 8, further comprising patterning the upper gate electrode layer to form an upper gate electrode. Original
A semiconductor device, comprising: a substrate comprising a first dielectric layer; a second dielectric layer and gate lines on the first dielectric layer, wherein an upper surface of the second dielectric layer and an upper surface of the gate lines facing away from the substrate are flush with one another; a patterned insulating buffer layer on the second dielectric layer and the gate lines, wherein the patterned insulating buffer layer comprises multiple separate portions each extending to intersect one or more gate lines; a graphene layer selectively grown on the patterned insulating buffer layer; a third dielectric layer covering the graphene layer and the second dielectric layer; and an upper gate electrode on the third dielectric layer. Withdrawn
The device according to claim 13, wherein the gate line comprises a polysilicon layer and a doped silicon germanium layer on the polysilicon layer. Withdrawn
The device according to claim 13, wherein the gate line comprises a polysilicon layer and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron on the polysilicon layer. Withdrawn
The device according to claim 13, wherein the patterned insulating buffer layer comprises an oxide of aluminum. Withdrawn
The device according to claim 13, wherein the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Withdrawn
A semiconductor device, comprising: a substrate comprising a first dielectric layer; a second dielectric layer and gate lines on the first dielectric layer, wherein an upper surface of the second dielectric layer and an upper surface of the gate lines facing away from the substrate flush with one another; a patterned insulating buffer layer on the second dielectric layer and the gate lines, wherein the insulating buffer layer extends to intersect the gate lines; a fourth dielectric layer covering part of the patterned insulating buffer layer, and separating the patterned insulating buffer layer into separate portions uncovered by the fourth dielectric layer, wherein each separate uncovered portion of the patterned insulating buffer layer intersects one or more gate lines; a graphene layer selectively grown on the separated portions of the patterned insulating buffer layer; a third dielectric layer covering the graphene layer and the fourth dielectric layer; and an upper gate electrode on the third dielectric layer. Withdrawn
The device according to claim 18, wherein the gate line comprises a polysilicon layer and a doped silicon germanium layer on the polysilicon layer, or a polysilicon layer and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron on the polysilicon layer. Withdrawn
The device according to claim 18, wherein the patterned insulating buffer layer comprises an oxide of aluminum, and wherein the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
dual-gate graphene semiconductor device (Type 1)
dual-gate graphene semiconductor device (Type 2 with fourth dielectric layer)
Materials described outside the worked examples.
graphene
oxide of aluminum
Al₂O₃
third dielectric layer
first dielectric layer
second dielectric layer
polysilicon
doped silicon germanium
SiGe
doped silicide of cobalt
CoSi₂
conductive nitride of boron
methane
CH₄
hydrogen
H₂
oxide of silicon
SiO₂
oxide of hafnium
HfO₂
nitride of aluminum
AlN
nonconductive nitride of boron
BN
bulk silicon
Si
oxide of silicon or nitride of silicon
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 900–1000 °C | — |
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GRAPHENE SHEET AND METHOD FOR PRODUCING THE SAME
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic flowchart of a method for manufacturing a semiconductor device; [0026]
FIG. 2 is schematic flowchart of another method for manufacturing a semiconductor device; [0027]
FIG. 3J illustrate schematically perspective views of several phases of a process of manufacturing a semiconductor device; and [0028]
FIG. 4G illustrate schematically perspective views of several phases of another process of manufacturing a semiconductor device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer on the first dielectric layer and the gate lines to cover the gate lines; planarizing the second dielectric layer to expose upper surfaces of the gate lines; forming an insulating buffer material layer on the second dielectric layer and the gate lines; patterning the insulating buffer material layer to form a patterned insulating buffer layer comprising multiple separate portions, each portion extending to intersect one or more gate lines; selectively growing a graphene layer on the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the second dielectric layer; and forming an upper gate electrode layer on the third dielectric layer. Original
The method according to claim 1, wherein the lower gate material layer comprises a polysilicon layer and a doped silicon germanium layer grown on the polysilicon layer. Original
The method according to claim 1, wherein the lower gate material layer comprises a polysilicon layer, and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron formed on the polysilicon layer. Original
The method according to claim 1, wherein the graphene layer is selectively grown on the patterned insulating buffer layer at a temperature of 900-1000 ° C by a chemical vapor deposition process using methane and hydrogen. Original
The method according to claim 1, wherein the insulating buffer material layer comprises an oxide of aluminum. Original
The method according to claim 1, wherein the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Original
The method according to claim 1, further comprising patterning the upper gate electrode layer to form an upper gate electrode. Original
A method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer on the first dielectric layer and the gate lines to cover the gate lines; planarizing the second dielectric layer to expose upper surfaces of the gate lines; forming an insulating buffer material layer on the second dielectric layer and the gate lines; patterning the insulating buffer material layer to form a patterned insulating buffer layer extending to intersect the gate lines; forming a patterned fourth dielectric layer, wherein the patterned fourth dielectric layer covers a portion of the patterned insulating buffer layer and exposes separate portions of the patterned insulating buffer layer, where each exposed portion of the patterned insulating buffer layer intersects one or more gate lines; selectively growing a graphene layer on the exposed portions of the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the fourth dielectric layer; and forming an upper gate electrode layer on the third dielectric layer. Original
The method according to claim 8, wherein the lower gate material layer comprises a polysilicon layer and a doped silicon germanium layer grown on the polysilicon layer, or a polysilicon layer, and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron formed on the polysilicon layer. Original
The method according to claim 8, wherein the graphene layer is selectively grown on the patterned insulating buffer layer at a temperature of 900-1000 ° C by a chemical vapor deposition process using methane and hydrogen. Original
The method according to claim 8, wherein the insulating buffer material layer comprises an oxide of aluminum and the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Original
The method according to claim 8, further comprising patterning the upper gate electrode layer to form an upper gate electrode. Original
A semiconductor device, comprising: a substrate comprising a first dielectric layer; a second dielectric layer and gate lines on the first dielectric layer, wherein an upper surface of the second dielectric layer and an upper surface of the gate lines facing away from the substrate are flush with one another; a patterned insulating buffer layer on the second dielectric layer and the gate lines, wherein the patterned insulating buffer layer comprises multiple separate portions each extending to intersect one or more gate lines; a graphene layer selectively grown on the patterned insulating buffer layer; a third dielectric layer covering the graphene layer and the second dielectric layer; and an upper gate electrode on the third dielectric layer. Withdrawn
The device according to claim 13, wherein the gate line comprises a polysilicon layer and a doped silicon germanium layer on the polysilicon layer. Withdrawn
The device according to claim 13, wherein the gate line comprises a polysilicon layer and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron on the polysilicon layer. Withdrawn
The device according to claim 13, wherein the patterned insulating buffer layer comprises an oxide of aluminum. Withdrawn
The device according to claim 13, wherein the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Withdrawn
A semiconductor device, comprising: a substrate comprising a first dielectric layer; a second dielectric layer and gate lines on the first dielectric layer, wherein an upper surface of the second dielectric layer and an upper surface of the gate lines facing away from the substrate flush with one another; a patterned insulating buffer layer on the second dielectric layer and the gate lines, wherein the insulating buffer layer extends to intersect the gate lines; a fourth dielectric layer covering part of the patterned insulating buffer layer, and separating the patterned insulating buffer layer into separate portions uncovered by the fourth dielectric layer, wherein each separate uncovered portion of the patterned insulating buffer layer intersects one or more gate lines; a graphene layer selectively grown on the separated portions of the patterned insulating buffer layer; a third dielectric layer covering the graphene layer and the fourth dielectric layer; and an upper gate electrode on the third dielectric layer. Withdrawn
The device according to claim 18, wherein the gate line comprises a polysilicon layer and a doped silicon germanium layer on the polysilicon layer, or a polysilicon layer and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron on the polysilicon layer. Withdrawn
The device according to claim 18, wherein the patterned insulating buffer layer comprises an oxide of aluminum, and wherein the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
dual-gate graphene semiconductor device (Type 1)
dual-gate graphene semiconductor device (Type 2 with fourth dielectric layer)
Materials described outside the worked examples.
graphene
oxide of aluminum
Al₂O₃
third dielectric layer
first dielectric layer
second dielectric layer
polysilicon
doped silicon germanium
SiGe
doped silicide of cobalt
CoSi₂
conductive nitride of boron
methane
CH₄
hydrogen
H₂
oxide of silicon
SiO₂
oxide of hafnium
HfO₂
nitride of aluminum
AlN
nonconductive nitride of boron
BN
bulk silicon
Si
oxide of silicon or nitride of silicon
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 900–1000 °C | — |
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METHOD FOR MANUFACTURING MONOCRYSTALLINE GRAPHENE
METHOD AND DEVICE FOR FINFET WITH GRAPHENE NANORIBBON
NANOTUBE AND GRAPHENE SEMICONDUCTOR STRUCTURES WITH VARYING ELECTRICAL PROPERTIES
WAVEGUIDE-INTEGRATED GRAPHENE PHOTODETECTORS
OPTICAL MODULATOR INCLUDING GRAPHENE
GRAPHENE SYNTHESIS BY CHEMICAL VAPOR DEPOSITION
SEMICONDUCTOR DEVICE WITH GRAPHENE LAYER AS CHANNEL
GRAPHENE ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME
METHOD OF TRANSFERRING GRAPHENE
METHODS OF FABRICATING PILLARED GRAPHENE NANOSTRUCTRES
APPARATUS AND METHOD FOR ANALYZING GRAPHENE AND GRAPHENE BOUNDARY
GRAPHENE SHEET AND METHOD FOR PRODUCING THE SAME
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic flowchart of a method for manufacturing a semiconductor device; [0026]
FIG. 2 is schematic flowchart of another method for manufacturing a semiconductor device; [0027]
FIG. 3J illustrate schematically perspective views of several phases of a process of manufacturing a semiconductor device; and [0028]
FIG. 4G illustrate schematically perspective views of several phases of another process of manufacturing a semiconductor device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer on the first dielectric layer and the gate lines to cover the gate lines; planarizing the second dielectric layer to expose upper surfaces of the gate lines; forming an insulating buffer material layer on the second dielectric layer and the gate lines; patterning the insulating buffer material layer to form a patterned insulating buffer layer comprising multiple separate portions, each portion extending to intersect one or more gate lines; selectively growing a graphene layer on the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the second dielectric layer; and forming an upper gate electrode layer on the third dielectric layer. Original
The method according to claim 1, wherein the lower gate material layer comprises a polysilicon layer and a doped silicon germanium layer grown on the polysilicon layer. Original
The method according to claim 1, wherein the lower gate material layer comprises a polysilicon layer, and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron formed on the polysilicon layer. Original
The method according to claim 1, wherein the graphene layer is selectively grown on the patterned insulating buffer layer at a temperature of 900-1000 ° C by a chemical vapor deposition process using methane and hydrogen. Original
The method according to claim 1, wherein the insulating buffer material layer comprises an oxide of aluminum. Original
The method according to claim 1, wherein the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Original
The method according to claim 1, further comprising patterning the upper gate electrode layer to form an upper gate electrode. Original
A method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer on the first dielectric layer and the gate lines to cover the gate lines; planarizing the second dielectric layer to expose upper surfaces of the gate lines; forming an insulating buffer material layer on the second dielectric layer and the gate lines; patterning the insulating buffer material layer to form a patterned insulating buffer layer extending to intersect the gate lines; forming a patterned fourth dielectric layer, wherein the patterned fourth dielectric layer covers a portion of the patterned insulating buffer layer and exposes separate portions of the patterned insulating buffer layer, where each exposed portion of the patterned insulating buffer layer intersects one or more gate lines; selectively growing a graphene layer on the exposed portions of the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the fourth dielectric layer; and forming an upper gate electrode layer on the third dielectric layer. Original
The method according to claim 8, wherein the lower gate material layer comprises a polysilicon layer and a doped silicon germanium layer grown on the polysilicon layer, or a polysilicon layer, and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron formed on the polysilicon layer. Original
The method according to claim 8, wherein the graphene layer is selectively grown on the patterned insulating buffer layer at a temperature of 900-1000 ° C by a chemical vapor deposition process using methane and hydrogen. Original
The method according to claim 8, wherein the insulating buffer material layer comprises an oxide of aluminum and the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Original
The method according to claim 8, further comprising patterning the upper gate electrode layer to form an upper gate electrode. Original
A semiconductor device, comprising: a substrate comprising a first dielectric layer; a second dielectric layer and gate lines on the first dielectric layer, wherein an upper surface of the second dielectric layer and an upper surface of the gate lines facing away from the substrate are flush with one another; a patterned insulating buffer layer on the second dielectric layer and the gate lines, wherein the patterned insulating buffer layer comprises multiple separate portions each extending to intersect one or more gate lines; a graphene layer selectively grown on the patterned insulating buffer layer; a third dielectric layer covering the graphene layer and the second dielectric layer; and an upper gate electrode on the third dielectric layer. Withdrawn
The device according to claim 13, wherein the gate line comprises a polysilicon layer and a doped silicon germanium layer on the polysilicon layer. Withdrawn
The device according to claim 13, wherein the gate line comprises a polysilicon layer and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron on the polysilicon layer. Withdrawn
The device according to claim 13, wherein the patterned insulating buffer layer comprises an oxide of aluminum. Withdrawn
The device according to claim 13, wherein the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Withdrawn
A semiconductor device, comprising: a substrate comprising a first dielectric layer; a second dielectric layer and gate lines on the first dielectric layer, wherein an upper surface of the second dielectric layer and an upper surface of the gate lines facing away from the substrate flush with one another; a patterned insulating buffer layer on the second dielectric layer and the gate lines, wherein the insulating buffer layer extends to intersect the gate lines; a fourth dielectric layer covering part of the patterned insulating buffer layer, and separating the patterned insulating buffer layer into separate portions uncovered by the fourth dielectric layer, wherein each separate uncovered portion of the patterned insulating buffer layer intersects one or more gate lines; a graphene layer selectively grown on the separated portions of the patterned insulating buffer layer; a third dielectric layer covering the graphene layer and the fourth dielectric layer; and an upper gate electrode on the third dielectric layer. Withdrawn
The device according to claim 18, wherein the gate line comprises a polysilicon layer and a doped silicon germanium layer on the polysilicon layer, or a polysilicon layer and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron on the polysilicon layer. Withdrawn
The device according to claim 18, wherein the patterned insulating buffer layer comprises an oxide of aluminum, and wherein the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
dual-gate graphene semiconductor device (Type 1)
dual-gate graphene semiconductor device (Type 2 with fourth dielectric layer)
Materials described outside the worked examples.
graphene
oxide of aluminum
Al₂O₃
third dielectric layer
first dielectric layer
second dielectric layer
polysilicon
doped silicon germanium
SiGe
doped silicide of cobalt
CoSi₂
conductive nitride of boron
methane
CH₄
hydrogen
H₂
oxide of silicon
SiO₂
oxide of hafnium
HfO₂
nitride of aluminum
AlN
nonconductive nitride of boron
BN
bulk silicon
Si
oxide of silicon or nitride of silicon
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 900–1000 °C | — |
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METHOD FOR MANUFACTURING MONOCRYSTALLINE GRAPHENE
METHOD AND DEVICE FOR FINFET WITH GRAPHENE NANORIBBON
NANOTUBE AND GRAPHENE SEMICONDUCTOR STRUCTURES WITH VARYING ELECTRICAL PROPERTIES
WAVEGUIDE-INTEGRATED GRAPHENE PHOTODETECTORS
OPTICAL MODULATOR INCLUDING GRAPHENE
GRAPHENE SYNTHESIS BY CHEMICAL VAPOR DEPOSITION
SEMICONDUCTOR DEVICE WITH GRAPHENE LAYER AS CHANNEL
GRAPHENE ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME
METHOD OF TRANSFERRING GRAPHENE
METHODS OF FABRICATING PILLARED GRAPHENE NANOSTRUCTRES
APPARATUS AND METHOD FOR ANALYZING GRAPHENE AND GRAPHENE BOUNDARY
GRAPHENE SHEET AND METHOD FOR PRODUCING THE SAME
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic flowchart of a method for manufacturing a semiconductor device; [0026]
FIG. 2 is schematic flowchart of another method for manufacturing a semiconductor device; [0027]
FIG. 3J illustrate schematically perspective views of several phases of a process of manufacturing a semiconductor device; and [0028]
FIG. 4G illustrate schematically perspective views of several phases of another process of manufacturing a semiconductor device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer on the first dielectric layer and the gate lines to cover the gate lines; planarizing the second dielectric layer to expose upper surfaces of the gate lines; forming an insulating buffer material layer on the second dielectric layer and the gate lines; patterning the insulating buffer material layer to form a patterned insulating buffer layer comprising multiple separate portions, each portion extending to intersect one or more gate lines; selectively growing a graphene layer on the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the second dielectric layer; and forming an upper gate electrode layer on the third dielectric layer. Original
The method according to claim 1, wherein the lower gate material layer comprises a polysilicon layer and a doped silicon germanium layer grown on the polysilicon layer. Original
The method according to claim 1, wherein the lower gate material layer comprises a polysilicon layer, and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron formed on the polysilicon layer. Original
The method according to claim 1, wherein the graphene layer is selectively grown on the patterned insulating buffer layer at a temperature of 900-1000 ° C by a chemical vapor deposition process using methane and hydrogen. Original
The method according to claim 1, wherein the insulating buffer material layer comprises an oxide of aluminum. Original
The method according to claim 1, wherein the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Original
The method according to claim 1, further comprising patterning the upper gate electrode layer to form an upper gate electrode. Original
A method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer on the first dielectric layer and the gate lines to cover the gate lines; planarizing the second dielectric layer to expose upper surfaces of the gate lines; forming an insulating buffer material layer on the second dielectric layer and the gate lines; patterning the insulating buffer material layer to form a patterned insulating buffer layer extending to intersect the gate lines; forming a patterned fourth dielectric layer, wherein the patterned fourth dielectric layer covers a portion of the patterned insulating buffer layer and exposes separate portions of the patterned insulating buffer layer, where each exposed portion of the patterned insulating buffer layer intersects one or more gate lines; selectively growing a graphene layer on the exposed portions of the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the fourth dielectric layer; and forming an upper gate electrode layer on the third dielectric layer. Original
The method according to claim 8, wherein the lower gate material layer comprises a polysilicon layer and a doped silicon germanium layer grown on the polysilicon layer, or a polysilicon layer, and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron formed on the polysilicon layer. Original
The method according to claim 8, wherein the graphene layer is selectively grown on the patterned insulating buffer layer at a temperature of 900-1000 ° C by a chemical vapor deposition process using methane and hydrogen. Original
The method according to claim 8, wherein the insulating buffer material layer comprises an oxide of aluminum and the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Original
The method according to claim 8, further comprising patterning the upper gate electrode layer to form an upper gate electrode. Original
A semiconductor device, comprising: a substrate comprising a first dielectric layer; a second dielectric layer and gate lines on the first dielectric layer, wherein an upper surface of the second dielectric layer and an upper surface of the gate lines facing away from the substrate are flush with one another; a patterned insulating buffer layer on the second dielectric layer and the gate lines, wherein the patterned insulating buffer layer comprises multiple separate portions each extending to intersect one or more gate lines; a graphene layer selectively grown on the patterned insulating buffer layer; a third dielectric layer covering the graphene layer and the second dielectric layer; and an upper gate electrode on the third dielectric layer. Withdrawn
The device according to claim 13, wherein the gate line comprises a polysilicon layer and a doped silicon germanium layer on the polysilicon layer. Withdrawn
The device according to claim 13, wherein the gate line comprises a polysilicon layer and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron on the polysilicon layer. Withdrawn
The device according to claim 13, wherein the patterned insulating buffer layer comprises an oxide of aluminum. Withdrawn
The device according to claim 13, wherein the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Withdrawn
A semiconductor device, comprising: a substrate comprising a first dielectric layer; a second dielectric layer and gate lines on the first dielectric layer, wherein an upper surface of the second dielectric layer and an upper surface of the gate lines facing away from the substrate flush with one another; a patterned insulating buffer layer on the second dielectric layer and the gate lines, wherein the insulating buffer layer extends to intersect the gate lines; a fourth dielectric layer covering part of the patterned insulating buffer layer, and separating the patterned insulating buffer layer into separate portions uncovered by the fourth dielectric layer, wherein each separate uncovered portion of the patterned insulating buffer layer intersects one or more gate lines; a graphene layer selectively grown on the separated portions of the patterned insulating buffer layer; a third dielectric layer covering the graphene layer and the fourth dielectric layer; and an upper gate electrode on the third dielectric layer. Withdrawn
The device according to claim 18, wherein the gate line comprises a polysilicon layer and a doped silicon germanium layer on the polysilicon layer, or a polysilicon layer and a doped layer of silicides of cobalt or a layer of conductive nitrides of boron on the polysilicon layer. Withdrawn
The device according to claim 18, wherein the patterned insulating buffer layer comprises an oxide of aluminum, and wherein the third dielectric layer comprises an oxide of silicon, an oxide of hafnium, a nonconductive nitride of boron, or a nitride of aluminum. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
dual-gate graphene semiconductor device (Type 1)
dual-gate graphene semiconductor device (Type 2 with fourth dielectric layer)
Materials described outside the worked examples.
graphene
oxide of aluminum
Al₂O₃
third dielectric layer
first dielectric layer
second dielectric layer
polysilicon
doped silicon germanium
SiGe
doped silicide of cobalt
CoSi₂
conductive nitride of boron
methane
CH₄
hydrogen
H₂
oxide of silicon
SiO₂
oxide of hafnium
HfO₂
nitride of aluminum
AlN
nonconductive nitride of boron
BN
bulk silicon
Si
oxide of silicon or nitride of silicon
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 900–1000 °C | — |
Related documents with shared materials, methods, properties, or citations.
METHOD FOR MANUFACTURING MONOCRYSTALLINE GRAPHENE
METHOD AND DEVICE FOR FINFET WITH GRAPHENE NANORIBBON
NANOTUBE AND GRAPHENE SEMICONDUCTOR STRUCTURES WITH VARYING ELECTRICAL PROPERTIES
WAVEGUIDE-INTEGRATED GRAPHENE PHOTODETECTORS
OPTICAL MODULATOR INCLUDING GRAPHENE
GRAPHENE SYNTHESIS BY CHEMICAL VAPOR DEPOSITION
SEMICONDUCTOR DEVICE WITH GRAPHENE LAYER AS CHANNEL
GRAPHENE ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME
METHOD OF TRANSFERRING GRAPHENE
METHODS OF FABRICATING PILLARED GRAPHENE NANOSTRUCTRES
APPARATUS AND METHOD FOR ANALYZING GRAPHENE AND GRAPHENE BOUNDARY
GRAPHENE SHEET AND METHOD FOR PRODUCING THE SAME