Patent
Atlas literature
Patent
US 11,978,790 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1K are cross sections of an example semiconductor device including a low threshold depletion mode gallium nitride field effect transistor, depicted in 60 …
FIG. 2 is a top view of an example semiconductor device that includes a low threshold depletion mode gallium nitride field effect transistor, and a silicon …
FIG. 3 is a circuit schematic of an example semiconductor device that includes a low threshold depletion mode gallium B₂ nitride field effect transistor, and a …
FIG. 65 1C. The aluminum-containing gas reagent may be imple- mented as trimethylaluminum or triethylaluminum, for B₂ example. The nitrogen-containing gas …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: forming a channel layer of III-N semiconductor material of a gallium nitride field effect transistor (GaN FET), the channel layer including gallium and nitrogen; forming a barrier layer of III-N semiconductor material over the channel layer, the barrier layer including aluminum and nitrogen, wherein two-dimensional elec-tron gas (2DEG) forms in the channel layer proximate the barrier layer as a result of forming the barrier layer, the 2DEG with a first free charge carrier density; forming an etch stop layer of III-N semiconductor mate-rial directly on the barrier layer, the etch stop layer including an aluminum content greater than the barrier layer; forming a p-type gate layer of III-N semiconductor mate-rial directly on the etch stop layer, the p-type gate layer including gallium and nitrogen; forming a gate mask on the p-type gate layer, the gate mask covering the p-type gate layer over an area for a p-type gate of the GaN FET; removing the p-type gate layer over the etch stop layer where exposed by the gate mask to form the p-type gate, wherein: the 2DEG under the p-type gate has a second free charge carrier density that is non-zero and less than the first free charge carrier density; and the 2DEG under the p-type gate is connected to the 2DEG outside a footprint of the p-type gate such that the GaN FET is normally on, the 2DEG outside the footprint of the p-type gate having the first free charge carrier density; and removing the gate mask.
The method of claim 1, wherein the barrier layer has a thickness of 1 nanometer to 60 nanometers.
The method of claim 1, wherein forming the barrier layer includes using a gallium containing gas reagent, so that the barrier layer includes gallium.
The method of claim 1, wherein forming the barrier layer includes using an indium containing gas reagent, so that the barrier layer includes indium.
The method of claim 1, wherein the p-type gate layer is 5 nanometers to 500 nanometers thick.
The method of claim 1, wherein forming the p-type gate layer includes using a magnesium containing gas reagent, so that the p-type gate layer has a magnesium concentration of 1×1017 cm⁻³ to 1×1020 cm⁻³.
The method of claim 1, wherein removing the p-type gate layer where exposed by the gate mask is performed using an inductively coupled plasma (ICP) process.
The method of claim 1, wherein the etch stop layer is 0.5 nanometers to 3 nanometers thick.
The method of claim 1, further comprising: forming a dielectric layer over the etch stop layer and the p-type gate, after removing the gate mask.
The method of claim 1, wherein forming the barrier layer comprises: forming an aluminum nitride layer over the channel layer; and forming an aluminum gallium nitride layer on the alumi-num nitride layer.
The method of claim 1, wherein the first free charge carrier density is greater than 8×1012 cm⁻².
The method of claim 1, wherein the second free charge carrier density is 1 percent to 75 percent of the first free charge carrier density.
The method of claim 1, wherein: the first free charge carrier density is greater than 8×1012 cm⁻²; and the second free charge carrier density is 1 percent to percent of the first free charge carrier density.
A method, comprising: forming a channel layer of a gallium nitride field effect transistor (GaN FET), the channel layer including gal-lium and nitrogen; forming a barrier layer on the channel layer, the barrier layer including aluminum and nitrogen, wherein two-dimensional electron gas (2DEG) forms in the channel layer proximate the barrier layer as a result of forming the barrier layer, the 2DEG with a first free charge carrier density; forming a p-type gate layer over the barrier layer, the p-type gate layer including gallium and nitrogen; patterning the p-type gate layer to form a p-type gate of the GaN FET, wherein: the 2DEG under the p-type gate has a second free charge carrier density that is non-zero and less than the first free charge carrier density; and the 2DEG under the p-type gate is connected to the 2DEG outside a footprint of the p-type gate such that the GaN FET is normally on, the 2DEG outside the footprint of the p-type gate having the first free charge carrier density; forming a dielectric layer over the p-type gate and over the barrier layer; and forming source and drain contacts of the GaN FET, the source and drain contacts extending through the dielec-tric layer and the barrier layer, and further extending partially into the channel layer, respectively.
The method of claim 14, further comprising: forming an etch stop layer on the barrier layer, the etch stop layer including an aluminum content greater than the barrier layer.
The method of claim 14, wherein forming the barrier layer comprises: forming an aluminum nitride layer on the channel layer; and forming an aluminum gallium nitride layer on the alumi-num nitride layer.
The method of claim 14, wherein forming the p-type gate layer has a magnesium concentration of 1×1017 cm⁻³ to 1×1020 cm⁻³.
The method of claim 14, wherein the first free charge carrier density is greater than 8×1012 cm⁻².
The method of claim 14, wherein the second free charge carrier density is 1 percent to 75 percent of the first free charge carrier density.
The method of claim 14, wherein: the first free charge carrier density is greater than 8×1012 cm⁻²; and the second free charge carrier density is 1 percent to percent of the first free charge carrier density. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
normally-on GaN FET with p-type gate
Materials described outside the worked examples.
GaN channel layer (III-N)
GaN
barrier layer (III-N, Al+N)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1K are cross sections of an example semiconductor device including a low threshold depletion mode gallium nitride field effect transistor, depicted in 60 …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN FET gate-source threshold potential (depletion mode) | — | — |
first free charge carrier density of 2DEG (outside p-gate footprint) | — | — |
second free charge carrier density of 2DEG (under p-gate), as fraction of first |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 18
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,978,790 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1K are cross sections of an example semiconductor device including a low threshold depletion mode gallium nitride field effect transistor, depicted in 60 …
FIG. 2 is a top view of an example semiconductor device that includes a low threshold depletion mode gallium nitride field effect transistor, and a silicon …
FIG. 3 is a circuit schematic of an example semiconductor device that includes a low threshold depletion mode gallium B₂ nitride field effect transistor, and a …
FIG. 65 1C. The aluminum-containing gas reagent may be imple- mented as trimethylaluminum or triethylaluminum, for B₂ example. The nitrogen-containing gas …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: forming a channel layer of III-N semiconductor material of a gallium nitride field effect transistor (GaN FET), the channel layer including gallium and nitrogen; forming a barrier layer of III-N semiconductor material over the channel layer, the barrier layer including aluminum and nitrogen, wherein two-dimensional elec-tron gas (2DEG) forms in the channel layer proximate the barrier layer as a result of forming the barrier layer, the 2DEG with a first free charge carrier density; forming an etch stop layer of III-N semiconductor mate-rial directly on the barrier layer, the etch stop layer including an aluminum content greater than the barrier layer; forming a p-type gate layer of III-N semiconductor mate-rial directly on the etch stop layer, the p-type gate layer including gallium and nitrogen; forming a gate mask on the p-type gate layer, the gate mask covering the p-type gate layer over an area for a p-type gate of the GaN FET; removing the p-type gate layer over the etch stop layer where exposed by the gate mask to form the p-type gate, wherein: the 2DEG under the p-type gate has a second free charge carrier density that is non-zero and less than the first free charge carrier density; and the 2DEG under the p-type gate is connected to the 2DEG outside a footprint of the p-type gate such that the GaN FET is normally on, the 2DEG outside the footprint of the p-type gate having the first free charge carrier density; and removing the gate mask.
The method of claim 1, wherein the barrier layer has a thickness of 1 nanometer to 60 nanometers.
The method of claim 1, wherein forming the barrier layer includes using a gallium containing gas reagent, so that the barrier layer includes gallium.
The method of claim 1, wherein forming the barrier layer includes using an indium containing gas reagent, so that the barrier layer includes indium.
The method of claim 1, wherein the p-type gate layer is 5 nanometers to 500 nanometers thick.
The method of claim 1, wherein forming the p-type gate layer includes using a magnesium containing gas reagent, so that the p-type gate layer has a magnesium concentration of 1×1017 cm⁻³ to 1×1020 cm⁻³.
The method of claim 1, wherein removing the p-type gate layer where exposed by the gate mask is performed using an inductively coupled plasma (ICP) process.
The method of claim 1, wherein the etch stop layer is 0.5 nanometers to 3 nanometers thick.
The method of claim 1, further comprising: forming a dielectric layer over the etch stop layer and the p-type gate, after removing the gate mask.
The method of claim 1, wherein forming the barrier layer comprises: forming an aluminum nitride layer over the channel layer; and forming an aluminum gallium nitride layer on the alumi-num nitride layer.
The method of claim 1, wherein the first free charge carrier density is greater than 8×1012 cm⁻².
The method of claim 1, wherein the second free charge carrier density is 1 percent to 75 percent of the first free charge carrier density.
The method of claim 1, wherein: the first free charge carrier density is greater than 8×1012 cm⁻²; and the second free charge carrier density is 1 percent to percent of the first free charge carrier density.
A method, comprising: forming a channel layer of a gallium nitride field effect transistor (GaN FET), the channel layer including gal-lium and nitrogen; forming a barrier layer on the channel layer, the barrier layer including aluminum and nitrogen, wherein two-dimensional electron gas (2DEG) forms in the channel layer proximate the barrier layer as a result of forming the barrier layer, the 2DEG with a first free charge carrier density; forming a p-type gate layer over the barrier layer, the p-type gate layer including gallium and nitrogen; patterning the p-type gate layer to form a p-type gate of the GaN FET, wherein: the 2DEG under the p-type gate has a second free charge carrier density that is non-zero and less than the first free charge carrier density; and the 2DEG under the p-type gate is connected to the 2DEG outside a footprint of the p-type gate such that the GaN FET is normally on, the 2DEG outside the footprint of the p-type gate having the first free charge carrier density; forming a dielectric layer over the p-type gate and over the barrier layer; and forming source and drain contacts of the GaN FET, the source and drain contacts extending through the dielec-tric layer and the barrier layer, and further extending partially into the channel layer, respectively.
The method of claim 14, further comprising: forming an etch stop layer on the barrier layer, the etch stop layer including an aluminum content greater than the barrier layer.
The method of claim 14, wherein forming the barrier layer comprises: forming an aluminum nitride layer on the channel layer; and forming an aluminum gallium nitride layer on the alumi-num nitride layer.
The method of claim 14, wherein forming the p-type gate layer has a magnesium concentration of 1×1017 cm⁻³ to 1×1020 cm⁻³.
The method of claim 14, wherein the first free charge carrier density is greater than 8×1012 cm⁻².
The method of claim 14, wherein the second free charge carrier density is 1 percent to 75 percent of the first free charge carrier density.
The method of claim 14, wherein: the first free charge carrier density is greater than 8×1012 cm⁻²; and the second free charge carrier density is 1 percent to percent of the first free charge carrier density. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
normally-on GaN FET with p-type gate
Materials described outside the worked examples.
GaN channel layer (III-N)
GaN
barrier layer (III-N, Al+N)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1K are cross sections of an example semiconductor device including a low threshold depletion mode gallium nitride field effect transistor, depicted in 60 …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN FET gate-source threshold potential (depletion mode) | — | — |
first free charge carrier density of 2DEG (outside p-gate footprint) | — | — |
second free charge carrier density of 2DEG (under p-gate), as fraction of first |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 18
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,978,790 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1K are cross sections of an example semiconductor device including a low threshold depletion mode gallium nitride field effect transistor, depicted in 60 …
FIG. 2 is a top view of an example semiconductor device that includes a low threshold depletion mode gallium nitride field effect transistor, and a silicon …
FIG. 3 is a circuit schematic of an example semiconductor device that includes a low threshold depletion mode gallium B₂ nitride field effect transistor, and a …
FIG. 65 1C. The aluminum-containing gas reagent may be imple- mented as trimethylaluminum or triethylaluminum, for B₂ example. The nitrogen-containing gas …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: forming a channel layer of III-N semiconductor material of a gallium nitride field effect transistor (GaN FET), the channel layer including gallium and nitrogen; forming a barrier layer of III-N semiconductor material over the channel layer, the barrier layer including aluminum and nitrogen, wherein two-dimensional elec-tron gas (2DEG) forms in the channel layer proximate the barrier layer as a result of forming the barrier layer, the 2DEG with a first free charge carrier density; forming an etch stop layer of III-N semiconductor mate-rial directly on the barrier layer, the etch stop layer including an aluminum content greater than the barrier layer; forming a p-type gate layer of III-N semiconductor mate-rial directly on the etch stop layer, the p-type gate layer including gallium and nitrogen; forming a gate mask on the p-type gate layer, the gate mask covering the p-type gate layer over an area for a p-type gate of the GaN FET; removing the p-type gate layer over the etch stop layer where exposed by the gate mask to form the p-type gate, wherein: the 2DEG under the p-type gate has a second free charge carrier density that is non-zero and less than the first free charge carrier density; and the 2DEG under the p-type gate is connected to the 2DEG outside a footprint of the p-type gate such that the GaN FET is normally on, the 2DEG outside the footprint of the p-type gate having the first free charge carrier density; and removing the gate mask.
The method of claim 1, wherein the barrier layer has a thickness of 1 nanometer to 60 nanometers.
The method of claim 1, wherein forming the barrier layer includes using a gallium containing gas reagent, so that the barrier layer includes gallium.
The method of claim 1, wherein forming the barrier layer includes using an indium containing gas reagent, so that the barrier layer includes indium.
The method of claim 1, wherein the p-type gate layer is 5 nanometers to 500 nanometers thick.
The method of claim 1, wherein forming the p-type gate layer includes using a magnesium containing gas reagent, so that the p-type gate layer has a magnesium concentration of 1×1017 cm⁻³ to 1×1020 cm⁻³.
The method of claim 1, wherein removing the p-type gate layer where exposed by the gate mask is performed using an inductively coupled plasma (ICP) process.
The method of claim 1, wherein the etch stop layer is 0.5 nanometers to 3 nanometers thick.
The method of claim 1, further comprising: forming a dielectric layer over the etch stop layer and the p-type gate, after removing the gate mask.
The method of claim 1, wherein forming the barrier layer comprises: forming an aluminum nitride layer over the channel layer; and forming an aluminum gallium nitride layer on the alumi-num nitride layer.
The method of claim 1, wherein the first free charge carrier density is greater than 8×1012 cm⁻².
The method of claim 1, wherein the second free charge carrier density is 1 percent to 75 percent of the first free charge carrier density.
The method of claim 1, wherein: the first free charge carrier density is greater than 8×1012 cm⁻²; and the second free charge carrier density is 1 percent to percent of the first free charge carrier density.
A method, comprising: forming a channel layer of a gallium nitride field effect transistor (GaN FET), the channel layer including gal-lium and nitrogen; forming a barrier layer on the channel layer, the barrier layer including aluminum and nitrogen, wherein two-dimensional electron gas (2DEG) forms in the channel layer proximate the barrier layer as a result of forming the barrier layer, the 2DEG with a first free charge carrier density; forming a p-type gate layer over the barrier layer, the p-type gate layer including gallium and nitrogen; patterning the p-type gate layer to form a p-type gate of the GaN FET, wherein: the 2DEG under the p-type gate has a second free charge carrier density that is non-zero and less than the first free charge carrier density; and the 2DEG under the p-type gate is connected to the 2DEG outside a footprint of the p-type gate such that the GaN FET is normally on, the 2DEG outside the footprint of the p-type gate having the first free charge carrier density; forming a dielectric layer over the p-type gate and over the barrier layer; and forming source and drain contacts of the GaN FET, the source and drain contacts extending through the dielec-tric layer and the barrier layer, and further extending partially into the channel layer, respectively.
The method of claim 14, further comprising: forming an etch stop layer on the barrier layer, the etch stop layer including an aluminum content greater than the barrier layer.
The method of claim 14, wherein forming the barrier layer comprises: forming an aluminum nitride layer on the channel layer; and forming an aluminum gallium nitride layer on the alumi-num nitride layer.
The method of claim 14, wherein forming the p-type gate layer has a magnesium concentration of 1×1017 cm⁻³ to 1×1020 cm⁻³.
The method of claim 14, wherein the first free charge carrier density is greater than 8×1012 cm⁻².
The method of claim 14, wherein the second free charge carrier density is 1 percent to 75 percent of the first free charge carrier density.
The method of claim 14, wherein: the first free charge carrier density is greater than 8×1012 cm⁻²; and the second free charge carrier density is 1 percent to percent of the first free charge carrier density. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
normally-on GaN FET with p-type gate
Materials described outside the worked examples.
GaN channel layer (III-N)
GaN
barrier layer (III-N, Al+N)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1K are cross sections of an example semiconductor device including a low threshold depletion mode gallium nitride field effect transistor, depicted in 60 …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN FET gate-source threshold potential (depletion mode) | — | — |
first free charge carrier density of 2DEG (outside p-gate footprint) | — | — |
second free charge carrier density of 2DEG (under p-gate), as fraction of first |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 18
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,978,790 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1K are cross sections of an example semiconductor device including a low threshold depletion mode gallium nitride field effect transistor, depicted in 60 …
FIG. 2 is a top view of an example semiconductor device that includes a low threshold depletion mode gallium nitride field effect transistor, and a silicon …
FIG. 3 is a circuit schematic of an example semiconductor device that includes a low threshold depletion mode gallium B₂ nitride field effect transistor, and a …
FIG. 65 1C. The aluminum-containing gas reagent may be imple- mented as trimethylaluminum or triethylaluminum, for B₂ example. The nitrogen-containing gas …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: forming a channel layer of III-N semiconductor material of a gallium nitride field effect transistor (GaN FET), the channel layer including gallium and nitrogen; forming a barrier layer of III-N semiconductor material over the channel layer, the barrier layer including aluminum and nitrogen, wherein two-dimensional elec-tron gas (2DEG) forms in the channel layer proximate the barrier layer as a result of forming the barrier layer, the 2DEG with a first free charge carrier density; forming an etch stop layer of III-N semiconductor mate-rial directly on the barrier layer, the etch stop layer including an aluminum content greater than the barrier layer; forming a p-type gate layer of III-N semiconductor mate-rial directly on the etch stop layer, the p-type gate layer including gallium and nitrogen; forming a gate mask on the p-type gate layer, the gate mask covering the p-type gate layer over an area for a p-type gate of the GaN FET; removing the p-type gate layer over the etch stop layer where exposed by the gate mask to form the p-type gate, wherein: the 2DEG under the p-type gate has a second free charge carrier density that is non-zero and less than the first free charge carrier density; and the 2DEG under the p-type gate is connected to the 2DEG outside a footprint of the p-type gate such that the GaN FET is normally on, the 2DEG outside the footprint of the p-type gate having the first free charge carrier density; and removing the gate mask.
The method of claim 1, wherein the barrier layer has a thickness of 1 nanometer to 60 nanometers.
The method of claim 1, wherein forming the barrier layer includes using a gallium containing gas reagent, so that the barrier layer includes gallium.
The method of claim 1, wherein forming the barrier layer includes using an indium containing gas reagent, so that the barrier layer includes indium.
The method of claim 1, wherein the p-type gate layer is 5 nanometers to 500 nanometers thick.
The method of claim 1, wherein forming the p-type gate layer includes using a magnesium containing gas reagent, so that the p-type gate layer has a magnesium concentration of 1×1017 cm⁻³ to 1×1020 cm⁻³.
The method of claim 1, wherein removing the p-type gate layer where exposed by the gate mask is performed using an inductively coupled plasma (ICP) process.
The method of claim 1, wherein the etch stop layer is 0.5 nanometers to 3 nanometers thick.
The method of claim 1, further comprising: forming a dielectric layer over the etch stop layer and the p-type gate, after removing the gate mask.
The method of claim 1, wherein forming the barrier layer comprises: forming an aluminum nitride layer over the channel layer; and forming an aluminum gallium nitride layer on the alumi-num nitride layer.
The method of claim 1, wherein the first free charge carrier density is greater than 8×1012 cm⁻².
The method of claim 1, wherein the second free charge carrier density is 1 percent to 75 percent of the first free charge carrier density.
The method of claim 1, wherein: the first free charge carrier density is greater than 8×1012 cm⁻²; and the second free charge carrier density is 1 percent to percent of the first free charge carrier density.
A method, comprising: forming a channel layer of a gallium nitride field effect transistor (GaN FET), the channel layer including gal-lium and nitrogen; forming a barrier layer on the channel layer, the barrier layer including aluminum and nitrogen, wherein two-dimensional electron gas (2DEG) forms in the channel layer proximate the barrier layer as a result of forming the barrier layer, the 2DEG with a first free charge carrier density; forming a p-type gate layer over the barrier layer, the p-type gate layer including gallium and nitrogen; patterning the p-type gate layer to form a p-type gate of the GaN FET, wherein: the 2DEG under the p-type gate has a second free charge carrier density that is non-zero and less than the first free charge carrier density; and the 2DEG under the p-type gate is connected to the 2DEG outside a footprint of the p-type gate such that the GaN FET is normally on, the 2DEG outside the footprint of the p-type gate having the first free charge carrier density; forming a dielectric layer over the p-type gate and over the barrier layer; and forming source and drain contacts of the GaN FET, the source and drain contacts extending through the dielec-tric layer and the barrier layer, and further extending partially into the channel layer, respectively.
The method of claim 14, further comprising: forming an etch stop layer on the barrier layer, the etch stop layer including an aluminum content greater than the barrier layer.
The method of claim 14, wherein forming the barrier layer comprises: forming an aluminum nitride layer on the channel layer; and forming an aluminum gallium nitride layer on the alumi-num nitride layer.
The method of claim 14, wherein forming the p-type gate layer has a magnesium concentration of 1×1017 cm⁻³ to 1×1020 cm⁻³.
The method of claim 14, wherein the first free charge carrier density is greater than 8×1012 cm⁻².
The method of claim 14, wherein the second free charge carrier density is 1 percent to 75 percent of the first free charge carrier density.
The method of claim 14, wherein: the first free charge carrier density is greater than 8×1012 cm⁻²; and the second free charge carrier density is 1 percent to percent of the first free charge carrier density. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
normally-on GaN FET with p-type gate
Materials described outside the worked examples.
GaN channel layer (III-N)
GaN
barrier layer (III-N, Al+N)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1K are cross sections of an example semiconductor device including a low threshold depletion mode gallium nitride field effect transistor, depicted in 60 …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN FET gate-source threshold potential (depletion mode) | — | — |
first free charge carrier density of 2DEG (outside p-gate footprint) | — | — |
second free charge carrier density of 2DEG (under p-gate), as fraction of first |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 18
Related documents with shared materials, methods, properties, or citations.
etch stop layer (III-N, high Al content)
p-type gate layer (III-N, Mg-doped GaN)
GaN:Mg
dielectric layer
aluminum nitride sublayer
AlN
aluminum gallium nitride sublayer
AlGaN
buffer layer (III-N)
FIG. 2 is a top view of an example semiconductor device that includes a low threshold depletion mode gallium nitride field effect transistor, and a silicon …
FIG. 3 is a circuit schematic of an example semiconductor device that includes a low threshold depletion mode gallium B₂ nitride field effect transistor, and a …
| — |
| — |
Temperature | 900–1100 °C | — |
Thickness | 1–10 nm | — |
Thickness | 0.5–3 nm | — |
Thickness | 1–60 nm | — |
Pressure | 10–50 mTorr | — |
Thickness | 5–500 nm | — |
Cited non-patent literature · 2
etch stop layer (III-N, high Al content)
p-type gate layer (III-N, Mg-doped GaN)
GaN:Mg
dielectric layer
aluminum nitride sublayer
AlN
aluminum gallium nitride sublayer
AlGaN
buffer layer (III-N)
FIG. 2 is a top view of an example semiconductor device that includes a low threshold depletion mode gallium nitride field effect transistor, and a silicon …
FIG. 3 is a circuit schematic of an example semiconductor device that includes a low threshold depletion mode gallium B₂ nitride field effect transistor, and a …
| — |
| — |
Temperature | 900–1100 °C | — |
Thickness | 1–10 nm | — |
Thickness | 0.5–3 nm | — |
Thickness | 1–60 nm | — |
Pressure | 10–50 mTorr | — |
Thickness | 5–500 nm | — |
Cited non-patent literature · 2
etch stop layer (III-N, high Al content)
p-type gate layer (III-N, Mg-doped GaN)
GaN:Mg
dielectric layer
aluminum nitride sublayer
AlN
aluminum gallium nitride sublayer
AlGaN
buffer layer (III-N)
FIG. 2 is a top view of an example semiconductor device that includes a low threshold depletion mode gallium nitride field effect transistor, and a silicon …
FIG. 3 is a circuit schematic of an example semiconductor device that includes a low threshold depletion mode gallium B₂ nitride field effect transistor, and a …
| — |
| — |
Temperature | 900–1100 °C | — |
Thickness | 1–10 nm | — |
Thickness | 0.5–3 nm | — |
Thickness | 1–60 nm | — |
Pressure | 10–50 mTorr | — |
Thickness | 5–500 nm | — |
Cited non-patent literature · 2
etch stop layer (III-N, high Al content)
p-type gate layer (III-N, Mg-doped GaN)
GaN:Mg
dielectric layer
aluminum nitride sublayer
AlN
aluminum gallium nitride sublayer
AlGaN
buffer layer (III-N)
FIG. 2 is a top view of an example semiconductor device that includes a low threshold depletion mode gallium nitride field effect transistor, and a silicon …
FIG. 3 is a circuit schematic of an example semiconductor device that includes a low threshold depletion mode gallium B₂ nitride field effect transistor, and a …
| — |
| — |
Temperature | 900–1100 °C | — |
Thickness | 1–10 nm | — |
Thickness | 0.5–3 nm | — |
Thickness | 1–60 nm | — |
Pressure | 10–50 mTorr | — |
Thickness | 5–500 nm | — |
Cited non-patent literature · 2
