Patent
Atlas literature
Patent
US 12,501,644 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1a is a sectional view of a semiconductor structure having a gallium nitride (GaN)-based transistor constructed in accordance with some embodiments;
FIGS. 2b, through 8b are schematic views of the semi- 50 conductor structure of
FIG. 3a. In
FIG. 4a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 55 138a …
FIG. 5a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 138a is …
FIG. 6a. A diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132 for isolation to prevent gate leakage. In another embodiment illustrated in
FIG. 7a. One diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132. Another diode 138f is formed between the p-GaN layer 130 and the n-GaN …
FIG. 8a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG 10 channel is defined between the source and drain. A diode 138e …
FIG. 9 is a sectional view of a semiconductor structure having a GaN-based transistor constructed in accordance 55 with some embodiments;
FIG. 10 is a sectional view of a semiconductor structure having a gallium nitride GaN-based transistor constructed in accordance with some embodiments;
FIG. 11 is a flowchart of a method making a semicon- 60 ductor structure, such as those of
FIGS. 12 through 19 are sectional views of a semicon- ductor structure (such as those of
FIG. 13, a first dielectric layer 150 is formed on the III-V semiconductor compound-based device by deposition, such as CVD, flowable CVD (CVD), spin coat- ing, …
FIG. 14, a first dielectric layer 150 is pat- terned to form a trench 160 in the first dielectric layer 150. The operation for patterning the first dielectric …
FIG. 15, a conductive layer 148 is deposited on the first dielectric layer 150 and in the trench 160 of the first dielectric layer 150 by a suitable deposition, …
FIG. 16, the conductive layer 148 is pat- terned to form a field plate, also being labeled as 148. The field plate 148 has a step-wise structure. The patterning …
FIG. 17, the second dielectric layer 156 is patterned to form trenches 162 and 164 to at least partially expose the source feature 120Aand the field plate 148 …
FIG. 18, one or more conductive material layer 166 is deposited in the trenches 162 and 164 and on the second dielectric layer 156 by a suitable deposition, …
FIG. 19, the conductive material layer 166 is patterned to form the conductive features 152 and 154, by a procedure that includes a lithography process and …
FIGS. 20 through 24 are sectional views of a semicon- ductor structure (such as those of
FIG. 21. The conductive feature 152 is formed by a process that includes patterning the second dielectric layer 156 to form a trench 162, as illustrated in
FIG. 22; depositing a conductive 45 material layer 166 on the second dielectric layer 156 and in the trench 162 by a suitable deposition method, as illustrated …
FIG. 23; and performing a patterning process to the conductive material layer 166 to form the conductive feature 152, as illustrated in
FIG. 24. 50
FIGS. 25 through 27 are sectional views of a semicon- ductor structure at various fabrication stages according to various embodiments; and
FIG. 26. Thereafter, the operations 208-212 are performed to form the field plate 148 as illustrated in
FIG. 27. In alter- B₂ native embodiments, the semiconductor structure 100 is a two-terminal device without the gate stack 122 but the field plate has a …
FIG. 28 is a diagrammatic view of various characteristic data of the gallium nitride GaN-based device according to some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a gallium nitride (GaN) layer on a substrate and having a top surface with a plane normal direction oriented from the substrate to the GaN layer; an aluminum gallium nitride (AlGaN) layer disposed on the top surface of the GaN layer along the plane normal direction; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a first dielectric material layer disposed on the gate stack; a field plate disposed on the first dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure, wherein the step-wise structure includes a first segment extending horizontally along a first direction being perpendicular to the plane normal direction, a second segment extending vertically from the first segment along the plane normal direction, and a third segment extending horizontally from the second segment along the first direction, and wherein the third segment is above the first segment along the plane normal direc-tion; a second dielectric material layer disposed on both the first dielectric material layer and the field plate; a first via on the source feature; a second via embedded in the second dielectric material layer and on the third segment of the field plate; and a metal line disposed on a topmost surface of the second dielectric material layer and above both the first and second vias along the plane normal direction and contacting both the first via and the second via, wherein the first via spans a first height along the plane normal direction, the second via spans a second height along the plane normal direction, the step-wise structure spans a third height along the plane normal direction, and the first height is greater than the sum of the second height and the third height.
The semiconductor structure of claim 1, wherein the second via includes a bottom surface and a top surface along the plane normal direction; the third segment includes a top surface being coplanar with the bottom surface of the second via; the metal line includes a bottom surface being coplanar with the top surface of the second via; the bottom surface of the second via spans a first lateral dimension along the first direction; the top surface of the third segment spans a second lateral dimension along the first direction; the second lateral dimension is greater than the first lateral dimension; and the step-wise structure is only electrically connected to the metal line through the second via.
The semiconductor structure of claim 1, wherein the gate stack includes a III-V compound p-type doped layer.
The semiconductor structure of claim 1, wherein the first via spans between the source feature and the metal line along the plane normal direction; and the second via spans between the third segment and the metal line along plane normal direction.
The semiconductor structure of claim 1, wherein the first via includes a bottom surface and a top surface along the plane normal direction; the first via includes a sidewall surface extending from the top surface to the bottom surface; and the sidewall surface of the first via is fully surrounded by the first and second dielectric material layers.
The semiconductor structure of claim 1, wherein the GaN layer is undoped or unintentionally doped.
The semiconductor structure of claim 1, wherein the source feature, the drain feature, and the gate stack are configured with the GaN layer and the AlGaN layer to form 45 a high electron mobility transistor.
The semiconductor structure of claim 1, wherein the top surface of the second dielectric material layer is above a topmost surface of the field plate along the plane normal direction; and the first via extending from the top surface of the dielec-tric layer to the source feature along the plane normal direction. ∗ ∗ ∗ ∗ ∗
A semiconductor structure, comprising: a first III-V compound layer on a substrate; a second III-V compound layer on the first III-V com-pound layer, the second III-V compound layer being different from the first III-V compound layer in com-position and further including aluminum; a gate stack on the second III-V compound layer; a source feature and a drain feature disposed on the second III-V compound layer; 55 a first via and a second via; a field plate disposed over the gate stack and electrically connected to the source feature by way of the first via and the second via, wherein the field plate includes at least three segments with a step-wise structure, and wherein the first via is on the source feature, wherein the step-wise structure includes a first segment extend-ing horizontally along a first direction, a second seg-ment extending vertically from the first segment along a second direction being perpendicular to the first direction, and a third segment extending horizontally from the second segment along the first direction, B₂ wherein the second III-V compound layer is directly on the second III-V compound layer along the second direction, and wherein the third segment is above the first segment along the second direction and the second via is in contact with a topmost segment of the field plate along the second direction; and a metal line disposed above and contacting both the first via and the second via along the second direction, wherein the first via spans a first height along the second direction, the second via spans a second height along the second direction, the step-wise structure spans a third height along the second direction, and the first height is greater than the sum of the second height and the third height.
The semiconductor structure of claim 13, wherein the first via includes a bottom surface and a top surface along the second direction; the second via includes a bottom surface and a top surface along the second direction; the metal line includes a bottom surface and a top surface along the second direction; the bottom surface of the metal line contacts the top surface of the first via and the top surface of the second via; the step-wise structure includes a top surface being copla-nar with the bottom surface of the second via along the second direction; the bottom surface of the second via spans a first lateral dimension along the first direction; the top surface of the third segment spans a second lateral dimension along the first direction; the second lateral dimension is greater than the first lateral dimension; and the step-wise structure is only electrically connected to the metal line through the second via.
A semiconductor structure, comprising: a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer, wherein the gate stack includes a junction isolation feature and a metal layer disposed on the junction isolation feature; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; a field plate embedded in the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure, wherein the step-wise structure includes a first segment extending horizontally along a first direction, a second segment extending vertically from the first segment along a second direction being perpendicular to the first direc-tion, and a third segment extending horizontally from the second segment along the first direction, wherein the AlGaN layer is above and contacts the GaN layer along the second direction, the gate stack is above and contacts the AlGaN layer, and wherein the third seg-ment is above the first segment along the second direction; a first via embedded in the dielectric material layer, vertically landing on the source feature, and having a top surface and a bottom surface along the second direction; a second via embedded in the dielectric material layer, vertically landing on the third segment, and having a top surface and a bottom surface along the second direction; and a metal line disposed on a top surface of the dielectric material layer along the second direction, and contact-ing the top surface of the first via and the top surface of the second via, wherein the first via spans a first height along the second direction, the second via spans a second height along the second direction, the step-wise structure spans a third height along the second direction, and the first height is greater than the sum of the second height and the third height.
The semiconductor structure of claim 16, wherein a top surface of the third segment is coplanar with a bottom surface of the second via; the bottom surface of the second via spans a first lateral dimension along the first direction; the top surface of the third segment spans a second lateral dimension along the first direction; the second lateral dimension is greater than the first lateral dimension; the step-wise structure is only electrically connected to the metal line through the second via; and the metal line is overlapped with the first via and the second via in a top view.
The semiconductor structure of claim 16, wherein the first via spans between the source feature and the metal line along the second direction; the second via spans between the third segment and the metal line along the second direction; and a bottom surface of the first via is below a bottom surface of the first segment along the second direction.
The semiconductor structure of claim 16, wherein the junction isolation feature includes two p-type doped GaN layers and two n-type doped GaN layers alterna-tively stacked; each of the two p-type doped GaN layers is doped with an impurity selected from the group consisting of magne-sium, calcium, zinc, beryllium, and carbon; and each of the two n-type doped GaN layers is doped with an impurity selected from the group consisting of silicon and oxygen.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT with step-wise field plate (claims 1–12, 20)
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
aluminum gallium nitride (AlGaN) layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1a is a sectional view of a semiconductor structure having a gallium nitride (GaN)-based transistor constructed in accordance with some embodiments;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–10 µm | — |
Thickness | 5–50 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,501,644 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1a is a sectional view of a semiconductor structure having a gallium nitride (GaN)-based transistor constructed in accordance with some embodiments;
FIGS. 2b, through 8b are schematic views of the semi- 50 conductor structure of
FIG. 3a. In
FIG. 4a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 55 138a …
FIG. 5a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 138a is …
FIG. 6a. A diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132 for isolation to prevent gate leakage. In another embodiment illustrated in
FIG. 7a. One diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132. Another diode 138f is formed between the p-GaN layer 130 and the n-GaN …
FIG. 8a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG 10 channel is defined between the source and drain. A diode 138e …
FIG. 9 is a sectional view of a semiconductor structure having a GaN-based transistor constructed in accordance 55 with some embodiments;
FIG. 10 is a sectional view of a semiconductor structure having a gallium nitride GaN-based transistor constructed in accordance with some embodiments;
FIG. 11 is a flowchart of a method making a semicon- 60 ductor structure, such as those of
FIGS. 12 through 19 are sectional views of a semicon- ductor structure (such as those of
FIG. 13, a first dielectric layer 150 is formed on the III-V semiconductor compound-based device by deposition, such as CVD, flowable CVD (CVD), spin coat- ing, …
FIG. 14, a first dielectric layer 150 is pat- terned to form a trench 160 in the first dielectric layer 150. The operation for patterning the first dielectric …
FIG. 15, a conductive layer 148 is deposited on the first dielectric layer 150 and in the trench 160 of the first dielectric layer 150 by a suitable deposition, …
FIG. 16, the conductive layer 148 is pat- terned to form a field plate, also being labeled as 148. The field plate 148 has a step-wise structure. The patterning …
FIG. 17, the second dielectric layer 156 is patterned to form trenches 162 and 164 to at least partially expose the source feature 120Aand the field plate 148 …
FIG. 18, one or more conductive material layer 166 is deposited in the trenches 162 and 164 and on the second dielectric layer 156 by a suitable deposition, …
FIG. 19, the conductive material layer 166 is patterned to form the conductive features 152 and 154, by a procedure that includes a lithography process and …
FIGS. 20 through 24 are sectional views of a semicon- ductor structure (such as those of
FIG. 21. The conductive feature 152 is formed by a process that includes patterning the second dielectric layer 156 to form a trench 162, as illustrated in
FIG. 22; depositing a conductive 45 material layer 166 on the second dielectric layer 156 and in the trench 162 by a suitable deposition method, as illustrated …
FIG. 23; and performing a patterning process to the conductive material layer 166 to form the conductive feature 152, as illustrated in
FIG. 24. 50
FIGS. 25 through 27 are sectional views of a semicon- ductor structure at various fabrication stages according to various embodiments; and
FIG. 26. Thereafter, the operations 208-212 are performed to form the field plate 148 as illustrated in
FIG. 27. In alter- B₂ native embodiments, the semiconductor structure 100 is a two-terminal device without the gate stack 122 but the field plate has a …
FIG. 28 is a diagrammatic view of various characteristic data of the gallium nitride GaN-based device according to some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a gallium nitride (GaN) layer on a substrate and having a top surface with a plane normal direction oriented from the substrate to the GaN layer; an aluminum gallium nitride (AlGaN) layer disposed on the top surface of the GaN layer along the plane normal direction; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a first dielectric material layer disposed on the gate stack; a field plate disposed on the first dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure, wherein the step-wise structure includes a first segment extending horizontally along a first direction being perpendicular to the plane normal direction, a second segment extending vertically from the first segment along the plane normal direction, and a third segment extending horizontally from the second segment along the first direction, and wherein the third segment is above the first segment along the plane normal direc-tion; a second dielectric material layer disposed on both the first dielectric material layer and the field plate; a first via on the source feature; a second via embedded in the second dielectric material layer and on the third segment of the field plate; and a metal line disposed on a topmost surface of the second dielectric material layer and above both the first and second vias along the plane normal direction and contacting both the first via and the second via, wherein the first via spans a first height along the plane normal direction, the second via spans a second height along the plane normal direction, the step-wise structure spans a third height along the plane normal direction, and the first height is greater than the sum of the second height and the third height.
The semiconductor structure of claim 1, wherein the second via includes a bottom surface and a top surface along the plane normal direction; the third segment includes a top surface being coplanar with the bottom surface of the second via; the metal line includes a bottom surface being coplanar with the top surface of the second via; the bottom surface of the second via spans a first lateral dimension along the first direction; the top surface of the third segment spans a second lateral dimension along the first direction; the second lateral dimension is greater than the first lateral dimension; and the step-wise structure is only electrically connected to the metal line through the second via.
The semiconductor structure of claim 1, wherein the gate stack includes a III-V compound p-type doped layer.
The semiconductor structure of claim 1, wherein the first via spans between the source feature and the metal line along the plane normal direction; and the second via spans between the third segment and the metal line along plane normal direction.
The semiconductor structure of claim 1, wherein the first via includes a bottom surface and a top surface along the plane normal direction; the first via includes a sidewall surface extending from the top surface to the bottom surface; and the sidewall surface of the first via is fully surrounded by the first and second dielectric material layers.
The semiconductor structure of claim 1, wherein the GaN layer is undoped or unintentionally doped.
The semiconductor structure of claim 1, wherein the source feature, the drain feature, and the gate stack are configured with the GaN layer and the AlGaN layer to form 45 a high electron mobility transistor.
The semiconductor structure of claim 1, wherein the top surface of the second dielectric material layer is above a topmost surface of the field plate along the plane normal direction; and the first via extending from the top surface of the dielec-tric layer to the source feature along the plane normal direction. ∗ ∗ ∗ ∗ ∗
A semiconductor structure, comprising: a first III-V compound layer on a substrate; a second III-V compound layer on the first III-V com-pound layer, the second III-V compound layer being different from the first III-V compound layer in com-position and further including aluminum; a gate stack on the second III-V compound layer; a source feature and a drain feature disposed on the second III-V compound layer; 55 a first via and a second via; a field plate disposed over the gate stack and electrically connected to the source feature by way of the first via and the second via, wherein the field plate includes at least three segments with a step-wise structure, and wherein the first via is on the source feature, wherein the step-wise structure includes a first segment extend-ing horizontally along a first direction, a second seg-ment extending vertically from the first segment along a second direction being perpendicular to the first direction, and a third segment extending horizontally from the second segment along the first direction, B₂ wherein the second III-V compound layer is directly on the second III-V compound layer along the second direction, and wherein the third segment is above the first segment along the second direction and the second via is in contact with a topmost segment of the field plate along the second direction; and a metal line disposed above and contacting both the first via and the second via along the second direction, wherein the first via spans a first height along the second direction, the second via spans a second height along the second direction, the step-wise structure spans a third height along the second direction, and the first height is greater than the sum of the second height and the third height.
The semiconductor structure of claim 13, wherein the first via includes a bottom surface and a top surface along the second direction; the second via includes a bottom surface and a top surface along the second direction; the metal line includes a bottom surface and a top surface along the second direction; the bottom surface of the metal line contacts the top surface of the first via and the top surface of the second via; the step-wise structure includes a top surface being copla-nar with the bottom surface of the second via along the second direction; the bottom surface of the second via spans a first lateral dimension along the first direction; the top surface of the third segment spans a second lateral dimension along the first direction; the second lateral dimension is greater than the first lateral dimension; and the step-wise structure is only electrically connected to the metal line through the second via.
A semiconductor structure, comprising: a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer, wherein the gate stack includes a junction isolation feature and a metal layer disposed on the junction isolation feature; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; a field plate embedded in the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure, wherein the step-wise structure includes a first segment extending horizontally along a first direction, a second segment extending vertically from the first segment along a second direction being perpendicular to the first direc-tion, and a third segment extending horizontally from the second segment along the first direction, wherein the AlGaN layer is above and contacts the GaN layer along the second direction, the gate stack is above and contacts the AlGaN layer, and wherein the third seg-ment is above the first segment along the second direction; a first via embedded in the dielectric material layer, vertically landing on the source feature, and having a top surface and a bottom surface along the second direction; a second via embedded in the dielectric material layer, vertically landing on the third segment, and having a top surface and a bottom surface along the second direction; and a metal line disposed on a top surface of the dielectric material layer along the second direction, and contact-ing the top surface of the first via and the top surface of the second via, wherein the first via spans a first height along the second direction, the second via spans a second height along the second direction, the step-wise structure spans a third height along the second direction, and the first height is greater than the sum of the second height and the third height.
The semiconductor structure of claim 16, wherein a top surface of the third segment is coplanar with a bottom surface of the second via; the bottom surface of the second via spans a first lateral dimension along the first direction; the top surface of the third segment spans a second lateral dimension along the first direction; the second lateral dimension is greater than the first lateral dimension; the step-wise structure is only electrically connected to the metal line through the second via; and the metal line is overlapped with the first via and the second via in a top view.
The semiconductor structure of claim 16, wherein the first via spans between the source feature and the metal line along the second direction; the second via spans between the third segment and the metal line along the second direction; and a bottom surface of the first via is below a bottom surface of the first segment along the second direction.
The semiconductor structure of claim 16, wherein the junction isolation feature includes two p-type doped GaN layers and two n-type doped GaN layers alterna-tively stacked; each of the two p-type doped GaN layers is doped with an impurity selected from the group consisting of magne-sium, calcium, zinc, beryllium, and carbon; and each of the two n-type doped GaN layers is doped with an impurity selected from the group consisting of silicon and oxygen.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT with step-wise field plate (claims 1–12, 20)
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
aluminum gallium nitride (AlGaN) layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1a is a sectional view of a semiconductor structure having a gallium nitride (GaN)-based transistor constructed in accordance with some embodiments;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–10 µm | — |
Thickness | 5–50 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,501,644 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1a is a sectional view of a semiconductor structure having a gallium nitride (GaN)-based transistor constructed in accordance with some embodiments;
FIGS. 2b, through 8b are schematic views of the semi- 50 conductor structure of
FIG. 3a. In
FIG. 4a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 55 138a …
FIG. 5a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 138a is …
FIG. 6a. A diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132 for isolation to prevent gate leakage. In another embodiment illustrated in
FIG. 7a. One diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132. Another diode 138f is formed between the p-GaN layer 130 and the n-GaN …
FIG. 8a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG 10 channel is defined between the source and drain. A diode 138e …
FIG. 9 is a sectional view of a semiconductor structure having a GaN-based transistor constructed in accordance 55 with some embodiments;
FIG. 10 is a sectional view of a semiconductor structure having a gallium nitride GaN-based transistor constructed in accordance with some embodiments;
FIG. 11 is a flowchart of a method making a semicon- 60 ductor structure, such as those of
FIGS. 12 through 19 are sectional views of a semicon- ductor structure (such as those of
FIG. 13, a first dielectric layer 150 is formed on the III-V semiconductor compound-based device by deposition, such as CVD, flowable CVD (CVD), spin coat- ing, …
FIG. 14, a first dielectric layer 150 is pat- terned to form a trench 160 in the first dielectric layer 150. The operation for patterning the first dielectric …
FIG. 15, a conductive layer 148 is deposited on the first dielectric layer 150 and in the trench 160 of the first dielectric layer 150 by a suitable deposition, …
FIG. 16, the conductive layer 148 is pat- terned to form a field plate, also being labeled as 148. The field plate 148 has a step-wise structure. The patterning …
FIG. 17, the second dielectric layer 156 is patterned to form trenches 162 and 164 to at least partially expose the source feature 120Aand the field plate 148 …
FIG. 18, one or more conductive material layer 166 is deposited in the trenches 162 and 164 and on the second dielectric layer 156 by a suitable deposition, …
FIG. 19, the conductive material layer 166 is patterned to form the conductive features 152 and 154, by a procedure that includes a lithography process and …
FIGS. 20 through 24 are sectional views of a semicon- ductor structure (such as those of
FIG. 21. The conductive feature 152 is formed by a process that includes patterning the second dielectric layer 156 to form a trench 162, as illustrated in
FIG. 22; depositing a conductive 45 material layer 166 on the second dielectric layer 156 and in the trench 162 by a suitable deposition method, as illustrated …
FIG. 23; and performing a patterning process to the conductive material layer 166 to form the conductive feature 152, as illustrated in
FIG. 24. 50
FIGS. 25 through 27 are sectional views of a semicon- ductor structure at various fabrication stages according to various embodiments; and
FIG. 26. Thereafter, the operations 208-212 are performed to form the field plate 148 as illustrated in
FIG. 27. In alter- B₂ native embodiments, the semiconductor structure 100 is a two-terminal device without the gate stack 122 but the field plate has a …
FIG. 28 is a diagrammatic view of various characteristic data of the gallium nitride GaN-based device according to some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a gallium nitride (GaN) layer on a substrate and having a top surface with a plane normal direction oriented from the substrate to the GaN layer; an aluminum gallium nitride (AlGaN) layer disposed on the top surface of the GaN layer along the plane normal direction; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a first dielectric material layer disposed on the gate stack; a field plate disposed on the first dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure, wherein the step-wise structure includes a first segment extending horizontally along a first direction being perpendicular to the plane normal direction, a second segment extending vertically from the first segment along the plane normal direction, and a third segment extending horizontally from the second segment along the first direction, and wherein the third segment is above the first segment along the plane normal direc-tion; a second dielectric material layer disposed on both the first dielectric material layer and the field plate; a first via on the source feature; a second via embedded in the second dielectric material layer and on the third segment of the field plate; and a metal line disposed on a topmost surface of the second dielectric material layer and above both the first and second vias along the plane normal direction and contacting both the first via and the second via, wherein the first via spans a first height along the plane normal direction, the second via spans a second height along the plane normal direction, the step-wise structure spans a third height along the plane normal direction, and the first height is greater than the sum of the second height and the third height.
The semiconductor structure of claim 1, wherein the second via includes a bottom surface and a top surface along the plane normal direction; the third segment includes a top surface being coplanar with the bottom surface of the second via; the metal line includes a bottom surface being coplanar with the top surface of the second via; the bottom surface of the second via spans a first lateral dimension along the first direction; the top surface of the third segment spans a second lateral dimension along the first direction; the second lateral dimension is greater than the first lateral dimension; and the step-wise structure is only electrically connected to the metal line through the second via.
The semiconductor structure of claim 1, wherein the gate stack includes a III-V compound p-type doped layer.
The semiconductor structure of claim 1, wherein the first via spans between the source feature and the metal line along the plane normal direction; and the second via spans between the third segment and the metal line along plane normal direction.
The semiconductor structure of claim 1, wherein the first via includes a bottom surface and a top surface along the plane normal direction; the first via includes a sidewall surface extending from the top surface to the bottom surface; and the sidewall surface of the first via is fully surrounded by the first and second dielectric material layers.
The semiconductor structure of claim 1, wherein the GaN layer is undoped or unintentionally doped.
The semiconductor structure of claim 1, wherein the source feature, the drain feature, and the gate stack are configured with the GaN layer and the AlGaN layer to form 45 a high electron mobility transistor.
The semiconductor structure of claim 1, wherein the top surface of the second dielectric material layer is above a topmost surface of the field plate along the plane normal direction; and the first via extending from the top surface of the dielec-tric layer to the source feature along the plane normal direction. ∗ ∗ ∗ ∗ ∗
A semiconductor structure, comprising: a first III-V compound layer on a substrate; a second III-V compound layer on the first III-V com-pound layer, the second III-V compound layer being different from the first III-V compound layer in com-position and further including aluminum; a gate stack on the second III-V compound layer; a source feature and a drain feature disposed on the second III-V compound layer; 55 a first via and a second via; a field plate disposed over the gate stack and electrically connected to the source feature by way of the first via and the second via, wherein the field plate includes at least three segments with a step-wise structure, and wherein the first via is on the source feature, wherein the step-wise structure includes a first segment extend-ing horizontally along a first direction, a second seg-ment extending vertically from the first segment along a second direction being perpendicular to the first direction, and a third segment extending horizontally from the second segment along the first direction, B₂ wherein the second III-V compound layer is directly on the second III-V compound layer along the second direction, and wherein the third segment is above the first segment along the second direction and the second via is in contact with a topmost segment of the field plate along the second direction; and a metal line disposed above and contacting both the first via and the second via along the second direction, wherein the first via spans a first height along the second direction, the second via spans a second height along the second direction, the step-wise structure spans a third height along the second direction, and the first height is greater than the sum of the second height and the third height.
The semiconductor structure of claim 13, wherein the first via includes a bottom surface and a top surface along the second direction; the second via includes a bottom surface and a top surface along the second direction; the metal line includes a bottom surface and a top surface along the second direction; the bottom surface of the metal line contacts the top surface of the first via and the top surface of the second via; the step-wise structure includes a top surface being copla-nar with the bottom surface of the second via along the second direction; the bottom surface of the second via spans a first lateral dimension along the first direction; the top surface of the third segment spans a second lateral dimension along the first direction; the second lateral dimension is greater than the first lateral dimension; and the step-wise structure is only electrically connected to the metal line through the second via.
A semiconductor structure, comprising: a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer, wherein the gate stack includes a junction isolation feature and a metal layer disposed on the junction isolation feature; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; a field plate embedded in the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure, wherein the step-wise structure includes a first segment extending horizontally along a first direction, a second segment extending vertically from the first segment along a second direction being perpendicular to the first direc-tion, and a third segment extending horizontally from the second segment along the first direction, wherein the AlGaN layer is above and contacts the GaN layer along the second direction, the gate stack is above and contacts the AlGaN layer, and wherein the third seg-ment is above the first segment along the second direction; a first via embedded in the dielectric material layer, vertically landing on the source feature, and having a top surface and a bottom surface along the second direction; a second via embedded in the dielectric material layer, vertically landing on the third segment, and having a top surface and a bottom surface along the second direction; and a metal line disposed on a top surface of the dielectric material layer along the second direction, and contact-ing the top surface of the first via and the top surface of the second via, wherein the first via spans a first height along the second direction, the second via spans a second height along the second direction, the step-wise structure spans a third height along the second direction, and the first height is greater than the sum of the second height and the third height.
The semiconductor structure of claim 16, wherein a top surface of the third segment is coplanar with a bottom surface of the second via; the bottom surface of the second via spans a first lateral dimension along the first direction; the top surface of the third segment spans a second lateral dimension along the first direction; the second lateral dimension is greater than the first lateral dimension; the step-wise structure is only electrically connected to the metal line through the second via; and the metal line is overlapped with the first via and the second via in a top view.
The semiconductor structure of claim 16, wherein the first via spans between the source feature and the metal line along the second direction; the second via spans between the third segment and the metal line along the second direction; and a bottom surface of the first via is below a bottom surface of the first segment along the second direction.
The semiconductor structure of claim 16, wherein the junction isolation feature includes two p-type doped GaN layers and two n-type doped GaN layers alterna-tively stacked; each of the two p-type doped GaN layers is doped with an impurity selected from the group consisting of magne-sium, calcium, zinc, beryllium, and carbon; and each of the two n-type doped GaN layers is doped with an impurity selected from the group consisting of silicon and oxygen.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT with step-wise field plate (claims 1–12, 20)
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
aluminum gallium nitride (AlGaN) layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1a is a sectional view of a semiconductor structure having a gallium nitride (GaN)-based transistor constructed in accordance with some embodiments;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–10 µm | — |
Thickness | 5–50 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,501,644 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1a is a sectional view of a semiconductor structure having a gallium nitride (GaN)-based transistor constructed in accordance with some embodiments;
FIGS. 2b, through 8b are schematic views of the semi- 50 conductor structure of
FIG. 3a. In
FIG. 4a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 55 138a …
FIG. 5a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 138a is …
FIG. 6a. A diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132 for isolation to prevent gate leakage. In another embodiment illustrated in
FIG. 7a. One diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132. Another diode 138f is formed between the p-GaN layer 130 and the n-GaN …
FIG. 8a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG 10 channel is defined between the source and drain. A diode 138e …
FIG. 9 is a sectional view of a semiconductor structure having a GaN-based transistor constructed in accordance 55 with some embodiments;
FIG. 10 is a sectional view of a semiconductor structure having a gallium nitride GaN-based transistor constructed in accordance with some embodiments;
FIG. 11 is a flowchart of a method making a semicon- 60 ductor structure, such as those of
FIGS. 12 through 19 are sectional views of a semicon- ductor structure (such as those of
FIG. 13, a first dielectric layer 150 is formed on the III-V semiconductor compound-based device by deposition, such as CVD, flowable CVD (CVD), spin coat- ing, …
FIG. 14, a first dielectric layer 150 is pat- terned to form a trench 160 in the first dielectric layer 150. The operation for patterning the first dielectric …
FIG. 15, a conductive layer 148 is deposited on the first dielectric layer 150 and in the trench 160 of the first dielectric layer 150 by a suitable deposition, …
FIG. 16, the conductive layer 148 is pat- terned to form a field plate, also being labeled as 148. The field plate 148 has a step-wise structure. The patterning …
FIG. 17, the second dielectric layer 156 is patterned to form trenches 162 and 164 to at least partially expose the source feature 120Aand the field plate 148 …
FIG. 18, one or more conductive material layer 166 is deposited in the trenches 162 and 164 and on the second dielectric layer 156 by a suitable deposition, …
FIG. 19, the conductive material layer 166 is patterned to form the conductive features 152 and 154, by a procedure that includes a lithography process and …
FIGS. 20 through 24 are sectional views of a semicon- ductor structure (such as those of
FIG. 21. The conductive feature 152 is formed by a process that includes patterning the second dielectric layer 156 to form a trench 162, as illustrated in
FIG. 22; depositing a conductive 45 material layer 166 on the second dielectric layer 156 and in the trench 162 by a suitable deposition method, as illustrated …
FIG. 23; and performing a patterning process to the conductive material layer 166 to form the conductive feature 152, as illustrated in
FIG. 24. 50
FIGS. 25 through 27 are sectional views of a semicon- ductor structure at various fabrication stages according to various embodiments; and
FIG. 26. Thereafter, the operations 208-212 are performed to form the field plate 148 as illustrated in
FIG. 27. In alter- B₂ native embodiments, the semiconductor structure 100 is a two-terminal device without the gate stack 122 but the field plate has a …
FIG. 28 is a diagrammatic view of various characteristic data of the gallium nitride GaN-based device according to some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a gallium nitride (GaN) layer on a substrate and having a top surface with a plane normal direction oriented from the substrate to the GaN layer; an aluminum gallium nitride (AlGaN) layer disposed on the top surface of the GaN layer along the plane normal direction; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a first dielectric material layer disposed on the gate stack; a field plate disposed on the first dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure, wherein the step-wise structure includes a first segment extending horizontally along a first direction being perpendicular to the plane normal direction, a second segment extending vertically from the first segment along the plane normal direction, and a third segment extending horizontally from the second segment along the first direction, and wherein the third segment is above the first segment along the plane normal direc-tion; a second dielectric material layer disposed on both the first dielectric material layer and the field plate; a first via on the source feature; a second via embedded in the second dielectric material layer and on the third segment of the field plate; and a metal line disposed on a topmost surface of the second dielectric material layer and above both the first and second vias along the plane normal direction and contacting both the first via and the second via, wherein the first via spans a first height along the plane normal direction, the second via spans a second height along the plane normal direction, the step-wise structure spans a third height along the plane normal direction, and the first height is greater than the sum of the second height and the third height.
The semiconductor structure of claim 1, wherein the second via includes a bottom surface and a top surface along the plane normal direction; the third segment includes a top surface being coplanar with the bottom surface of the second via; the metal line includes a bottom surface being coplanar with the top surface of the second via; the bottom surface of the second via spans a first lateral dimension along the first direction; the top surface of the third segment spans a second lateral dimension along the first direction; the second lateral dimension is greater than the first lateral dimension; and the step-wise structure is only electrically connected to the metal line through the second via.
The semiconductor structure of claim 1, wherein the gate stack includes a III-V compound p-type doped layer.
The semiconductor structure of claim 1, wherein the first via spans between the source feature and the metal line along the plane normal direction; and the second via spans between the third segment and the metal line along plane normal direction.
The semiconductor structure of claim 1, wherein the first via includes a bottom surface and a top surface along the plane normal direction; the first via includes a sidewall surface extending from the top surface to the bottom surface; and the sidewall surface of the first via is fully surrounded by the first and second dielectric material layers.
The semiconductor structure of claim 1, wherein the GaN layer is undoped or unintentionally doped.
The semiconductor structure of claim 1, wherein the source feature, the drain feature, and the gate stack are configured with the GaN layer and the AlGaN layer to form 45 a high electron mobility transistor.
The semiconductor structure of claim 1, wherein the top surface of the second dielectric material layer is above a topmost surface of the field plate along the plane normal direction; and the first via extending from the top surface of the dielec-tric layer to the source feature along the plane normal direction. ∗ ∗ ∗ ∗ ∗
A semiconductor structure, comprising: a first III-V compound layer on a substrate; a second III-V compound layer on the first III-V com-pound layer, the second III-V compound layer being different from the first III-V compound layer in com-position and further including aluminum; a gate stack on the second III-V compound layer; a source feature and a drain feature disposed on the second III-V compound layer; 55 a first via and a second via; a field plate disposed over the gate stack and electrically connected to the source feature by way of the first via and the second via, wherein the field plate includes at least three segments with a step-wise structure, and wherein the first via is on the source feature, wherein the step-wise structure includes a first segment extend-ing horizontally along a first direction, a second seg-ment extending vertically from the first segment along a second direction being perpendicular to the first direction, and a third segment extending horizontally from the second segment along the first direction, B₂ wherein the second III-V compound layer is directly on the second III-V compound layer along the second direction, and wherein the third segment is above the first segment along the second direction and the second via is in contact with a topmost segment of the field plate along the second direction; and a metal line disposed above and contacting both the first via and the second via along the second direction, wherein the first via spans a first height along the second direction, the second via spans a second height along the second direction, the step-wise structure spans a third height along the second direction, and the first height is greater than the sum of the second height and the third height.
The semiconductor structure of claim 13, wherein the first via includes a bottom surface and a top surface along the second direction; the second via includes a bottom surface and a top surface along the second direction; the metal line includes a bottom surface and a top surface along the second direction; the bottom surface of the metal line contacts the top surface of the first via and the top surface of the second via; the step-wise structure includes a top surface being copla-nar with the bottom surface of the second via along the second direction; the bottom surface of the second via spans a first lateral dimension along the first direction; the top surface of the third segment spans a second lateral dimension along the first direction; the second lateral dimension is greater than the first lateral dimension; and the step-wise structure is only electrically connected to the metal line through the second via.
A semiconductor structure, comprising: a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer, wherein the gate stack includes a junction isolation feature and a metal layer disposed on the junction isolation feature; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; a field plate embedded in the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure, wherein the step-wise structure includes a first segment extending horizontally along a first direction, a second segment extending vertically from the first segment along a second direction being perpendicular to the first direc-tion, and a third segment extending horizontally from the second segment along the first direction, wherein the AlGaN layer is above and contacts the GaN layer along the second direction, the gate stack is above and contacts the AlGaN layer, and wherein the third seg-ment is above the first segment along the second direction; a first via embedded in the dielectric material layer, vertically landing on the source feature, and having a top surface and a bottom surface along the second direction; a second via embedded in the dielectric material layer, vertically landing on the third segment, and having a top surface and a bottom surface along the second direction; and a metal line disposed on a top surface of the dielectric material layer along the second direction, and contact-ing the top surface of the first via and the top surface of the second via, wherein the first via spans a first height along the second direction, the second via spans a second height along the second direction, the step-wise structure spans a third height along the second direction, and the first height is greater than the sum of the second height and the third height.
The semiconductor structure of claim 16, wherein a top surface of the third segment is coplanar with a bottom surface of the second via; the bottom surface of the second via spans a first lateral dimension along the first direction; the top surface of the third segment spans a second lateral dimension along the first direction; the second lateral dimension is greater than the first lateral dimension; the step-wise structure is only electrically connected to the metal line through the second via; and the metal line is overlapped with the first via and the second via in a top view.
The semiconductor structure of claim 16, wherein the first via spans between the source feature and the metal line along the second direction; the second via spans between the third segment and the metal line along the second direction; and a bottom surface of the first via is below a bottom surface of the first segment along the second direction.
The semiconductor structure of claim 16, wherein the junction isolation feature includes two p-type doped GaN layers and two n-type doped GaN layers alterna-tively stacked; each of the two p-type doped GaN layers is doped with an impurity selected from the group consisting of magne-sium, calcium, zinc, beryllium, and carbon; and each of the two n-type doped GaN layers is doped with an impurity selected from the group consisting of silicon and oxygen.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT with step-wise field plate (claims 1–12, 20)
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
aluminum gallium nitride (AlGaN) layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1a is a sectional view of a semiconductor structure having a gallium nitride (GaN)-based transistor constructed in accordance with some embodiments;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–10 µm | — |
Thickness | 5–50 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Related documents with shared materials, methods, properties, or citations.
GaN-based device with step-wise field plate using generic III-V compound layers (claims 13–15)
GaN-based HEMT with embedded step-wise field plate and junction isolation gate stack (claims 16–19)
first III-V compound layer
second III-V compound layer (aluminum-containing)
FIG. 4a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 55 138a …
FIG. 5a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 138a is …
FIG. 6a. A diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132 for isolation to prevent gate leakage. In another embodiment illustrated in
FIG. 7a. One diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132. Another diode 138f is formed between the p-GaN layer 130 and the n-GaN …
FIG. 8a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG 10 channel is defined between the source and drain. A diode 138e …
FIG. 9 is a sectional view of a semiconductor structure having a GaN-based transistor constructed in accordance 55 with some embodiments;
FIG. 10 is a sectional view of a semiconductor structure having a gallium nitride GaN-based transistor constructed in accordance with some embodiments;
FIG. 13, a first dielectric layer 150 is formed on the III-V semiconductor compound-based device by deposition, such as CVD, flowable CVD (CVD), spin coat- ing, …
| — |
Temperature | 800–900 °C | — |
Thickness | 1–100 nm | — |
Thickness | 3–100 nm | — |
Thickness | 0.25–5 µm | — |
Thickness | 30–500 nm | — |
GaN-based device with step-wise field plate using generic III-V compound layers (claims 13–15)
GaN-based HEMT with embedded step-wise field plate and junction isolation gate stack (claims 16–19)
first III-V compound layer
second III-V compound layer (aluminum-containing)
FIG. 4a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 55 138a …
FIG. 5a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 138a is …
FIG. 6a. A diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132 for isolation to prevent gate leakage. In another embodiment illustrated in
FIG. 7a. One diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132. Another diode 138f is formed between the p-GaN layer 130 and the n-GaN …
FIG. 8a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG 10 channel is defined between the source and drain. A diode 138e …
FIG. 9 is a sectional view of a semiconductor structure having a GaN-based transistor constructed in accordance 55 with some embodiments;
FIG. 10 is a sectional view of a semiconductor structure having a gallium nitride GaN-based transistor constructed in accordance with some embodiments;
FIG. 13, a first dielectric layer 150 is formed on the III-V semiconductor compound-based device by deposition, such as CVD, flowable CVD (CVD), spin coat- ing, …
| — |
Temperature | 800–900 °C | — |
Thickness | 1–100 nm | — |
Thickness | 3–100 nm | — |
Thickness | 0.25–5 µm | — |
Thickness | 30–500 nm | — |
GaN-based device with step-wise field plate using generic III-V compound layers (claims 13–15)
GaN-based HEMT with embedded step-wise field plate and junction isolation gate stack (claims 16–19)
first III-V compound layer
second III-V compound layer (aluminum-containing)
FIG. 4a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 55 138a …
FIG. 5a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 138a is …
FIG. 6a. A diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132 for isolation to prevent gate leakage. In another embodiment illustrated in
FIG. 7a. One diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132. Another diode 138f is formed between the p-GaN layer 130 and the n-GaN …
FIG. 8a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG 10 channel is defined between the source and drain. A diode 138e …
FIG. 9 is a sectional view of a semiconductor structure having a GaN-based transistor constructed in accordance 55 with some embodiments;
FIG. 10 is a sectional view of a semiconductor structure having a gallium nitride GaN-based transistor constructed in accordance with some embodiments;
FIG. 13, a first dielectric layer 150 is formed on the III-V semiconductor compound-based device by deposition, such as CVD, flowable CVD (CVD), spin coat- ing, …
| — |
Temperature | 800–900 °C | — |
Thickness | 1–100 nm | — |
Thickness | 3–100 nm | — |
Thickness | 0.25–5 µm | — |
Thickness | 30–500 nm | — |
GaN-based device with step-wise field plate using generic III-V compound layers (claims 13–15)
GaN-based HEMT with embedded step-wise field plate and junction isolation gate stack (claims 16–19)
first III-V compound layer
second III-V compound layer (aluminum-containing)
FIG. 4a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 55 138a …
FIG. 5a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG channel is defined between the source and drain. A diode 138a is …
FIG. 6a. A diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132 for isolation to prevent gate leakage. In another embodiment illustrated in
FIG. 7a. One diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132. Another diode 138f is formed between the p-GaN layer 130 and the n-GaN …
FIG. 8a. Symbols “G”, “S”, and “D” represent gate, source, and drain, respectively. The 2-DEG 10 channel is defined between the source and drain. A diode 138e …
FIG. 9 is a sectional view of a semiconductor structure having a GaN-based transistor constructed in accordance 55 with some embodiments;
FIG. 10 is a sectional view of a semiconductor structure having a gallium nitride GaN-based transistor constructed in accordance with some embodiments;
FIG. 13, a first dielectric layer 150 is formed on the III-V semiconductor compound-based device by deposition, such as CVD, flowable CVD (CVD), spin coat- ing, …
| — |
Temperature | 800–900 °C | — |
Thickness | 1–100 nm | — |
Thickness | 3–100 nm | — |
Thickness | 0.25–5 µm | — |
Thickness | 30–500 nm | — |
