ENHANCEMENT-MODE GaN TRANSISTOR WITH SELECTIVE AND NONSELECTIVE

Jianjun Cao

Patent

Atlas literature

Patent

US 10,622,455

ENHANCEMENT-MODE GaN TRANSISTOR WITH SELECTIVE AND NONSELECTIVE

Jianjun Cao, Robert Beach, Guangyuan Zhao, Yoga Saripalli et al.

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1 illustrates a cross-sectional view of a conventional FET. [0015]

FIG. 2

FIG. 2 illustrates a cross-se c tional view of a conventional step in formation of a typical enhancement-mode GaN HEMT device. #109042533 SVG …

FIG. 3

FIG. 3 illustrates a cross-sectional view of a conventional step in formation of a typical enhancement-mode GaN transistor device. [0017]

FIG. 4

FIG. 4 illustrates a cross-sectional view of a conventional depletion-mode HEMT FET. [0018]

FIG. 5

FIG. 5 illustrates a cross-sectional view of an enhancement-mode transistor structure formed according to a ﬁrst embodiment of the present invention. [0019]

FIG. 6

FIG. 6 illustrates a cross-sectional view of the starting gate structure in an exemplary process ﬂow for fabricating the enhancement-mode transistor structure …

FIG. 7

FIG. 7 illustrates a cross-sectional view of the gate structure after a ﬁrst etch in the process for fabricating the enhancement-mode transistor structure …

FIG. 8

FIG. 8 illustrates a cross-sectional view of the gate structure after a second etch in the process for fabricating the enhancement-mode transistor structure …

FIG. 9

FIG. 9 illustrates a cross-sectional view of an enhancement-mode transistor structure formed according to a second embodiment of the present invention. [0023]

FIG. 10

FIG. 10 illustrates a cross-sectional view of an enhancement-mode transistor structure formed according to a third embodiment of the present invention. [0024]

FIG. 11

FIG. 11 illustrates a cross-sectional view of an enhancement-m o de transistor structure formed according to a fourth embodiment of the present invention. …

FIG. 12

FIG. 12 illustrates a cross-sectional view of an enhancement-mode transistor structure formed according to a ﬁfth embodiment of the present invention. …

FIG. 13

FIG. 13. The material 508 above the etch stop layer 507 and the material 506 below the etch stop layer 507 may be pGa N, pAl GaN, or pAlInGaN, and their Al …

FIG. 14

FIGS. 14 and 15, and pAlInGaN layers 537, 557 in

FIG. 15

FIG. 15). #109042533 SVG 16006981.06-13-2018.JID₈₈FA₀RXEAPX4.SPEC.10.29.1309.2932.1330.2967.svg 0.117 0.07 Chemistry Black and white [0043] The method steps in …

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

3 independent · 8 dependent

1
Independent
Claims 1-9. (Cancel ed) Canceled
9
Independent
Canceled
10
IndependentGaNGaN:pAlGaN:pAlGaNenhancement-mode GaN transistor gate structure
A method of forming a transistor with a uniform spacer layer in areas surrounding the transistor gate, comprising: providing a transistor gate structure comprising: a barrier layer; a spacer layer disposed above the barrier layer, the spacer layer comprising a column I1l -V material; a ﬁrst layer comprising p-type or compensated column I I -V material disposed above the spacer layer; an etch stop layer comprising a p-type Al-containing column I II -V material disposed above the spacer layer and the ﬁrst layer comprising p-type or compensated column I ll-V material; and a second layer comprising p-type or compensated column I Il -V material positioned above the etch stop layer, the second layer comprising p-type or compensated column I ll-V material being thicker than the ﬁrst layer comprising p-type or compensated column I Il-V material; positioning a mask over a gate region of the second layer comprising p-type or compensated column I I -V material; performing a ﬁrst etch of the second layer comprising p-type or compensated column I ll-V material outside the gate region with an etch recipe that is selective to the p-type A l- containing column I II -V material of the etch stop layer, such that the etch stops on the etch stop layer; performing a second etch through the mask with an etch recipe that is nonselective to the p- type Al-containing column I Il -V material of the etch stop layer, such that the etch stop layer and the ﬁrst layer comprising p-type or compensated column I II -V material are completely etched outside the gate region covered by the mask, and the entire spacer layer outside the gate region covered by the mask is partially and uniformly etched e g g y. Currently amended
1. 11
  Dependent← claim 10GaN
  The method of claim 10, wherein the spacer layer comprises GaN. Original
2. 12
  Dependent← claim 10GaN:p
  The method of claim 10, wherein the ﬁrst and second layers of p-type or compensated column III -V material comprise pGaN. Original
3. 13
  Dependent← claim 10AlGaN:pAlInGaN:p
  The method of claim 10, wherein the etch stop layer comprises pAlGaN or pAlInGaN. Original
4. 15
  Dependent← claim 10GaNGaN:pAlGaN:p
  The method of claim 10, wherein the spacer layer has a thickness of 1 nim-6 nm, the ﬁrst layer comprising p-type or compensated column I Il -V material has a thickness of 1 nm⁻³⁰ nm, the etch stop layer has a thickness of 0.5 ni m-2 nm, and the second layer comprising p-type or compensated column III -V material has a thickness of 20 nm⁻¹⁰⁰ nm. Original
5. 16
  Dependent← claim 10GaN
  The method of claim 10, wherein the second etch results in the spacer layer being thicker in the gate region than outside the gate region, and the thickness of the spacer layer outside the gate region is substantially uniform. Original
6. 17
  Dependent← claim 10AlGaN:p
  The method of claim 10, further comprising an additional etch stop layer disposed above the second layer comprising p-type or compensated column I II -V material, and an additional layer of p-type or compensated column I II -V material disposed above the additional etch stop layer, wherein the thickness of the structure between the than the thickness of the structure between the and wherein an additional etch is performed for graduated etching. Original

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

enhancement-mode GaN transistor gate structure

GaN:psecond p-type layer

AlGaN:petch stop layer

GaN:pfirst p-type layer

GaNspacer layer

AlGaNbarrier layer

Materials

Materials described outside the worked examples.

GaN spacer layer

GaN

Spacer Layer

pGaN

GaN:p

P-Type Gate Layer

Process steps

Additional fabrication and treatment steps described in the patent.

Selective Etch

Step 1

Process details

description:First etch of second p-type or compensated column III-V layer outside the gate region using an etch recipe selective to the p-type Al-containing column III-V etch stop layer; etch stops on the etch stop layer

Materials:GaN:pAlGaN:p

Characterization

Measurements and analyses referenced in the patent, with their drawing references.

fet electrical

Fet Electrical

FIG. 1 illustrates a cross-sectional view of a conventional FET. [0015]

Figure references

FIG. 1

fet electrical

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
GaN spacer layer thickness (claimed range)	1–6 nm	GaN
first pGaN layer thickness (claimed range)	1–30 nm

Why these are connected

Related documents with shared materials, methods, properties, or citations.

ENHANCEMENT-MODE GaN TRANSISTOR WITH SELECTIVE AND NONSELECTIVE | Matter42 Literature