Patent
US 10,854,727HIGH POWER GALLIUM NITRIDE ELECTRONICS USING MISCUT SUBSTRATES
Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
Nexgen Power Systems, Inc.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,854,727Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 O C is a simplified schematic diagram illustrating a lateral p-n junction displaced from a regrowth interface with an underfilled regrowth profile …
FIG. 2B. It should be noted that the example illustrated in
FIG. 3B is a Nomarski micrograph of epitaxial surface, for case when substrate misorientation is > 0.65 °. As illustrated in
FIG. 4A, it should also be noted that good surface morphology can also be obtained by adjusting both the misorientation with respect to the a-direction and the …
FIG. 5 A is a plot showing the forward bias current-voltage characteristics of a high voltage PN diode according to an embodiment of the present invention. …
FIG. 6 is a plot showing the reverse bias current-voltage characteristics of a high- voltage GaN PN diode according to an embodiment of the present invention …
FIG. 7 is a simplified flowchart illustrating a method of fabricating an electronic device according to an embodiment of the present invention. Referring to
FIG. 8B, the m -planes of a Wurtzite crystal are illustrated. The c-axis (0001) is normal to the plane of the figures and the (000-1) axis points into the plane …
FIG. 9B, the diffusion of the acceptor drives the p-n junction, which would have been located in the vicinity of the regrowth interface, into the bulk. …
FIG. 10 A. For the embodiment illustrated in FIG. lO B, an in-situ etch process was utilized prior to regrowth, producing undercutting under the etch mask and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
. Canceled
A field effect transistor comprising: a I II -V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <000 1> direction towards the < 1100> direction by an angle ranging between -0.3° and -0.6° and towards the < 1120> direction by an angle ranging between-0.1V and -0.2°; a first epitaxial layer coupled to the I II -V substrate; a second epitaxial layer coupled to the first epitaxial layer; one or more recessed regions extending into the second epitaxial layer, wherein each of the one or more recessed regions defines a sidewall surface in the second epitaxial layer and a lateral surface, wherein a doped region extends into the sidewall surface and the lateral surface; a drain contact in electrical contact with the I II -V substrate; a source contact in electrical contact with the second epitaxial layer; and a gate contact in electrical contact with the doped region. New
The field effect transistor of claim 2 wherein the I II -V substrate comprises an n-type GaN substrate. New
The field effect transistor of claim 2 wherein the first epitaxial layer comprises an n-type GaN epitaxial layer and the second epitaxial layer comprises an n-type GaN epitaxial layer. New
The field effect transistor of claim 2 wherein the doped region comprises a diffused region. New
The field effect transistor of claim 2 wherein the doped region comprises zinc. New
The field effect transistor of claim 2 wherein the doped region comprises magnesium. New
The field effect transistor of claim 2 wherein the doped region comprises beryllium. New
The field effect transistor of claim 2 wherein the doped region comprises calcium. New
The field effect transistor of claim 2 wherein the first epitaxial layer has a thickness greater than 5 m. New
The field effect transistor of claim 2 wherein a dopant concentration in the first epitaxial layer varies as a function of a thickness of the first epitaxial layer. New
The field effect transistor of claim 2 wherein a dopant concentration in the second epitaxial layer varies as a function of a thickness of the second epitaxial layer. New
The field effect transistor of claim 2 wherein the doped region extends into the second epitaxial layer by a distance between about 1 nm and about 1 km. New
The field effect transistor of claim 2 wherein the lateral surface is substantially orthogonal to a growth direction of the first epitaxial layer. New
The field effect transistor of claim 2 wherein the sidewall surface is substantially parallel to a growth direction of the second epitaxial layer. New
The field effect transistor of claim 2 wherein the lateral surface is disposed in the second epitaxial layer. New
The field effect transistor of claim 2 further comprising an isolation region disposed laterally to the second epitaxial layer. New
Layer stacks claimed or described, ordered top of device to substrate.
field effect transistor
Materials described outside the worked examples.
III-V substrate (hexagonal, miscut)
first epitaxial layer
second epitaxial layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 O C is a simplified schematic diagram illustrating a lateral p-n junction displaced from a regrowth interface with an underfilled regrowth profile …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≤ 200 V | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,854,727Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 O C is a simplified schematic diagram illustrating a lateral p-n junction displaced from a regrowth interface with an underfilled regrowth profile …
FIG. 2B. It should be noted that the example illustrated in
FIG. 3B is a Nomarski micrograph of epitaxial surface, for case when substrate misorientation is > 0.65 °. As illustrated in
FIG. 4A, it should also be noted that good surface morphology can also be obtained by adjusting both the misorientation with respect to the a-direction and the …
FIG. 5 A is a plot showing the forward bias current-voltage characteristics of a high voltage PN diode according to an embodiment of the present invention. …
FIG. 6 is a plot showing the reverse bias current-voltage characteristics of a high- voltage GaN PN diode according to an embodiment of the present invention …
FIG. 7 is a simplified flowchart illustrating a method of fabricating an electronic device according to an embodiment of the present invention. Referring to
FIG. 8B, the m -planes of a Wurtzite crystal are illustrated. The c-axis (0001) is normal to the plane of the figures and the (000-1) axis points into the plane …
FIG. 9B, the diffusion of the acceptor drives the p-n junction, which would have been located in the vicinity of the regrowth interface, into the bulk. …
FIG. 10 A. For the embodiment illustrated in FIG. lO B, an in-situ etch process was utilized prior to regrowth, producing undercutting under the etch mask and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
. Canceled
A field effect transistor comprising: a I II -V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <000 1> direction towards the < 1100> direction by an angle ranging between -0.3° and -0.6° and towards the < 1120> direction by an angle ranging between-0.1V and -0.2°; a first epitaxial layer coupled to the I II -V substrate; a second epitaxial layer coupled to the first epitaxial layer; one or more recessed regions extending into the second epitaxial layer, wherein each of the one or more recessed regions defines a sidewall surface in the second epitaxial layer and a lateral surface, wherein a doped region extends into the sidewall surface and the lateral surface; a drain contact in electrical contact with the I II -V substrate; a source contact in electrical contact with the second epitaxial layer; and a gate contact in electrical contact with the doped region. New
The field effect transistor of claim 2 wherein the I II -V substrate comprises an n-type GaN substrate. New
The field effect transistor of claim 2 wherein the first epitaxial layer comprises an n-type GaN epitaxial layer and the second epitaxial layer comprises an n-type GaN epitaxial layer. New
The field effect transistor of claim 2 wherein the doped region comprises a diffused region. New
The field effect transistor of claim 2 wherein the doped region comprises zinc. New
The field effect transistor of claim 2 wherein the doped region comprises magnesium. New
The field effect transistor of claim 2 wherein the doped region comprises beryllium. New
The field effect transistor of claim 2 wherein the doped region comprises calcium. New
The field effect transistor of claim 2 wherein the first epitaxial layer has a thickness greater than 5 m. New
The field effect transistor of claim 2 wherein a dopant concentration in the first epitaxial layer varies as a function of a thickness of the first epitaxial layer. New
The field effect transistor of claim 2 wherein a dopant concentration in the second epitaxial layer varies as a function of a thickness of the second epitaxial layer. New
The field effect transistor of claim 2 wherein the doped region extends into the second epitaxial layer by a distance between about 1 nm and about 1 km. New
The field effect transistor of claim 2 wherein the lateral surface is substantially orthogonal to a growth direction of the first epitaxial layer. New
The field effect transistor of claim 2 wherein the sidewall surface is substantially parallel to a growth direction of the second epitaxial layer. New
The field effect transistor of claim 2 wherein the lateral surface is disposed in the second epitaxial layer. New
The field effect transistor of claim 2 further comprising an isolation region disposed laterally to the second epitaxial layer. New
Layer stacks claimed or described, ordered top of device to substrate.
field effect transistor
Materials described outside the worked examples.
III-V substrate (hexagonal, miscut)
first epitaxial layer
second epitaxial layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 O C is a simplified schematic diagram illustrating a lateral p-n junction displaced from a regrowth interface with an underfilled regrowth profile …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≤ 200 V | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,854,727Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 O C is a simplified schematic diagram illustrating a lateral p-n junction displaced from a regrowth interface with an underfilled regrowth profile …
FIG. 2B. It should be noted that the example illustrated in
FIG. 3B is a Nomarski micrograph of epitaxial surface, for case when substrate misorientation is > 0.65 °. As illustrated in
FIG. 4A, it should also be noted that good surface morphology can also be obtained by adjusting both the misorientation with respect to the a-direction and the …
FIG. 5 A is a plot showing the forward bias current-voltage characteristics of a high voltage PN diode according to an embodiment of the present invention. …
FIG. 6 is a plot showing the reverse bias current-voltage characteristics of a high- voltage GaN PN diode according to an embodiment of the present invention …
FIG. 7 is a simplified flowchart illustrating a method of fabricating an electronic device according to an embodiment of the present invention. Referring to
FIG. 8B, the m -planes of a Wurtzite crystal are illustrated. The c-axis (0001) is normal to the plane of the figures and the (000-1) axis points into the plane …
FIG. 9B, the diffusion of the acceptor drives the p-n junction, which would have been located in the vicinity of the regrowth interface, into the bulk. …
FIG. 10 A. For the embodiment illustrated in FIG. lO B, an in-situ etch process was utilized prior to regrowth, producing undercutting under the etch mask and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
. Canceled
A field effect transistor comprising: a I II -V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <000 1> direction towards the < 1100> direction by an angle ranging between -0.3° and -0.6° and towards the < 1120> direction by an angle ranging between-0.1V and -0.2°; a first epitaxial layer coupled to the I II -V substrate; a second epitaxial layer coupled to the first epitaxial layer; one or more recessed regions extending into the second epitaxial layer, wherein each of the one or more recessed regions defines a sidewall surface in the second epitaxial layer and a lateral surface, wherein a doped region extends into the sidewall surface and the lateral surface; a drain contact in electrical contact with the I II -V substrate; a source contact in electrical contact with the second epitaxial layer; and a gate contact in electrical contact with the doped region. New
The field effect transistor of claim 2 wherein the I II -V substrate comprises an n-type GaN substrate. New
The field effect transistor of claim 2 wherein the first epitaxial layer comprises an n-type GaN epitaxial layer and the second epitaxial layer comprises an n-type GaN epitaxial layer. New
The field effect transistor of claim 2 wherein the doped region comprises a diffused region. New
The field effect transistor of claim 2 wherein the doped region comprises zinc. New
The field effect transistor of claim 2 wherein the doped region comprises magnesium. New
The field effect transistor of claim 2 wherein the doped region comprises beryllium. New
The field effect transistor of claim 2 wherein the doped region comprises calcium. New
The field effect transistor of claim 2 wherein the first epitaxial layer has a thickness greater than 5 m. New
The field effect transistor of claim 2 wherein a dopant concentration in the first epitaxial layer varies as a function of a thickness of the first epitaxial layer. New
The field effect transistor of claim 2 wherein a dopant concentration in the second epitaxial layer varies as a function of a thickness of the second epitaxial layer. New
The field effect transistor of claim 2 wherein the doped region extends into the second epitaxial layer by a distance between about 1 nm and about 1 km. New
The field effect transistor of claim 2 wherein the lateral surface is substantially orthogonal to a growth direction of the first epitaxial layer. New
The field effect transistor of claim 2 wherein the sidewall surface is substantially parallel to a growth direction of the second epitaxial layer. New
The field effect transistor of claim 2 wherein the lateral surface is disposed in the second epitaxial layer. New
The field effect transistor of claim 2 further comprising an isolation region disposed laterally to the second epitaxial layer. New
Layer stacks claimed or described, ordered top of device to substrate.
field effect transistor
Materials described outside the worked examples.
III-V substrate (hexagonal, miscut)
first epitaxial layer
second epitaxial layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 O C is a simplified schematic diagram illustrating a lateral p-n junction displaced from a regrowth interface with an underfilled regrowth profile …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≤ 200 V | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,854,727Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 O C is a simplified schematic diagram illustrating a lateral p-n junction displaced from a regrowth interface with an underfilled regrowth profile …
FIG. 2B. It should be noted that the example illustrated in
FIG. 3B is a Nomarski micrograph of epitaxial surface, for case when substrate misorientation is > 0.65 °. As illustrated in
FIG. 4A, it should also be noted that good surface morphology can also be obtained by adjusting both the misorientation with respect to the a-direction and the …
FIG. 5 A is a plot showing the forward bias current-voltage characteristics of a high voltage PN diode according to an embodiment of the present invention. …
FIG. 6 is a plot showing the reverse bias current-voltage characteristics of a high- voltage GaN PN diode according to an embodiment of the present invention …
FIG. 7 is a simplified flowchart illustrating a method of fabricating an electronic device according to an embodiment of the present invention. Referring to
FIG. 8B, the m -planes of a Wurtzite crystal are illustrated. The c-axis (0001) is normal to the plane of the figures and the (000-1) axis points into the plane …
FIG. 9B, the diffusion of the acceptor drives the p-n junction, which would have been located in the vicinity of the regrowth interface, into the bulk. …
FIG. 10 A. For the embodiment illustrated in FIG. lO B, an in-situ etch process was utilized prior to regrowth, producing undercutting under the etch mask and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
. Canceled
A field effect transistor comprising: a I II -V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <000 1> direction towards the < 1100> direction by an angle ranging between -0.3° and -0.6° and towards the < 1120> direction by an angle ranging between-0.1V and -0.2°; a first epitaxial layer coupled to the I II -V substrate; a second epitaxial layer coupled to the first epitaxial layer; one or more recessed regions extending into the second epitaxial layer, wherein each of the one or more recessed regions defines a sidewall surface in the second epitaxial layer and a lateral surface, wherein a doped region extends into the sidewall surface and the lateral surface; a drain contact in electrical contact with the I II -V substrate; a source contact in electrical contact with the second epitaxial layer; and a gate contact in electrical contact with the doped region. New
The field effect transistor of claim 2 wherein the I II -V substrate comprises an n-type GaN substrate. New
The field effect transistor of claim 2 wherein the first epitaxial layer comprises an n-type GaN epitaxial layer and the second epitaxial layer comprises an n-type GaN epitaxial layer. New
The field effect transistor of claim 2 wherein the doped region comprises a diffused region. New
The field effect transistor of claim 2 wherein the doped region comprises zinc. New
The field effect transistor of claim 2 wherein the doped region comprises magnesium. New
The field effect transistor of claim 2 wherein the doped region comprises beryllium. New
The field effect transistor of claim 2 wherein the doped region comprises calcium. New
The field effect transistor of claim 2 wherein the first epitaxial layer has a thickness greater than 5 m. New
The field effect transistor of claim 2 wherein a dopant concentration in the first epitaxial layer varies as a function of a thickness of the first epitaxial layer. New
The field effect transistor of claim 2 wherein a dopant concentration in the second epitaxial layer varies as a function of a thickness of the second epitaxial layer. New
The field effect transistor of claim 2 wherein the doped region extends into the second epitaxial layer by a distance between about 1 nm and about 1 km. New
The field effect transistor of claim 2 wherein the lateral surface is substantially orthogonal to a growth direction of the first epitaxial layer. New
The field effect transistor of claim 2 wherein the sidewall surface is substantially parallel to a growth direction of the second epitaxial layer. New
The field effect transistor of claim 2 wherein the lateral surface is disposed in the second epitaxial layer. New
The field effect transistor of claim 2 further comprising an isolation region disposed laterally to the second epitaxial layer. New
Layer stacks claimed or described, ordered top of device to substrate.
field effect transistor
Materials described outside the worked examples.
III-V substrate (hexagonal, miscut)
first epitaxial layer
second epitaxial layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 O C is a simplified schematic diagram illustrating a lateral p-n junction displaced from a regrowth interface with an underfilled regrowth profile …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≤ 200 V | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
n-type GaN substrate
GaN
zinc dopant
Zn
magnesium dopant
Mg
beryllium dopant
Be
calcium dopant
Ca
FIG. 9B, the diffusion of the acceptor drives the p-n junction, which would have been located in the vicinity of the regrowth interface, into the bulk. …
| — |
Voltage | ≥ 600 V | — |
Voltage | ≥ 1200 V | — |
Voltage | ≥ 1700 V | — |
Voltage | ≥ 200 V | — |
n-type GaN substrate
GaN
zinc dopant
Zn
magnesium dopant
Mg
beryllium dopant
Be
calcium dopant
Ca
FIG. 9B, the diffusion of the acceptor drives the p-n junction, which would have been located in the vicinity of the regrowth interface, into the bulk. …
| — |
Voltage | ≥ 600 V | — |
Voltage | ≥ 1200 V | — |
Voltage | ≥ 1700 V | — |
Voltage | ≥ 200 V | — |
n-type GaN substrate
GaN
zinc dopant
Zn
magnesium dopant
Mg
beryllium dopant
Be
calcium dopant
Ca
FIG. 9B, the diffusion of the acceptor drives the p-n junction, which would have been located in the vicinity of the regrowth interface, into the bulk. …
| — |
Voltage | ≥ 600 V | — |
Voltage | ≥ 1200 V | — |
Voltage | ≥ 1700 V | — |
Voltage | ≥ 200 V | — |
n-type GaN substrate
GaN
zinc dopant
Zn
magnesium dopant
Mg
beryllium dopant
Be
calcium dopant
Ca
FIG. 9B, the diffusion of the acceptor drives the p-n junction, which would have been located in the vicinity of the regrowth interface, into the bulk. …
| — |
Voltage | ≥ 600 V | — |
Voltage | ≥ 1200 V | — |
Voltage | ≥ 1700 V | — |
Voltage | ≥ 200 V | — |