Patent
US 9,318,331METHOD AND SYSTEM FOR DIFFUSION AND IMPLANTATION IN GALLIUM NITRIDE BASED DEVICES
David P. Bour
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,318,331Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic diagram illustrating a conventional Schottky barrier diode. The cross section illustrated in
FIG. 2 is a simplified schematic diagram illustrating a conventional p-n junction diode. 5 The cross section illustrated in
FIG. 3A. The ammonia provides a source of active nitrogen species to counteract the 5 decomposition of the GaN material during the diffusion process resulting …
FIGS. 4A-4C are simplified process flow diagrams illustrating a solid-source diffusion 10 process according to an embodiment of the present invention. The …
FIG. 5A, an n-type doped GaN substrate 501 is implanted with an acceptor species (e.g., zin c, magnesium, beryllium, or the like) in implanted region 502. An …
FIGS. 6A-6 B are simplified process flow diagrams illustrating an ion implantation 25 process using a sacrificial layer according to an embodiment of the present …
FIG. 7C, lateral p-n junctions can thus be formed using this implantation process utilizing a sacrificial layer formed after the ion- implantation process. …
FIG. 8 is a simplified schematic diagram of a vertical junction field effect transistor 800 according to an embodiment of the present invention. The illustrated …
FIG. 9 is a simplified schematic diagram of a Schottky barri er diode according to an embodiment of the present invention. The Schottky ba rri er diode …
FIG. 10 is a simplified schematic diagram of a p-i-n diode according to an embodiment of the present invention. The p-i-n diode 1000 includes an n-type doped …
FIG. 11 is a simplified schematic diagram of a junction barrier Schottky (JBS) diode 1100 according to an embodiment of the present invention. The JBS diode …
FIG. 12 is a simplified flowchart illustrating a method of fabricating a vertical junction 15 field effect transistor according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a doped region in a I II -nitride substrate, the method comprising: providing the I II -nitride substrate, wherein the I II -nitride substrate is characterized by a first conductivity type; forming a masking layer having a predetermined pattern, wherein the predetermined pattern defines exposed regions of the I II -nitride substrate; placing the exposed regions of the I II -nitride substrate in a dual-precursor gas comprising both a chemically reactive nitrogen source and a dopant source; while the exposed regions of the III -nitride substrate are exposed to the chemically reactive nitrogen source and the dopant source of the dual-precursor gas, implanting the dopant from the dopant source of the dual-precursor gas into the exposed regions of the III- nitride substrate, wherein, while the dopant is implanted into the exposed regions, the chemically reactive nitrogen source counteracts the effects of nitrogen escaping from the III -nitride substrate; and removing the masking layer.
The method of claim 1, wherein the I II -nitride substrate comprises an n-type GaN substrate.
The method of claim 1, wherein the masking layer comprises a refractory material.
The method of claim 1, wherein a temperature of the dual-precursor gas is between about 800 ° C to about 1800 °C.
The method of claim 1, wherein the dual-precursor gas includes ammonia and an acceptor species.
The method of claim 1, wherein placing the exposed regions of the I II -nitride substrate in the dual-precursor gas comprises: positioning the I II -nitride substrate in a chamber; and flowing the dual-precursor gas including both the nitrogen source and the dopant source through the chamber.
The method of claim 1, wherein implanting the dopant into the III -nitride substrate comprises diffusing the dopant into the I II -nitride substrate.
A method of forming a doped region in a I II -nitride substrate, the method comprising: providing the III -nitride substrate, wherein the III -nitride substrate is characterized by a first conductivity type; forming a masking layer having a predetermined pattern, wherein the predetermined pattern defines predetermined portions of the III -nitride substrate; placing the I II-nitride substrate in a chamber; forming an environment in the chamber, wherein the environment comprises a dual-precursor gas including both a chemically reactive nitrogen source and a dopant source, wherein the dopant is characterized by a second conductivity type; exposing the predetermined portions of the III -nitride substrate to the chemically reactive nitrogen source and the dopant source of the dual-precursor gas; while the predetermined portions of the III -nitride substrate are exposed to the chemically reactive nitrogen source and the dopant source of the dual-precursor gas, implanting the dopant into the predetermined portions of the III -nitride substrate; while the predetermined portions of the III -nitride substrate are exposed to the chemically reactive nitrogen source, with the chemically reactive nitrogen source, counteracting the effects of nitrogen escaping from the III -nitride substrate; and removing the masking layer.
The method of claim 9, wherein the chamber comprises an MOC V D reactor.
The method of claim 9, wherein the chamber comprises an annealing furnace.
The method of claim 9, wherein the I II -nitride substrate comprises an n-type GaN substrate.
The method of claim 9, wherein the masking layer comprises a refractory material.
The method of claim 9, wherein removing the masking layer is performed prior to placing the I II -nitride substrate in the chamber.
The method of claim 9, wherein a temperature of the environment is between about 800 ° C to about 1800 °C.
The method of claim 9, wherein the dopant comp ri ses an acceptor species.
The method of claim 9, further comprising forming a sacrificial layer coupled to the I II-nitride substrate prior to implanting the dopant.
The method of claim 9, wherein implanting comprises performing an ion implantation process.
The method of claim 9, wherein implanting comprises diffusing the dopant into the I II -nitride removing the sacrificial layer is performed after the dopant into the III -nitride substrate the dopant into the III -nitride substrate substrate. Page 4 of 8
Layer stacks claimed or described, ordered top of device to substrate.
vertical junction field effect transistor (VJFET)
Schottky barrier diode
p-n junction diode
Materials described outside the worked examples.
III-nitride substrate
chemically reactive nitrogen source
dopant source
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A. The ammonia provides a source of active nitrogen species to counteract the 5 decomposition of the GaN material during the diffusion process resulting …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
p-type region activation level (dopant activation) | ≥ 10000000000000000 cm⁻³ | p-type III-nitride |
Temperature | 800–1800 °C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,318,331Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic diagram illustrating a conventional Schottky barrier diode. The cross section illustrated in
FIG. 2 is a simplified schematic diagram illustrating a conventional p-n junction diode. 5 The cross section illustrated in
FIG. 3A. The ammonia provides a source of active nitrogen species to counteract the 5 decomposition of the GaN material during the diffusion process resulting …
FIGS. 4A-4C are simplified process flow diagrams illustrating a solid-source diffusion 10 process according to an embodiment of the present invention. The …
FIG. 5A, an n-type doped GaN substrate 501 is implanted with an acceptor species (e.g., zin c, magnesium, beryllium, or the like) in implanted region 502. An …
FIGS. 6A-6 B are simplified process flow diagrams illustrating an ion implantation 25 process using a sacrificial layer according to an embodiment of the present …
FIG. 7C, lateral p-n junctions can thus be formed using this implantation process utilizing a sacrificial layer formed after the ion- implantation process. …
FIG. 8 is a simplified schematic diagram of a vertical junction field effect transistor 800 according to an embodiment of the present invention. The illustrated …
FIG. 9 is a simplified schematic diagram of a Schottky barri er diode according to an embodiment of the present invention. The Schottky ba rri er diode …
FIG. 10 is a simplified schematic diagram of a p-i-n diode according to an embodiment of the present invention. The p-i-n diode 1000 includes an n-type doped …
FIG. 11 is a simplified schematic diagram of a junction barrier Schottky (JBS) diode 1100 according to an embodiment of the present invention. The JBS diode …
FIG. 12 is a simplified flowchart illustrating a method of fabricating a vertical junction 15 field effect transistor according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a doped region in a I II -nitride substrate, the method comprising: providing the I II -nitride substrate, wherein the I II -nitride substrate is characterized by a first conductivity type; forming a masking layer having a predetermined pattern, wherein the predetermined pattern defines exposed regions of the I II -nitride substrate; placing the exposed regions of the I II -nitride substrate in a dual-precursor gas comprising both a chemically reactive nitrogen source and a dopant source; while the exposed regions of the III -nitride substrate are exposed to the chemically reactive nitrogen source and the dopant source of the dual-precursor gas, implanting the dopant from the dopant source of the dual-precursor gas into the exposed regions of the III- nitride substrate, wherein, while the dopant is implanted into the exposed regions, the chemically reactive nitrogen source counteracts the effects of nitrogen escaping from the III -nitride substrate; and removing the masking layer.
The method of claim 1, wherein the I II -nitride substrate comprises an n-type GaN substrate.
The method of claim 1, wherein the masking layer comprises a refractory material.
The method of claim 1, wherein a temperature of the dual-precursor gas is between about 800 ° C to about 1800 °C.
The method of claim 1, wherein the dual-precursor gas includes ammonia and an acceptor species.
The method of claim 1, wherein placing the exposed regions of the I II -nitride substrate in the dual-precursor gas comprises: positioning the I II -nitride substrate in a chamber; and flowing the dual-precursor gas including both the nitrogen source and the dopant source through the chamber.
The method of claim 1, wherein implanting the dopant into the III -nitride substrate comprises diffusing the dopant into the I II -nitride substrate.
A method of forming a doped region in a I II -nitride substrate, the method comprising: providing the III -nitride substrate, wherein the III -nitride substrate is characterized by a first conductivity type; forming a masking layer having a predetermined pattern, wherein the predetermined pattern defines predetermined portions of the III -nitride substrate; placing the I II-nitride substrate in a chamber; forming an environment in the chamber, wherein the environment comprises a dual-precursor gas including both a chemically reactive nitrogen source and a dopant source, wherein the dopant is characterized by a second conductivity type; exposing the predetermined portions of the III -nitride substrate to the chemically reactive nitrogen source and the dopant source of the dual-precursor gas; while the predetermined portions of the III -nitride substrate are exposed to the chemically reactive nitrogen source and the dopant source of the dual-precursor gas, implanting the dopant into the predetermined portions of the III -nitride substrate; while the predetermined portions of the III -nitride substrate are exposed to the chemically reactive nitrogen source, with the chemically reactive nitrogen source, counteracting the effects of nitrogen escaping from the III -nitride substrate; and removing the masking layer.
The method of claim 9, wherein the chamber comprises an MOC V D reactor.
The method of claim 9, wherein the chamber comprises an annealing furnace.
The method of claim 9, wherein the I II -nitride substrate comprises an n-type GaN substrate.
The method of claim 9, wherein the masking layer comprises a refractory material.
The method of claim 9, wherein removing the masking layer is performed prior to placing the I II -nitride substrate in the chamber.
The method of claim 9, wherein a temperature of the environment is between about 800 ° C to about 1800 °C.
The method of claim 9, wherein the dopant comp ri ses an acceptor species.
The method of claim 9, further comprising forming a sacrificial layer coupled to the I II-nitride substrate prior to implanting the dopant.
The method of claim 9, wherein implanting comprises performing an ion implantation process.
The method of claim 9, wherein implanting comprises diffusing the dopant into the I II -nitride removing the sacrificial layer is performed after the dopant into the III -nitride substrate the dopant into the III -nitride substrate substrate. Page 4 of 8
Layer stacks claimed or described, ordered top of device to substrate.
vertical junction field effect transistor (VJFET)
Schottky barrier diode
p-n junction diode
Materials described outside the worked examples.
III-nitride substrate
chemically reactive nitrogen source
dopant source
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A. The ammonia provides a source of active nitrogen species to counteract the 5 decomposition of the GaN material during the diffusion process resulting …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
p-type region activation level (dopant activation) | ≥ 10000000000000000 cm⁻³ | p-type III-nitride |
Temperature | 800–1800 °C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,318,331Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic diagram illustrating a conventional Schottky barrier diode. The cross section illustrated in
FIG. 2 is a simplified schematic diagram illustrating a conventional p-n junction diode. 5 The cross section illustrated in
FIG. 3A. The ammonia provides a source of active nitrogen species to counteract the 5 decomposition of the GaN material during the diffusion process resulting …
FIGS. 4A-4C are simplified process flow diagrams illustrating a solid-source diffusion 10 process according to an embodiment of the present invention. The …
FIG. 5A, an n-type doped GaN substrate 501 is implanted with an acceptor species (e.g., zin c, magnesium, beryllium, or the like) in implanted region 502. An …
FIGS. 6A-6 B are simplified process flow diagrams illustrating an ion implantation 25 process using a sacrificial layer according to an embodiment of the present …
FIG. 7C, lateral p-n junctions can thus be formed using this implantation process utilizing a sacrificial layer formed after the ion- implantation process. …
FIG. 8 is a simplified schematic diagram of a vertical junction field effect transistor 800 according to an embodiment of the present invention. The illustrated …
FIG. 9 is a simplified schematic diagram of a Schottky barri er diode according to an embodiment of the present invention. The Schottky ba rri er diode …
FIG. 10 is a simplified schematic diagram of a p-i-n diode according to an embodiment of the present invention. The p-i-n diode 1000 includes an n-type doped …
FIG. 11 is a simplified schematic diagram of a junction barrier Schottky (JBS) diode 1100 according to an embodiment of the present invention. The JBS diode …
FIG. 12 is a simplified flowchart illustrating a method of fabricating a vertical junction 15 field effect transistor according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a doped region in a I II -nitride substrate, the method comprising: providing the I II -nitride substrate, wherein the I II -nitride substrate is characterized by a first conductivity type; forming a masking layer having a predetermined pattern, wherein the predetermined pattern defines exposed regions of the I II -nitride substrate; placing the exposed regions of the I II -nitride substrate in a dual-precursor gas comprising both a chemically reactive nitrogen source and a dopant source; while the exposed regions of the III -nitride substrate are exposed to the chemically reactive nitrogen source and the dopant source of the dual-precursor gas, implanting the dopant from the dopant source of the dual-precursor gas into the exposed regions of the III- nitride substrate, wherein, while the dopant is implanted into the exposed regions, the chemically reactive nitrogen source counteracts the effects of nitrogen escaping from the III -nitride substrate; and removing the masking layer.
The method of claim 1, wherein the I II -nitride substrate comprises an n-type GaN substrate.
The method of claim 1, wherein the masking layer comprises a refractory material.
The method of claim 1, wherein a temperature of the dual-precursor gas is between about 800 ° C to about 1800 °C.
The method of claim 1, wherein the dual-precursor gas includes ammonia and an acceptor species.
The method of claim 1, wherein placing the exposed regions of the I II -nitride substrate in the dual-precursor gas comprises: positioning the I II -nitride substrate in a chamber; and flowing the dual-precursor gas including both the nitrogen source and the dopant source through the chamber.
The method of claim 1, wherein implanting the dopant into the III -nitride substrate comprises diffusing the dopant into the I II -nitride substrate.
A method of forming a doped region in a I II -nitride substrate, the method comprising: providing the III -nitride substrate, wherein the III -nitride substrate is characterized by a first conductivity type; forming a masking layer having a predetermined pattern, wherein the predetermined pattern defines predetermined portions of the III -nitride substrate; placing the I II-nitride substrate in a chamber; forming an environment in the chamber, wherein the environment comprises a dual-precursor gas including both a chemically reactive nitrogen source and a dopant source, wherein the dopant is characterized by a second conductivity type; exposing the predetermined portions of the III -nitride substrate to the chemically reactive nitrogen source and the dopant source of the dual-precursor gas; while the predetermined portions of the III -nitride substrate are exposed to the chemically reactive nitrogen source and the dopant source of the dual-precursor gas, implanting the dopant into the predetermined portions of the III -nitride substrate; while the predetermined portions of the III -nitride substrate are exposed to the chemically reactive nitrogen source, with the chemically reactive nitrogen source, counteracting the effects of nitrogen escaping from the III -nitride substrate; and removing the masking layer.
The method of claim 9, wherein the chamber comprises an MOC V D reactor.
The method of claim 9, wherein the chamber comprises an annealing furnace.
The method of claim 9, wherein the I II -nitride substrate comprises an n-type GaN substrate.
The method of claim 9, wherein the masking layer comprises a refractory material.
The method of claim 9, wherein removing the masking layer is performed prior to placing the I II -nitride substrate in the chamber.
The method of claim 9, wherein a temperature of the environment is between about 800 ° C to about 1800 °C.
The method of claim 9, wherein the dopant comp ri ses an acceptor species.
The method of claim 9, further comprising forming a sacrificial layer coupled to the I II-nitride substrate prior to implanting the dopant.
The method of claim 9, wherein implanting comprises performing an ion implantation process.
The method of claim 9, wherein implanting comprises diffusing the dopant into the I II -nitride removing the sacrificial layer is performed after the dopant into the III -nitride substrate the dopant into the III -nitride substrate substrate. Page 4 of 8
Layer stacks claimed or described, ordered top of device to substrate.
vertical junction field effect transistor (VJFET)
Schottky barrier diode
p-n junction diode
Materials described outside the worked examples.
III-nitride substrate
chemically reactive nitrogen source
dopant source
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A. The ammonia provides a source of active nitrogen species to counteract the 5 decomposition of the GaN material during the diffusion process resulting …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
p-type region activation level (dopant activation) | ≥ 10000000000000000 cm⁻³ | p-type III-nitride |
Temperature | 800–1800 °C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,318,331Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic diagram illustrating a conventional Schottky barrier diode. The cross section illustrated in
FIG. 2 is a simplified schematic diagram illustrating a conventional p-n junction diode. 5 The cross section illustrated in
FIG. 3A. The ammonia provides a source of active nitrogen species to counteract the 5 decomposition of the GaN material during the diffusion process resulting …
FIGS. 4A-4C are simplified process flow diagrams illustrating a solid-source diffusion 10 process according to an embodiment of the present invention. The …
FIG. 5A, an n-type doped GaN substrate 501 is implanted with an acceptor species (e.g., zin c, magnesium, beryllium, or the like) in implanted region 502. An …
FIGS. 6A-6 B are simplified process flow diagrams illustrating an ion implantation 25 process using a sacrificial layer according to an embodiment of the present …
FIG. 7C, lateral p-n junctions can thus be formed using this implantation process utilizing a sacrificial layer formed after the ion- implantation process. …
FIG. 8 is a simplified schematic diagram of a vertical junction field effect transistor 800 according to an embodiment of the present invention. The illustrated …
FIG. 9 is a simplified schematic diagram of a Schottky barri er diode according to an embodiment of the present invention. The Schottky ba rri er diode …
FIG. 10 is a simplified schematic diagram of a p-i-n diode according to an embodiment of the present invention. The p-i-n diode 1000 includes an n-type doped …
FIG. 11 is a simplified schematic diagram of a junction barrier Schottky (JBS) diode 1100 according to an embodiment of the present invention. The JBS diode …
FIG. 12 is a simplified flowchart illustrating a method of fabricating a vertical junction 15 field effect transistor according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a doped region in a I II -nitride substrate, the method comprising: providing the I II -nitride substrate, wherein the I II -nitride substrate is characterized by a first conductivity type; forming a masking layer having a predetermined pattern, wherein the predetermined pattern defines exposed regions of the I II -nitride substrate; placing the exposed regions of the I II -nitride substrate in a dual-precursor gas comprising both a chemically reactive nitrogen source and a dopant source; while the exposed regions of the III -nitride substrate are exposed to the chemically reactive nitrogen source and the dopant source of the dual-precursor gas, implanting the dopant from the dopant source of the dual-precursor gas into the exposed regions of the III- nitride substrate, wherein, while the dopant is implanted into the exposed regions, the chemically reactive nitrogen source counteracts the effects of nitrogen escaping from the III -nitride substrate; and removing the masking layer.
The method of claim 1, wherein the I II -nitride substrate comprises an n-type GaN substrate.
The method of claim 1, wherein the masking layer comprises a refractory material.
The method of claim 1, wherein a temperature of the dual-precursor gas is between about 800 ° C to about 1800 °C.
The method of claim 1, wherein the dual-precursor gas includes ammonia and an acceptor species.
The method of claim 1, wherein placing the exposed regions of the I II -nitride substrate in the dual-precursor gas comprises: positioning the I II -nitride substrate in a chamber; and flowing the dual-precursor gas including both the nitrogen source and the dopant source through the chamber.
The method of claim 1, wherein implanting the dopant into the III -nitride substrate comprises diffusing the dopant into the I II -nitride substrate.
A method of forming a doped region in a I II -nitride substrate, the method comprising: providing the III -nitride substrate, wherein the III -nitride substrate is characterized by a first conductivity type; forming a masking layer having a predetermined pattern, wherein the predetermined pattern defines predetermined portions of the III -nitride substrate; placing the I II-nitride substrate in a chamber; forming an environment in the chamber, wherein the environment comprises a dual-precursor gas including both a chemically reactive nitrogen source and a dopant source, wherein the dopant is characterized by a second conductivity type; exposing the predetermined portions of the III -nitride substrate to the chemically reactive nitrogen source and the dopant source of the dual-precursor gas; while the predetermined portions of the III -nitride substrate are exposed to the chemically reactive nitrogen source and the dopant source of the dual-precursor gas, implanting the dopant into the predetermined portions of the III -nitride substrate; while the predetermined portions of the III -nitride substrate are exposed to the chemically reactive nitrogen source, with the chemically reactive nitrogen source, counteracting the effects of nitrogen escaping from the III -nitride substrate; and removing the masking layer.
The method of claim 9, wherein the chamber comprises an MOC V D reactor.
The method of claim 9, wherein the chamber comprises an annealing furnace.
The method of claim 9, wherein the I II -nitride substrate comprises an n-type GaN substrate.
The method of claim 9, wherein the masking layer comprises a refractory material.
The method of claim 9, wherein removing the masking layer is performed prior to placing the I II -nitride substrate in the chamber.
The method of claim 9, wherein a temperature of the environment is between about 800 ° C to about 1800 °C.
The method of claim 9, wherein the dopant comp ri ses an acceptor species.
The method of claim 9, further comprising forming a sacrificial layer coupled to the I II-nitride substrate prior to implanting the dopant.
The method of claim 9, wherein implanting comprises performing an ion implantation process.
The method of claim 9, wherein implanting comprises diffusing the dopant into the I II -nitride removing the sacrificial layer is performed after the dopant into the III -nitride substrate the dopant into the III -nitride substrate substrate. Page 4 of 8
Layer stacks claimed or described, ordered top of device to substrate.
vertical junction field effect transistor (VJFET)
Schottky barrier diode
p-n junction diode
Materials described outside the worked examples.
III-nitride substrate
chemically reactive nitrogen source
dopant source
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A. The ammonia provides a source of active nitrogen species to counteract the 5 decomposition of the GaN material during the diffusion process resulting …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
p-type region activation level (dopant activation) | ≥ 10000000000000000 cm⁻³ | p-type III-nitride |
Temperature | 800–1800 °C |
Related documents with shared materials, methods, properties, or citations.
p-i-n diode
junction barrier Schottky diode
n-type GaN substrate
GaN
refractory material (masking layer)
ammonia
NH₃
acceptor species (dopant)
p-type III-nitride
FIG. 8 is a simplified schematic diagram of a vertical junction field effect transistor 800 according to an embodiment of the present invention. The illustrated …
FIG. 12 is a simplified flowchart illustrating a method of fabricating a vertical junction 15 field effect transistor according to an embodiment of the present …
| — |
Thickness | 1–200 nm | — |
p-i-n diode
junction barrier Schottky diode
n-type GaN substrate
GaN
refractory material (masking layer)
ammonia
NH₃
acceptor species (dopant)
p-type III-nitride
FIG. 8 is a simplified schematic diagram of a vertical junction field effect transistor 800 according to an embodiment of the present invention. The illustrated …
FIG. 12 is a simplified flowchart illustrating a method of fabricating a vertical junction 15 field effect transistor according to an embodiment of the present …
| — |
Thickness | 1–200 nm | — |
p-i-n diode
junction barrier Schottky diode
n-type GaN substrate
GaN
refractory material (masking layer)
ammonia
NH₃
acceptor species (dopant)
p-type III-nitride
FIG. 8 is a simplified schematic diagram of a vertical junction field effect transistor 800 according to an embodiment of the present invention. The illustrated …
FIG. 12 is a simplified flowchart illustrating a method of fabricating a vertical junction 15 field effect transistor according to an embodiment of the present …
| — |
Thickness | 1–200 nm | — |
p-i-n diode
junction barrier Schottky diode
n-type GaN substrate
GaN
refractory material (masking layer)
ammonia
NH₃
acceptor species (dopant)
p-type III-nitride
FIG. 8 is a simplified schematic diagram of a vertical junction field effect transistor 800 according to an embodiment of the present invention. The illustrated …
FIG. 12 is a simplified flowchart illustrating a method of fabricating a vertical junction 15 field effect transistor according to an embodiment of the present …
| — |
Thickness | 1–200 nm | — |