Patent
US 9,224,828METHOD AND SYSTEM FOR FLOATING GUARD RINGS IN GAN MATERIALS
Andrew Edwards, Hui Nie, Isik C. Kizilyalli, Richard J. Brown et al.
EPOWERSOFT, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,224,828Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-1 B are simplified cross-sectional diagrams of a portion of a semiconductor device, illustrating how edge termination structures improve the …
FIGS. 2-7 are simplified cross-sectional diagrams illustrating the fabrication of a Schottky diode in gallium-nitride (GaN) with edge termination structures …
FIG. 3 illustrates the formation of a second GaN epitaxial layer 301 above the first GaN epitaxial layer 201. The second GaN epitaxial layer 301, from which …
FIG. 4 illustrates the formation of a first metallic structure 401 below the GaN substrate 20 200. The first metallic structure 401 can be one or more layers of …
FIG. 5 is a simplified cross-sectional diagram illustrating the removal at least a portion of the second GaN epitaxial layer 301 to form edge termination …
FIG. 6 illustrates the formation of a second metallic structure 601 on the exposed portion 510 of the first GaN epitaxial layer 201. The second metallic …
FIG. 7A. These metallic field plates 1001 can be formed using the same techniques used to form 20 the metallic structures 401 and 901, and also can include …
FIGS. 8-10 are simplified cross-sectional diagrams illustrating fabrication of a P IN diode in GaN with edge termination structures formed through the etching …
FIG. 9 illustrates the formation of a second metallic structure 901 (in addition to the metallic structure 401) electrically coupled to the device structure …
FIG. 10. One of ordinary skill in the art would recognize many variations, modifications, and alternatives. 25 [0048]
FIG. 11 is simplified cross-sectional diagram illustrating a vertical JFET with edge termination structures according to another embodiment of the present …
FIGS. 12-14 are simplified top-view illustrations showing different example embodiments of edge termination structures according to embodiments of the present …
FIG. 13, illustrating how edge termination structures, such as guard rings 1420, can shaped differently to accommodate differently-shaped semiconductor …
FIG. 14 illustrates yet another embodiment of a transistor structure similar to the embodiment shown in
FIG. 15 is a simplified flowchart illustrating a method of fabricating a Schottky diode with edge termination structures formed through the etching of an …
FIG. 16 is a simplified flowchart illustrating a method of fabricating a PIN diode with edge termination structures formed through the etching of an epitaxial …
FIGS. 17A-17F are cross-sectional diagrams of a process for forming a GaN Schottky diode with a buried p-type layer with edge termination structures, according …
FIG. 18 is an illustration of an overhead view of the diode formed in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating edge termination structures in gallium nitride (GaN) materials, the method comprising: providing a n-type GaN substrate having a first surface and a second surface; forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate; adding a p-type dopant into the n-type GaN epitaxial layer to form a p-type GaN epitaxial layer, wherein the doping concentration of the p-type GaN epitaxial layer is less than 5 x 10 18 cm⁻³-removing at least a portion of the p-type GaN epitaxial layer to: form at least one p-type gate region of a vertical junction field-effect transistor (JFET) using a remaining portion of the p-type GaN epitaxial layer; form an exposed portion of the n-type GaN epitaxial layer; and form a plurality of edge termination structures; forming a first metallic structure electrically coupled to the second surface of the n-type GaN substrate; forming an n-type GaN channel region coupled to the at least one p-type gate region, wherein the n-type GaN channel region overlaps the gate region; forming an n-type GaN source region coupled with the n-type GaN channel region, wherein the n-type GaN source region overlaps the gate region; and forming first and second ohmic metal contacts coupled to the at least one p-type gate region and the n-type GaN source region, respectively, wherein the second ohmic metal contact overlaps the gate region.; and providing a dielectric between the edge termination structures.
The method of claim 1 wherein the n-type GaN substrate is characterized by a first n-type dopant concentration and the n-type GaN epitaxial layer is Page 2 o f 9 App l. No. 13/270,606 PATENT Amdt. dated Response to Office Action of characterized by a second n-type dopant concentration less than the first n-type dopant concentration.
The method of claim 1 further comprising forming a second metallic structure electrically coupled to the at least one p-type gate region.
The method of claim 1 further comprising forming a metallic field plate coupled to at least one edge termination structure.
The method of claim 1 wherein at least one edge termination structure circumscribes a device structure.
The method of claim 1 wherein forming the first metallic structure is performed after forming the edge termination structures.
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A method of fabricating an epitaxial structure, the method comprising: providing a I II -nitride substrate of a first conductivity type characterized by a first dopant concentration; forming a first I II -nitride epitaxial layer of the first conductivity type coupled to a first surface of the I II -nitride substrate; adding a dopant into the first I II -nitride epitaxial layer to form a second I II -nitride epitaxial layer, wherein the second I II -nitride epitaxial layer has the second conductivity type, and wherein the doping concentration of the second I II -nitride epitaxial layer is less than 5 x 1018 cm⁻³; and removing at least a portion of the second I II -nitride epitaxial layer to: form an exposed portion of the first I II -nitride epitaxial layer; form a plurality of edge termination structures; and Page 3 of 9 App l. No. 13/270,606 PATENT Amdt. dated Response to Office Action of form a p-type gate region of a vertical junction field-effect transistor (JF E T); forming an n-type GaN channel region coupled to the p-type gate region, wherein the n-type GaN channel region overlaps the p-type gate region; forming an n-type GaN source region coupled with the n-type GaN channel region, wherein the n-type GaN source region overlaps the p-type gate region; forming first and second ohmic metal contacts coupled to the p-type gate region and the n-type GaN source region, respectively, wherein the second ohmic metal contact overlaps the p-type gate region; and providing a dielectric between the edge termination structures.
The method of claim 11 further comprising forming a metallic structure coupled to the p-type gate region.
The method of claim 11 further comprising forming a metallic field plate coupled to at least one edge termination structure.
The method of claim 11 wherein at least one edge termination structure circumscribes a semiconductor device.
The method of claim 11 wherein the first I II -nitride epitaxial layer is characterized by a second dopant concentration less than the first dopant concentration.
The method of claim 11 wherein forming the edge termination structures comprises forming three or more edge termination structures with predetermined spaces between each of the three or more edge termination structures, wherein: a first spacing of the predetermined spaces is located closer to a semiconductor device than a second spacing of the predetermined spaces; and a width of the first spacing is smaller than a width of the second spacing.
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A semiconductor structure comprising: a I II -nitride substrate having a first side and a second side opposing the first side, wherein the I II -nitride substrate is characterized by a first conductivity type and a first dopant concentration; a I II -nitride epitaxial layer of the first conductivity type coupled to the first surface of the I II -nitride substrate, wherein the I II -nitride epitaxial layer has a diff u sion region which has a dopant of a second conductivity type, and wherein the doping concentration of the diffusion region is less than about 5 x 1018 cm -3; a first metallic structure electrically coupled to the second surface of the III- nitride substrate; a I II-nitride epitaxial structure of the second conductivity type formed of an etched portion of the diffusion region of the I II -nitride epitaxial layer, wherein the I II -nitride epitaxial structure comprises a plurality of edge termination structures and at least one gate region of a vertical junction field-effect transistor (JFE T); a dielectric between the edge termination structures; a channel region coupled to the at least one gate region and the I II -nitride epitaxial layer, wherein the channel region comprises a I II -nitride epitaxial material of the first conductivity type, and wherein the channel region overlaps the gate region; a source region coupled to the channel region, wherein the source region comprises a I II -nitride epitaxial material of the first conductivity type, and wherein the source region overlaps the gate region; and first and second ohmic metal contacts coupled to the source region and the at least one gate region, respectively, wherein the second ohmic metal contact overlaps the gate region.
The semiconductor structure of claim 19 f u rther comprising a metallic field plate coupled to at least one edge termination structure.
The semiconductor structure of claim 19 wherein at least one edge termination structure circumscribes a semiconductor device.
The semiconductor structure of claim 19 wherein: the edge termination structure comprise three or more edge termination structures with a plurality of spacings between the edge termination structures; a first spacing is located closer to a semiconductor device than a second spacing; and a width of the first spacing is smaller than a width of the second spacing.
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Layer stacks claimed or described, ordered top of device to substrate.
vertical junction field-effect transistor (JFET) with edge termination structures (GaN)
vertical junction field-effect transistor (JFET) with edge termination structures (III-nitride, generic)
Materials described outside the worked examples.
n-type GaN substrate
GaN
dielectric
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 9 illustrates the formation of a second metallic structure 901 (in addition to the metallic structure 401) electrically coupled to the device structure …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,224,828Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-1 B are simplified cross-sectional diagrams of a portion of a semiconductor device, illustrating how edge termination structures improve the …
FIGS. 2-7 are simplified cross-sectional diagrams illustrating the fabrication of a Schottky diode in gallium-nitride (GaN) with edge termination structures …
FIG. 3 illustrates the formation of a second GaN epitaxial layer 301 above the first GaN epitaxial layer 201. The second GaN epitaxial layer 301, from which …
FIG. 4 illustrates the formation of a first metallic structure 401 below the GaN substrate 20 200. The first metallic structure 401 can be one or more layers of …
FIG. 5 is a simplified cross-sectional diagram illustrating the removal at least a portion of the second GaN epitaxial layer 301 to form edge termination …
FIG. 6 illustrates the formation of a second metallic structure 601 on the exposed portion 510 of the first GaN epitaxial layer 201. The second metallic …
FIG. 7A. These metallic field plates 1001 can be formed using the same techniques used to form 20 the metallic structures 401 and 901, and also can include …
FIGS. 8-10 are simplified cross-sectional diagrams illustrating fabrication of a P IN diode in GaN with edge termination structures formed through the etching …
FIG. 9 illustrates the formation of a second metallic structure 901 (in addition to the metallic structure 401) electrically coupled to the device structure …
FIG. 10. One of ordinary skill in the art would recognize many variations, modifications, and alternatives. 25 [0048]
FIG. 11 is simplified cross-sectional diagram illustrating a vertical JFET with edge termination structures according to another embodiment of the present …
FIGS. 12-14 are simplified top-view illustrations showing different example embodiments of edge termination structures according to embodiments of the present …
FIG. 13, illustrating how edge termination structures, such as guard rings 1420, can shaped differently to accommodate differently-shaped semiconductor …
FIG. 14 illustrates yet another embodiment of a transistor structure similar to the embodiment shown in
FIG. 15 is a simplified flowchart illustrating a method of fabricating a Schottky diode with edge termination structures formed through the etching of an …
FIG. 16 is a simplified flowchart illustrating a method of fabricating a PIN diode with edge termination structures formed through the etching of an epitaxial …
FIGS. 17A-17F are cross-sectional diagrams of a process for forming a GaN Schottky diode with a buried p-type layer with edge termination structures, according …
FIG. 18 is an illustration of an overhead view of the diode formed in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating edge termination structures in gallium nitride (GaN) materials, the method comprising: providing a n-type GaN substrate having a first surface and a second surface; forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate; adding a p-type dopant into the n-type GaN epitaxial layer to form a p-type GaN epitaxial layer, wherein the doping concentration of the p-type GaN epitaxial layer is less than 5 x 10 18 cm⁻³-removing at least a portion of the p-type GaN epitaxial layer to: form at least one p-type gate region of a vertical junction field-effect transistor (JFET) using a remaining portion of the p-type GaN epitaxial layer; form an exposed portion of the n-type GaN epitaxial layer; and form a plurality of edge termination structures; forming a first metallic structure electrically coupled to the second surface of the n-type GaN substrate; forming an n-type GaN channel region coupled to the at least one p-type gate region, wherein the n-type GaN channel region overlaps the gate region; forming an n-type GaN source region coupled with the n-type GaN channel region, wherein the n-type GaN source region overlaps the gate region; and forming first and second ohmic metal contacts coupled to the at least one p-type gate region and the n-type GaN source region, respectively, wherein the second ohmic metal contact overlaps the gate region.; and providing a dielectric between the edge termination structures.
The method of claim 1 wherein the n-type GaN substrate is characterized by a first n-type dopant concentration and the n-type GaN epitaxial layer is Page 2 o f 9 App l. No. 13/270,606 PATENT Amdt. dated Response to Office Action of characterized by a second n-type dopant concentration less than the first n-type dopant concentration.
The method of claim 1 further comprising forming a second metallic structure electrically coupled to the at least one p-type gate region.
The method of claim 1 further comprising forming a metallic field plate coupled to at least one edge termination structure.
The method of claim 1 wherein at least one edge termination structure circumscribes a device structure.
The method of claim 1 wherein forming the first metallic structure is performed after forming the edge termination structures.
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A method of fabricating an epitaxial structure, the method comprising: providing a I II -nitride substrate of a first conductivity type characterized by a first dopant concentration; forming a first I II -nitride epitaxial layer of the first conductivity type coupled to a first surface of the I II -nitride substrate; adding a dopant into the first I II -nitride epitaxial layer to form a second I II -nitride epitaxial layer, wherein the second I II -nitride epitaxial layer has the second conductivity type, and wherein the doping concentration of the second I II -nitride epitaxial layer is less than 5 x 1018 cm⁻³; and removing at least a portion of the second I II -nitride epitaxial layer to: form an exposed portion of the first I II -nitride epitaxial layer; form a plurality of edge termination structures; and Page 3 of 9 App l. No. 13/270,606 PATENT Amdt. dated Response to Office Action of form a p-type gate region of a vertical junction field-effect transistor (JF E T); forming an n-type GaN channel region coupled to the p-type gate region, wherein the n-type GaN channel region overlaps the p-type gate region; forming an n-type GaN source region coupled with the n-type GaN channel region, wherein the n-type GaN source region overlaps the p-type gate region; forming first and second ohmic metal contacts coupled to the p-type gate region and the n-type GaN source region, respectively, wherein the second ohmic metal contact overlaps the p-type gate region; and providing a dielectric between the edge termination structures.
The method of claim 11 further comprising forming a metallic structure coupled to the p-type gate region.
The method of claim 11 further comprising forming a metallic field plate coupled to at least one edge termination structure.
The method of claim 11 wherein at least one edge termination structure circumscribes a semiconductor device.
The method of claim 11 wherein the first I II -nitride epitaxial layer is characterized by a second dopant concentration less than the first dopant concentration.
The method of claim 11 wherein forming the edge termination structures comprises forming three or more edge termination structures with predetermined spaces between each of the three or more edge termination structures, wherein: a first spacing of the predetermined spaces is located closer to a semiconductor device than a second spacing of the predetermined spaces; and a width of the first spacing is smaller than a width of the second spacing.
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A semiconductor structure comprising: a I II -nitride substrate having a first side and a second side opposing the first side, wherein the I II -nitride substrate is characterized by a first conductivity type and a first dopant concentration; a I II -nitride epitaxial layer of the first conductivity type coupled to the first surface of the I II -nitride substrate, wherein the I II -nitride epitaxial layer has a diff u sion region which has a dopant of a second conductivity type, and wherein the doping concentration of the diffusion region is less than about 5 x 1018 cm -3; a first metallic structure electrically coupled to the second surface of the III- nitride substrate; a I II-nitride epitaxial structure of the second conductivity type formed of an etched portion of the diffusion region of the I II -nitride epitaxial layer, wherein the I II -nitride epitaxial structure comprises a plurality of edge termination structures and at least one gate region of a vertical junction field-effect transistor (JFE T); a dielectric between the edge termination structures; a channel region coupled to the at least one gate region and the I II -nitride epitaxial layer, wherein the channel region comprises a I II -nitride epitaxial material of the first conductivity type, and wherein the channel region overlaps the gate region; a source region coupled to the channel region, wherein the source region comprises a I II -nitride epitaxial material of the first conductivity type, and wherein the source region overlaps the gate region; and first and second ohmic metal contacts coupled to the source region and the at least one gate region, respectively, wherein the second ohmic metal contact overlaps the gate region.
The semiconductor structure of claim 19 f u rther comprising a metallic field plate coupled to at least one edge termination structure.
The semiconductor structure of claim 19 wherein at least one edge termination structure circumscribes a semiconductor device.
The semiconductor structure of claim 19 wherein: the edge termination structure comprise three or more edge termination structures with a plurality of spacings between the edge termination structures; a first spacing is located closer to a semiconductor device than a second spacing; and a width of the first spacing is smaller than a width of the second spacing.
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Layer stacks claimed or described, ordered top of device to substrate.
vertical junction field-effect transistor (JFET) with edge termination structures (GaN)
vertical junction field-effect transistor (JFET) with edge termination structures (III-nitride, generic)
Materials described outside the worked examples.
n-type GaN substrate
GaN
dielectric
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 9 illustrates the formation of a second metallic structure 901 (in addition to the metallic structure 401) electrically coupled to the device structure …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,224,828Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-1 B are simplified cross-sectional diagrams of a portion of a semiconductor device, illustrating how edge termination structures improve the …
FIGS. 2-7 are simplified cross-sectional diagrams illustrating the fabrication of a Schottky diode in gallium-nitride (GaN) with edge termination structures …
FIG. 3 illustrates the formation of a second GaN epitaxial layer 301 above the first GaN epitaxial layer 201. The second GaN epitaxial layer 301, from which …
FIG. 4 illustrates the formation of a first metallic structure 401 below the GaN substrate 20 200. The first metallic structure 401 can be one or more layers of …
FIG. 5 is a simplified cross-sectional diagram illustrating the removal at least a portion of the second GaN epitaxial layer 301 to form edge termination …
FIG. 6 illustrates the formation of a second metallic structure 601 on the exposed portion 510 of the first GaN epitaxial layer 201. The second metallic …
FIG. 7A. These metallic field plates 1001 can be formed using the same techniques used to form 20 the metallic structures 401 and 901, and also can include …
FIGS. 8-10 are simplified cross-sectional diagrams illustrating fabrication of a P IN diode in GaN with edge termination structures formed through the etching …
FIG. 9 illustrates the formation of a second metallic structure 901 (in addition to the metallic structure 401) electrically coupled to the device structure …
FIG. 10. One of ordinary skill in the art would recognize many variations, modifications, and alternatives. 25 [0048]
FIG. 11 is simplified cross-sectional diagram illustrating a vertical JFET with edge termination structures according to another embodiment of the present …
FIGS. 12-14 are simplified top-view illustrations showing different example embodiments of edge termination structures according to embodiments of the present …
FIG. 13, illustrating how edge termination structures, such as guard rings 1420, can shaped differently to accommodate differently-shaped semiconductor …
FIG. 14 illustrates yet another embodiment of a transistor structure similar to the embodiment shown in
FIG. 15 is a simplified flowchart illustrating a method of fabricating a Schottky diode with edge termination structures formed through the etching of an …
FIG. 16 is a simplified flowchart illustrating a method of fabricating a PIN diode with edge termination structures formed through the etching of an epitaxial …
FIGS. 17A-17F are cross-sectional diagrams of a process for forming a GaN Schottky diode with a buried p-type layer with edge termination structures, according …
FIG. 18 is an illustration of an overhead view of the diode formed in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating edge termination structures in gallium nitride (GaN) materials, the method comprising: providing a n-type GaN substrate having a first surface and a second surface; forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate; adding a p-type dopant into the n-type GaN epitaxial layer to form a p-type GaN epitaxial layer, wherein the doping concentration of the p-type GaN epitaxial layer is less than 5 x 10 18 cm⁻³-removing at least a portion of the p-type GaN epitaxial layer to: form at least one p-type gate region of a vertical junction field-effect transistor (JFET) using a remaining portion of the p-type GaN epitaxial layer; form an exposed portion of the n-type GaN epitaxial layer; and form a plurality of edge termination structures; forming a first metallic structure electrically coupled to the second surface of the n-type GaN substrate; forming an n-type GaN channel region coupled to the at least one p-type gate region, wherein the n-type GaN channel region overlaps the gate region; forming an n-type GaN source region coupled with the n-type GaN channel region, wherein the n-type GaN source region overlaps the gate region; and forming first and second ohmic metal contacts coupled to the at least one p-type gate region and the n-type GaN source region, respectively, wherein the second ohmic metal contact overlaps the gate region.; and providing a dielectric between the edge termination structures.
The method of claim 1 wherein the n-type GaN substrate is characterized by a first n-type dopant concentration and the n-type GaN epitaxial layer is Page 2 o f 9 App l. No. 13/270,606 PATENT Amdt. dated Response to Office Action of characterized by a second n-type dopant concentration less than the first n-type dopant concentration.
The method of claim 1 further comprising forming a second metallic structure electrically coupled to the at least one p-type gate region.
The method of claim 1 further comprising forming a metallic field plate coupled to at least one edge termination structure.
The method of claim 1 wherein at least one edge termination structure circumscribes a device structure.
The method of claim 1 wherein forming the first metallic structure is performed after forming the edge termination structures.
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A method of fabricating an epitaxial structure, the method comprising: providing a I II -nitride substrate of a first conductivity type characterized by a first dopant concentration; forming a first I II -nitride epitaxial layer of the first conductivity type coupled to a first surface of the I II -nitride substrate; adding a dopant into the first I II -nitride epitaxial layer to form a second I II -nitride epitaxial layer, wherein the second I II -nitride epitaxial layer has the second conductivity type, and wherein the doping concentration of the second I II -nitride epitaxial layer is less than 5 x 1018 cm⁻³; and removing at least a portion of the second I II -nitride epitaxial layer to: form an exposed portion of the first I II -nitride epitaxial layer; form a plurality of edge termination structures; and Page 3 of 9 App l. No. 13/270,606 PATENT Amdt. dated Response to Office Action of form a p-type gate region of a vertical junction field-effect transistor (JF E T); forming an n-type GaN channel region coupled to the p-type gate region, wherein the n-type GaN channel region overlaps the p-type gate region; forming an n-type GaN source region coupled with the n-type GaN channel region, wherein the n-type GaN source region overlaps the p-type gate region; forming first and second ohmic metal contacts coupled to the p-type gate region and the n-type GaN source region, respectively, wherein the second ohmic metal contact overlaps the p-type gate region; and providing a dielectric between the edge termination structures.
The method of claim 11 further comprising forming a metallic structure coupled to the p-type gate region.
The method of claim 11 further comprising forming a metallic field plate coupled to at least one edge termination structure.
The method of claim 11 wherein at least one edge termination structure circumscribes a semiconductor device.
The method of claim 11 wherein the first I II -nitride epitaxial layer is characterized by a second dopant concentration less than the first dopant concentration.
The method of claim 11 wherein forming the edge termination structures comprises forming three or more edge termination structures with predetermined spaces between each of the three or more edge termination structures, wherein: a first spacing of the predetermined spaces is located closer to a semiconductor device than a second spacing of the predetermined spaces; and a width of the first spacing is smaller than a width of the second spacing.
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A semiconductor structure comprising: a I II -nitride substrate having a first side and a second side opposing the first side, wherein the I II -nitride substrate is characterized by a first conductivity type and a first dopant concentration; a I II -nitride epitaxial layer of the first conductivity type coupled to the first surface of the I II -nitride substrate, wherein the I II -nitride epitaxial layer has a diff u sion region which has a dopant of a second conductivity type, and wherein the doping concentration of the diffusion region is less than about 5 x 1018 cm -3; a first metallic structure electrically coupled to the second surface of the III- nitride substrate; a I II-nitride epitaxial structure of the second conductivity type formed of an etched portion of the diffusion region of the I II -nitride epitaxial layer, wherein the I II -nitride epitaxial structure comprises a plurality of edge termination structures and at least one gate region of a vertical junction field-effect transistor (JFE T); a dielectric between the edge termination structures; a channel region coupled to the at least one gate region and the I II -nitride epitaxial layer, wherein the channel region comprises a I II -nitride epitaxial material of the first conductivity type, and wherein the channel region overlaps the gate region; a source region coupled to the channel region, wherein the source region comprises a I II -nitride epitaxial material of the first conductivity type, and wherein the source region overlaps the gate region; and first and second ohmic metal contacts coupled to the source region and the at least one gate region, respectively, wherein the second ohmic metal contact overlaps the gate region.
The semiconductor structure of claim 19 f u rther comprising a metallic field plate coupled to at least one edge termination structure.
The semiconductor structure of claim 19 wherein at least one edge termination structure circumscribes a semiconductor device.
The semiconductor structure of claim 19 wherein: the edge termination structure comprise three or more edge termination structures with a plurality of spacings between the edge termination structures; a first spacing is located closer to a semiconductor device than a second spacing; and a width of the first spacing is smaller than a width of the second spacing.
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Layer stacks claimed or described, ordered top of device to substrate.
vertical junction field-effect transistor (JFET) with edge termination structures (GaN)
vertical junction field-effect transistor (JFET) with edge termination structures (III-nitride, generic)
Materials described outside the worked examples.
n-type GaN substrate
GaN
dielectric
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 9 illustrates the formation of a second metallic structure 901 (in addition to the metallic structure 401) electrically coupled to the device structure …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,224,828Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-1 B are simplified cross-sectional diagrams of a portion of a semiconductor device, illustrating how edge termination structures improve the …
FIGS. 2-7 are simplified cross-sectional diagrams illustrating the fabrication of a Schottky diode in gallium-nitride (GaN) with edge termination structures …
FIG. 3 illustrates the formation of a second GaN epitaxial layer 301 above the first GaN epitaxial layer 201. The second GaN epitaxial layer 301, from which …
FIG. 4 illustrates the formation of a first metallic structure 401 below the GaN substrate 20 200. The first metallic structure 401 can be one or more layers of …
FIG. 5 is a simplified cross-sectional diagram illustrating the removal at least a portion of the second GaN epitaxial layer 301 to form edge termination …
FIG. 6 illustrates the formation of a second metallic structure 601 on the exposed portion 510 of the first GaN epitaxial layer 201. The second metallic …
FIG. 7A. These metallic field plates 1001 can be formed using the same techniques used to form 20 the metallic structures 401 and 901, and also can include …
FIGS. 8-10 are simplified cross-sectional diagrams illustrating fabrication of a P IN diode in GaN with edge termination structures formed through the etching …
FIG. 9 illustrates the formation of a second metallic structure 901 (in addition to the metallic structure 401) electrically coupled to the device structure …
FIG. 10. One of ordinary skill in the art would recognize many variations, modifications, and alternatives. 25 [0048]
FIG. 11 is simplified cross-sectional diagram illustrating a vertical JFET with edge termination structures according to another embodiment of the present …
FIGS. 12-14 are simplified top-view illustrations showing different example embodiments of edge termination structures according to embodiments of the present …
FIG. 13, illustrating how edge termination structures, such as guard rings 1420, can shaped differently to accommodate differently-shaped semiconductor …
FIG. 14 illustrates yet another embodiment of a transistor structure similar to the embodiment shown in
FIG. 15 is a simplified flowchart illustrating a method of fabricating a Schottky diode with edge termination structures formed through the etching of an …
FIG. 16 is a simplified flowchart illustrating a method of fabricating a PIN diode with edge termination structures formed through the etching of an epitaxial …
FIGS. 17A-17F are cross-sectional diagrams of a process for forming a GaN Schottky diode with a buried p-type layer with edge termination structures, according …
FIG. 18 is an illustration of an overhead view of the diode formed in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating edge termination structures in gallium nitride (GaN) materials, the method comprising: providing a n-type GaN substrate having a first surface and a second surface; forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate; adding a p-type dopant into the n-type GaN epitaxial layer to form a p-type GaN epitaxial layer, wherein the doping concentration of the p-type GaN epitaxial layer is less than 5 x 10 18 cm⁻³-removing at least a portion of the p-type GaN epitaxial layer to: form at least one p-type gate region of a vertical junction field-effect transistor (JFET) using a remaining portion of the p-type GaN epitaxial layer; form an exposed portion of the n-type GaN epitaxial layer; and form a plurality of edge termination structures; forming a first metallic structure electrically coupled to the second surface of the n-type GaN substrate; forming an n-type GaN channel region coupled to the at least one p-type gate region, wherein the n-type GaN channel region overlaps the gate region; forming an n-type GaN source region coupled with the n-type GaN channel region, wherein the n-type GaN source region overlaps the gate region; and forming first and second ohmic metal contacts coupled to the at least one p-type gate region and the n-type GaN source region, respectively, wherein the second ohmic metal contact overlaps the gate region.; and providing a dielectric between the edge termination structures.
The method of claim 1 wherein the n-type GaN substrate is characterized by a first n-type dopant concentration and the n-type GaN epitaxial layer is Page 2 o f 9 App l. No. 13/270,606 PATENT Amdt. dated Response to Office Action of characterized by a second n-type dopant concentration less than the first n-type dopant concentration.
The method of claim 1 further comprising forming a second metallic structure electrically coupled to the at least one p-type gate region.
The method of claim 1 further comprising forming a metallic field plate coupled to at least one edge termination structure.
The method of claim 1 wherein at least one edge termination structure circumscribes a device structure.
The method of claim 1 wherein forming the first metallic structure is performed after forming the edge termination structures.
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A method of fabricating an epitaxial structure, the method comprising: providing a I II -nitride substrate of a first conductivity type characterized by a first dopant concentration; forming a first I II -nitride epitaxial layer of the first conductivity type coupled to a first surface of the I II -nitride substrate; adding a dopant into the first I II -nitride epitaxial layer to form a second I II -nitride epitaxial layer, wherein the second I II -nitride epitaxial layer has the second conductivity type, and wherein the doping concentration of the second I II -nitride epitaxial layer is less than 5 x 1018 cm⁻³; and removing at least a portion of the second I II -nitride epitaxial layer to: form an exposed portion of the first I II -nitride epitaxial layer; form a plurality of edge termination structures; and Page 3 of 9 App l. No. 13/270,606 PATENT Amdt. dated Response to Office Action of form a p-type gate region of a vertical junction field-effect transistor (JF E T); forming an n-type GaN channel region coupled to the p-type gate region, wherein the n-type GaN channel region overlaps the p-type gate region; forming an n-type GaN source region coupled with the n-type GaN channel region, wherein the n-type GaN source region overlaps the p-type gate region; forming first and second ohmic metal contacts coupled to the p-type gate region and the n-type GaN source region, respectively, wherein the second ohmic metal contact overlaps the p-type gate region; and providing a dielectric between the edge termination structures.
The method of claim 11 further comprising forming a metallic structure coupled to the p-type gate region.
The method of claim 11 further comprising forming a metallic field plate coupled to at least one edge termination structure.
The method of claim 11 wherein at least one edge termination structure circumscribes a semiconductor device.
The method of claim 11 wherein the first I II -nitride epitaxial layer is characterized by a second dopant concentration less than the first dopant concentration.
The method of claim 11 wherein forming the edge termination structures comprises forming three or more edge termination structures with predetermined spaces between each of the three or more edge termination structures, wherein: a first spacing of the predetermined spaces is located closer to a semiconductor device than a second spacing of the predetermined spaces; and a width of the first spacing is smaller than a width of the second spacing.
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A semiconductor structure comprising: a I II -nitride substrate having a first side and a second side opposing the first side, wherein the I II -nitride substrate is characterized by a first conductivity type and a first dopant concentration; a I II -nitride epitaxial layer of the first conductivity type coupled to the first surface of the I II -nitride substrate, wherein the I II -nitride epitaxial layer has a diff u sion region which has a dopant of a second conductivity type, and wherein the doping concentration of the diffusion region is less than about 5 x 1018 cm -3; a first metallic structure electrically coupled to the second surface of the III- nitride substrate; a I II-nitride epitaxial structure of the second conductivity type formed of an etched portion of the diffusion region of the I II -nitride epitaxial layer, wherein the I II -nitride epitaxial structure comprises a plurality of edge termination structures and at least one gate region of a vertical junction field-effect transistor (JFE T); a dielectric between the edge termination structures; a channel region coupled to the at least one gate region and the I II -nitride epitaxial layer, wherein the channel region comprises a I II -nitride epitaxial material of the first conductivity type, and wherein the channel region overlaps the gate region; a source region coupled to the channel region, wherein the source region comprises a I II -nitride epitaxial material of the first conductivity type, and wherein the source region overlaps the gate region; and first and second ohmic metal contacts coupled to the source region and the at least one gate region, respectively, wherein the second ohmic metal contact overlaps the gate region.
The semiconductor structure of claim 19 f u rther comprising a metallic field plate coupled to at least one edge termination structure.
The semiconductor structure of claim 19 wherein at least one edge termination structure circumscribes a semiconductor device.
The semiconductor structure of claim 19 wherein: the edge termination structure comprise three or more edge termination structures with a plurality of spacings between the edge termination structures; a first spacing is located closer to a semiconductor device than a second spacing; and a width of the first spacing is smaller than a width of the second spacing.
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Layer stacks claimed or described, ordered top of device to substrate.
vertical junction field-effect transistor (JFET) with edge termination structures (GaN)
vertical junction field-effect transistor (JFET) with edge termination structures (III-nitride, generic)
Materials described outside the worked examples.
n-type GaN substrate
GaN
dielectric
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 9 illustrates the formation of a second metallic structure 901 (in addition to the metallic structure 401) electrically coupled to the device structure …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
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