Patent
US 8,937,317METHOD AND SYSTEM FOR CO-PACKAGING GALLIUM NITRIDE ELECTRONICS
Donald R. Disney
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,937,317Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As described, current flow through the GaN 5 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface 10 of GaN …
FIG. 3, the tops of finger-like 15 projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0038] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 30 including GaN substrate 406 and first Gan epitaxial layer 404. Similar to the …
FIG. 5. One or more pins 532-B may extend from the body of the electronic package for the source region 530-B of the transistor 530, which corresponds with the …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a vertical GaN transistor is co-packaged with a GaN …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
WHAT IS CLAIMED IS: 1 1. An electronic package comprising: 2 a leadframe; 3 a plurality of pins; 4 a gallium nitride (GaN) transistor comprising a drain region, a drift region, 5 a source region, and a gate region, wherein: 6 the drain region comprises a GaN substrate and a drain contact; 7 the drift region comprises a first GaN epitaxial layer coupled to the 8 GaN substrate; 9 the source region is separated from the GaN substrate by the drift 10 region and comprises a source contact; 11 the gate region comprises a second GaN epitaxial layer coupled to 12 the first GaN epitaxial layer and a gate contact; 13 a GaN diode comprising an anode region and a cathode region, wherein: 14 the cathode region comprises the GaN substrate and a cathode 15 contact; and 16 the anode region comprises a third GaN epitaxial layer coupled to 17 the GaN substrate and an anode contact; 18 wherein the drain contact and the anode contact are electrically connected 19 to the leadframe.
1 11. The electronic package of claim 1 wherein the leadframe 2 comprises a bond pad, and further wherein the drain contact and the anode contact are 3 electrically connected to the leadframe via the bond pad.
1 3. The electronic package of claim 2 wherein: 2 the electrical connections of the cathode contact, the source contact, and 3 the gate contact comprises at least one of wire bonds, ribbon bonds, or copper clips.
1 17. The method of claim 13 wherein electrically connecting the anode 2 contact comprises at least one of epoxying, eutectic formation, sintering or soldering.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor (vertical)
GaN diode (vertical)
co-packaged GaN electronic package
Materials described outside the worked examples.
gallium nitride substrate
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As described, current flow through the GaN 5 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 25–400 nm | — |
Thickness | 2–6 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,937,317Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As described, current flow through the GaN 5 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface 10 of GaN …
FIG. 3, the tops of finger-like 15 projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0038] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 30 including GaN substrate 406 and first Gan epitaxial layer 404. Similar to the …
FIG. 5. One or more pins 532-B may extend from the body of the electronic package for the source region 530-B of the transistor 530, which corresponds with the …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a vertical GaN transistor is co-packaged with a GaN …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
WHAT IS CLAIMED IS: 1 1. An electronic package comprising: 2 a leadframe; 3 a plurality of pins; 4 a gallium nitride (GaN) transistor comprising a drain region, a drift region, 5 a source region, and a gate region, wherein: 6 the drain region comprises a GaN substrate and a drain contact; 7 the drift region comprises a first GaN epitaxial layer coupled to the 8 GaN substrate; 9 the source region is separated from the GaN substrate by the drift 10 region and comprises a source contact; 11 the gate region comprises a second GaN epitaxial layer coupled to 12 the first GaN epitaxial layer and a gate contact; 13 a GaN diode comprising an anode region and a cathode region, wherein: 14 the cathode region comprises the GaN substrate and a cathode 15 contact; and 16 the anode region comprises a third GaN epitaxial layer coupled to 17 the GaN substrate and an anode contact; 18 wherein the drain contact and the anode contact are electrically connected 19 to the leadframe.
1 11. The electronic package of claim 1 wherein the leadframe 2 comprises a bond pad, and further wherein the drain contact and the anode contact are 3 electrically connected to the leadframe via the bond pad.
1 3. The electronic package of claim 2 wherein: 2 the electrical connections of the cathode contact, the source contact, and 3 the gate contact comprises at least one of wire bonds, ribbon bonds, or copper clips.
1 17. The method of claim 13 wherein electrically connecting the anode 2 contact comprises at least one of epoxying, eutectic formation, sintering or soldering.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor (vertical)
GaN diode (vertical)
co-packaged GaN electronic package
Materials described outside the worked examples.
gallium nitride substrate
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As described, current flow through the GaN 5 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 25–400 nm | — |
Thickness | 2–6 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,937,317Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As described, current flow through the GaN 5 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface 10 of GaN …
FIG. 3, the tops of finger-like 15 projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0038] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 30 including GaN substrate 406 and first Gan epitaxial layer 404. Similar to the …
FIG. 5. One or more pins 532-B may extend from the body of the electronic package for the source region 530-B of the transistor 530, which corresponds with the …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a vertical GaN transistor is co-packaged with a GaN …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
WHAT IS CLAIMED IS: 1 1. An electronic package comprising: 2 a leadframe; 3 a plurality of pins; 4 a gallium nitride (GaN) transistor comprising a drain region, a drift region, 5 a source region, and a gate region, wherein: 6 the drain region comprises a GaN substrate and a drain contact; 7 the drift region comprises a first GaN epitaxial layer coupled to the 8 GaN substrate; 9 the source region is separated from the GaN substrate by the drift 10 region and comprises a source contact; 11 the gate region comprises a second GaN epitaxial layer coupled to 12 the first GaN epitaxial layer and a gate contact; 13 a GaN diode comprising an anode region and a cathode region, wherein: 14 the cathode region comprises the GaN substrate and a cathode 15 contact; and 16 the anode region comprises a third GaN epitaxial layer coupled to 17 the GaN substrate and an anode contact; 18 wherein the drain contact and the anode contact are electrically connected 19 to the leadframe.
1 11. The electronic package of claim 1 wherein the leadframe 2 comprises a bond pad, and further wherein the drain contact and the anode contact are 3 electrically connected to the leadframe via the bond pad.
1 3. The electronic package of claim 2 wherein: 2 the electrical connections of the cathode contact, the source contact, and 3 the gate contact comprises at least one of wire bonds, ribbon bonds, or copper clips.
1 17. The method of claim 13 wherein electrically connecting the anode 2 contact comprises at least one of epoxying, eutectic formation, sintering or soldering.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor (vertical)
GaN diode (vertical)
co-packaged GaN electronic package
Materials described outside the worked examples.
gallium nitride substrate
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As described, current flow through the GaN 5 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 25–400 nm | — |
Thickness | 2–6 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,937,317Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As described, current flow through the GaN 5 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface 10 of GaN …
FIG. 3, the tops of finger-like 15 projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0038] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 30 including GaN substrate 406 and first Gan epitaxial layer 404. Similar to the …
FIG. 5. One or more pins 532-B may extend from the body of the electronic package for the source region 530-B of the transistor 530, which corresponds with the …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a vertical GaN transistor is co-packaged with a GaN …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
WHAT IS CLAIMED IS: 1 1. An electronic package comprising: 2 a leadframe; 3 a plurality of pins; 4 a gallium nitride (GaN) transistor comprising a drain region, a drift region, 5 a source region, and a gate region, wherein: 6 the drain region comprises a GaN substrate and a drain contact; 7 the drift region comprises a first GaN epitaxial layer coupled to the 8 GaN substrate; 9 the source region is separated from the GaN substrate by the drift 10 region and comprises a source contact; 11 the gate region comprises a second GaN epitaxial layer coupled to 12 the first GaN epitaxial layer and a gate contact; 13 a GaN diode comprising an anode region and a cathode region, wherein: 14 the cathode region comprises the GaN substrate and a cathode 15 contact; and 16 the anode region comprises a third GaN epitaxial layer coupled to 17 the GaN substrate and an anode contact; 18 wherein the drain contact and the anode contact are electrically connected 19 to the leadframe.
1 11. The electronic package of claim 1 wherein the leadframe 2 comprises a bond pad, and further wherein the drain contact and the anode contact are 3 electrically connected to the leadframe via the bond pad.
1 3. The electronic package of claim 2 wherein: 2 the electrical connections of the cathode contact, the source contact, and 3 the gate contact comprises at least one of wire bonds, ribbon bonds, or copper clips.
1 17. The method of claim 13 wherein electrically connecting the anode 2 contact comprises at least one of epoxying, eutectic formation, sintering or soldering.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor (vertical)
GaN diode (vertical)
co-packaged GaN electronic package
Materials described outside the worked examples.
gallium nitride substrate
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As described, current flow through the GaN 5 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 25–400 nm | — |
Thickness | 2–6 µm |
Related documents with shared materials, methods, properties, or citations.
No layer stack recorded.
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface 10 of GaN …
FIG. 3, the tops of finger-like 15 projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0038] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 30 including GaN substrate 406 and first Gan epitaxial layer 404. Similar to the …
FIG. 5. One or more pins 532-B may extend from the body of the electronic package for the source region 530-B of the transistor 530, which corresponds with the …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a vertical GaN transistor is co-packaged with a GaN …
| — |
Thickness | 3.5–4.5 µm | — |
Thickness | 50–500 µm | — |
No layer stack recorded.
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface 10 of GaN …
FIG. 3, the tops of finger-like 15 projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0038] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 30 including GaN substrate 406 and first Gan epitaxial layer 404. Similar to the …
FIG. 5. One or more pins 532-B may extend from the body of the electronic package for the source region 530-B of the transistor 530, which corresponds with the …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a vertical GaN transistor is co-packaged with a GaN …
| — |
Thickness | 3.5–4.5 µm | — |
Thickness | 50–500 µm | — |
No layer stack recorded.
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface 10 of GaN …
FIG. 3, the tops of finger-like 15 projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0038] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 30 including GaN substrate 406 and first Gan epitaxial layer 404. Similar to the …
FIG. 5. One or more pins 532-B may extend from the body of the electronic package for the source region 530-B of the transistor 530, which corresponds with the …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a vertical GaN transistor is co-packaged with a GaN …
| — |
Thickness | 3.5–4.5 µm | — |
Thickness | 50–500 µm | — |
No layer stack recorded.
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface 10 of GaN …
FIG. 3, the tops of finger-like 15 projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0038] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 30 including GaN substrate 406 and first Gan epitaxial layer 404. Similar to the …
FIG. 5. One or more pins 532-B may extend from the body of the electronic package for the source region 530-B of the transistor 530, which corresponds with the …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a vertical GaN transistor is co-packaged with a GaN …
| — |
Thickness | 3.5–4.5 µm | — |
Thickness | 50–500 µm | — |