Patent
US 9,929,652GAN FET WITH INTEGRATED DRIVER AND SLEW RATE CONTROL
Thomas Ribarich, Santosh Sharma, Ju Zhang, Marco Giandalia et al.
NAVITAS SEMICONDUCTOR, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,929,652Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0008]
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit illustrated in
FIG. 5 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capacitor charging circuit as compared to the circuit illustrated in
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UVLO circuit illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a high side reference voltage g eneration circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the invention; [0028]
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the high side control circuit illustrated in
FIG. 30 is a schematic of the level shift I receiver circuit illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0041]
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0042]
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention; [0043]
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of a Boost circuit having an integrated power FET and power FET driver. [0045]
FIG. 39 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0046]
FIG. 40 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0047]
FIG. 41 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0048]
FIG. 42 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0049]
FIG. 43 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0050]
FIG. 44 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0051]
FIG. 45 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0052]
FIG. 46 is as schematic illustration of an embodiment of an integrated power F ET and power FET driver. [0053]
FIG. 47 is as schematic illustration of an embodiment of a power FET driver
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power circuit, comprising: a power capacitor; a power resistor, connected to the power capacitor; and a power integrated circuit, comprising: a GaN-based substrate; a power F ET on the substrate; a driver on the substrate, <~ wherein the driver is configured to charge a gate of the power FET using current from power node; and a first power voltage regulator on the substrate _-.C;Lvu t "n puwui-eceive a reference voltage and to cause current to flow to the power node and through the power resistor to charge the power capacitor, such that a substantially fixed voltage based on the reference wherein the driver is configured to receive current e substantially n xea vo it age v. from the p ower capac P ' and to cha the gate of the power FET th the received current., Currently amended
The power circuit of claim 1, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal. Original
The power circuit of claim 1, wherein the first power voltage regulator is configured to provide current to the capacitor in response to the voltage of the gate of the power F ET becoming greater than a threshold. Original
The power circuit of claim 1, wherein the first power voltage regulator is configured to provide current to the capacitor in response to the voltage of the drain of the power FET becoming less than a threshold. Original
7. The power circuit of claim 1, wherein the power integrated circuit further comprises a second power voltage regulator, wherein the first power voltage regulator is configured to provide current to a first portion of the driver and the first power voltage regulator is configured to provide current to a second portion of the driver. Original
A method of using a power circuit, the method comprising: with a power voltage regulator _ a to r eceive a reier ence vOI L, charging a capacitor resistor;f ence volt; and fn rst power vo it age regu l ator is con n gurea to receive a re f erence voltage and to cause current to flow to the power node and through the power resistor to charge the power capacitor, such that a substantially fixed voltage based on the reference voltage is with a driver connected to the series connected capacitor and resistor, r----------- --- m the -r ---------d capacito r f-I the substantiall y fixed voltage, a t charging a gate of a power FET with l e rece i current, Currently amended
The method of claim 8, wherein the power voltage regulator is configured to provide current to the capacitor while the driver does not charge the gate of the power F ET. Original
The method of claim 8, wherein the gate of the power FET is charged by the driver while the power voltage regulator does not charge the capacitor. Original
The method of claim 8, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the power voltage regulator is configured to provide current to the capacitor in response to the PWM signal. Original
The method of claim 8, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the driver is configured receive current from the capacitor in response to the PWM signal. Original
The of claim 8, wherein the power voltage regulator is configured to provide current to the capacitor in response to the voltage of the gate of the power FET becoming greater than a threshold. Currently amended
The of claim 8, wherein the power voltage regulator is configured to provide current to the capacitor in response to the voltage of the drain of the power FET becoming less than a threshold. Currently amended
A power integrated circuit, comprising: a GaN-based substrate; a power FET on the substrate; a driver on the substrate, 1---", -- wherein the driver is configured to charge a gate of the power FET using current from power node; and age regul a-input/output node, wherein the first power voltage regulator is configured to receive a reference input/output node, such that a voltage based on the reference voltage is generated at the power input/output node, wherein the driver is configured to receive current flowing into the power integrated circuit at the substantially fixed voltage from the power supply input/output node and to charge the gate of the power F ET with the received current., Currently amended
The integrated circuit of claim 15, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the first power voltage regulator is configured to provide current to the power node in response to the PWM signal. Currently amended
The integrated circuit of claim 15, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the L 1 L m m mm g in response to the PWM signal. Currently amended
The integrated circuit of claim 15, wherein the first power voltage regulator is configured to provide current in response to the voltage of the gate of the power FET becoming greater than a threshold. Currently amended
The integrated circuit of claim 15, wherein the first power voltage regulator I circuit, wherein the tra ns *° rr ° ~.'°n °r- °+'* ---A ""--+' ~ °- in response to the voltage of the drain of the power FET becoming less than a threshold. Currently amended
20. The integrated circuit of claim 15, further comprising a second power voltage regulator, wherein the first power voltage regulator is configured to provide current to a first portion of the driver and the first power voltage regulator is configured to provide current to a second portion of
Layer stacks claimed or described, ordered top of device to substrate.
power circuit with GaN-based power integrated circuit
power integrated circuit (GaN-based)
half bridge power conversion circuit
Materials described outside the worked examples.
GaN-based substrate
GaN on silicon
GaN on silicon carbide
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,929,652Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0008]
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit illustrated in
FIG. 5 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capacitor charging circuit as compared to the circuit illustrated in
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UVLO circuit illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a high side reference voltage g eneration circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the invention; [0028]
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the high side control circuit illustrated in
FIG. 30 is a schematic of the level shift I receiver circuit illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0041]
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0042]
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention; [0043]
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of a Boost circuit having an integrated power FET and power FET driver. [0045]
FIG. 39 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0046]
FIG. 40 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0047]
FIG. 41 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0048]
FIG. 42 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0049]
FIG. 43 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0050]
FIG. 44 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0051]
FIG. 45 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0052]
FIG. 46 is as schematic illustration of an embodiment of an integrated power F ET and power FET driver. [0053]
FIG. 47 is as schematic illustration of an embodiment of a power FET driver
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power circuit, comprising: a power capacitor; a power resistor, connected to the power capacitor; and a power integrated circuit, comprising: a GaN-based substrate; a power F ET on the substrate; a driver on the substrate, <~ wherein the driver is configured to charge a gate of the power FET using current from power node; and a first power voltage regulator on the substrate _-.C;Lvu t "n puwui-eceive a reference voltage and to cause current to flow to the power node and through the power resistor to charge the power capacitor, such that a substantially fixed voltage based on the reference wherein the driver is configured to receive current e substantially n xea vo it age v. from the p ower capac P ' and to cha the gate of the power FET th the received current., Currently amended
The power circuit of claim 1, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal. Original
The power circuit of claim 1, wherein the first power voltage regulator is configured to provide current to the capacitor in response to the voltage of the gate of the power F ET becoming greater than a threshold. Original
The power circuit of claim 1, wherein the first power voltage regulator is configured to provide current to the capacitor in response to the voltage of the drain of the power FET becoming less than a threshold. Original
7. The power circuit of claim 1, wherein the power integrated circuit further comprises a second power voltage regulator, wherein the first power voltage regulator is configured to provide current to a first portion of the driver and the first power voltage regulator is configured to provide current to a second portion of the driver. Original
A method of using a power circuit, the method comprising: with a power voltage regulator _ a to r eceive a reier ence vOI L, charging a capacitor resistor;f ence volt; and fn rst power vo it age regu l ator is con n gurea to receive a re f erence voltage and to cause current to flow to the power node and through the power resistor to charge the power capacitor, such that a substantially fixed voltage based on the reference voltage is with a driver connected to the series connected capacitor and resistor, r----------- --- m the -r ---------d capacito r f-I the substantiall y fixed voltage, a t charging a gate of a power FET with l e rece i current, Currently amended
The method of claim 8, wherein the power voltage regulator is configured to provide current to the capacitor while the driver does not charge the gate of the power F ET. Original
The method of claim 8, wherein the gate of the power FET is charged by the driver while the power voltage regulator does not charge the capacitor. Original
The method of claim 8, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the power voltage regulator is configured to provide current to the capacitor in response to the PWM signal. Original
The method of claim 8, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the driver is configured receive current from the capacitor in response to the PWM signal. Original
The of claim 8, wherein the power voltage regulator is configured to provide current to the capacitor in response to the voltage of the gate of the power FET becoming greater than a threshold. Currently amended
The of claim 8, wherein the power voltage regulator is configured to provide current to the capacitor in response to the voltage of the drain of the power FET becoming less than a threshold. Currently amended
A power integrated circuit, comprising: a GaN-based substrate; a power FET on the substrate; a driver on the substrate, 1---", -- wherein the driver is configured to charge a gate of the power FET using current from power node; and age regul a-input/output node, wherein the first power voltage regulator is configured to receive a reference input/output node, such that a voltage based on the reference voltage is generated at the power input/output node, wherein the driver is configured to receive current flowing into the power integrated circuit at the substantially fixed voltage from the power supply input/output node and to charge the gate of the power F ET with the received current., Currently amended
The integrated circuit of claim 15, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the first power voltage regulator is configured to provide current to the power node in response to the PWM signal. Currently amended
The integrated circuit of claim 15, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the L 1 L m m mm g in response to the PWM signal. Currently amended
The integrated circuit of claim 15, wherein the first power voltage regulator is configured to provide current in response to the voltage of the gate of the power FET becoming greater than a threshold. Currently amended
The integrated circuit of claim 15, wherein the first power voltage regulator I circuit, wherein the tra ns *° rr ° ~.'°n °r- °+'* ---A ""--+' ~ °- in response to the voltage of the drain of the power FET becoming less than a threshold. Currently amended
20. The integrated circuit of claim 15, further comprising a second power voltage regulator, wherein the first power voltage regulator is configured to provide current to a first portion of the driver and the first power voltage regulator is configured to provide current to a second portion of
Layer stacks claimed or described, ordered top of device to substrate.
power circuit with GaN-based power integrated circuit
power integrated circuit (GaN-based)
half bridge power conversion circuit
Materials described outside the worked examples.
GaN-based substrate
GaN on silicon
GaN on silicon carbide
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,929,652Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0008]
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit illustrated in
FIG. 5 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capacitor charging circuit as compared to the circuit illustrated in
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UVLO circuit illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a high side reference voltage g eneration circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the invention; [0028]
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the high side control circuit illustrated in
FIG. 30 is a schematic of the level shift I receiver circuit illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0041]
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0042]
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention; [0043]
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of a Boost circuit having an integrated power FET and power FET driver. [0045]
FIG. 39 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0046]
FIG. 40 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0047]
FIG. 41 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0048]
FIG. 42 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0049]
FIG. 43 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0050]
FIG. 44 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0051]
FIG. 45 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0052]
FIG. 46 is as schematic illustration of an embodiment of an integrated power F ET and power FET driver. [0053]
FIG. 47 is as schematic illustration of an embodiment of a power FET driver
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power circuit, comprising: a power capacitor; a power resistor, connected to the power capacitor; and a power integrated circuit, comprising: a GaN-based substrate; a power F ET on the substrate; a driver on the substrate, <~ wherein the driver is configured to charge a gate of the power FET using current from power node; and a first power voltage regulator on the substrate _-.C;Lvu t "n puwui-eceive a reference voltage and to cause current to flow to the power node and through the power resistor to charge the power capacitor, such that a substantially fixed voltage based on the reference wherein the driver is configured to receive current e substantially n xea vo it age v. from the p ower capac P ' and to cha the gate of the power FET th the received current., Currently amended
The power circuit of claim 1, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal. Original
The power circuit of claim 1, wherein the first power voltage regulator is configured to provide current to the capacitor in response to the voltage of the gate of the power F ET becoming greater than a threshold. Original
The power circuit of claim 1, wherein the first power voltage regulator is configured to provide current to the capacitor in response to the voltage of the drain of the power FET becoming less than a threshold. Original
7. The power circuit of claim 1, wherein the power integrated circuit further comprises a second power voltage regulator, wherein the first power voltage regulator is configured to provide current to a first portion of the driver and the first power voltage regulator is configured to provide current to a second portion of the driver. Original
A method of using a power circuit, the method comprising: with a power voltage regulator _ a to r eceive a reier ence vOI L, charging a capacitor resistor;f ence volt; and fn rst power vo it age regu l ator is con n gurea to receive a re f erence voltage and to cause current to flow to the power node and through the power resistor to charge the power capacitor, such that a substantially fixed voltage based on the reference voltage is with a driver connected to the series connected capacitor and resistor, r----------- --- m the -r ---------d capacito r f-I the substantiall y fixed voltage, a t charging a gate of a power FET with l e rece i current, Currently amended
The method of claim 8, wherein the power voltage regulator is configured to provide current to the capacitor while the driver does not charge the gate of the power F ET. Original
The method of claim 8, wherein the gate of the power FET is charged by the driver while the power voltage regulator does not charge the capacitor. Original
The method of claim 8, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the power voltage regulator is configured to provide current to the capacitor in response to the PWM signal. Original
The method of claim 8, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the driver is configured receive current from the capacitor in response to the PWM signal. Original
The of claim 8, wherein the power voltage regulator is configured to provide current to the capacitor in response to the voltage of the gate of the power FET becoming greater than a threshold. Currently amended
The of claim 8, wherein the power voltage regulator is configured to provide current to the capacitor in response to the voltage of the drain of the power FET becoming less than a threshold. Currently amended
A power integrated circuit, comprising: a GaN-based substrate; a power FET on the substrate; a driver on the substrate, 1---", -- wherein the driver is configured to charge a gate of the power FET using current from power node; and age regul a-input/output node, wherein the first power voltage regulator is configured to receive a reference input/output node, such that a voltage based on the reference voltage is generated at the power input/output node, wherein the driver is configured to receive current flowing into the power integrated circuit at the substantially fixed voltage from the power supply input/output node and to charge the gate of the power F ET with the received current., Currently amended
The integrated circuit of claim 15, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the first power voltage regulator is configured to provide current to the power node in response to the PWM signal. Currently amended
The integrated circuit of claim 15, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the L 1 L m m mm g in response to the PWM signal. Currently amended
The integrated circuit of claim 15, wherein the first power voltage regulator is configured to provide current in response to the voltage of the gate of the power FET becoming greater than a threshold. Currently amended
The integrated circuit of claim 15, wherein the first power voltage regulator I circuit, wherein the tra ns *° rr ° ~.'°n °r- °+'* ---A ""--+' ~ °- in response to the voltage of the drain of the power FET becoming less than a threshold. Currently amended
20. The integrated circuit of claim 15, further comprising a second power voltage regulator, wherein the first power voltage regulator is configured to provide current to a first portion of the driver and the first power voltage regulator is configured to provide current to a second portion of
Layer stacks claimed or described, ordered top of device to substrate.
power circuit with GaN-based power integrated circuit
power integrated circuit (GaN-based)
half bridge power conversion circuit
Materials described outside the worked examples.
GaN-based substrate
GaN on silicon
GaN on silicon carbide
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,929,652Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0008]
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit illustrated in
FIG. 5 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capacitor charging circuit as compared to the circuit illustrated in
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UVLO circuit illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a high side reference voltage g eneration circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the invention; [0028]
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the high side control circuit illustrated in
FIG. 30 is a schematic of the level shift I receiver circuit illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0041]
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0042]
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention; [0043]
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of a Boost circuit having an integrated power FET and power FET driver. [0045]
FIG. 39 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0046]
FIG. 40 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0047]
FIG. 41 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0048]
FIG. 42 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0049]
FIG. 43 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0050]
FIG. 44 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0051]
FIG. 45 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0052]
FIG. 46 is as schematic illustration of an embodiment of an integrated power F ET and power FET driver. [0053]
FIG. 47 is as schematic illustration of an embodiment of a power FET driver
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power circuit, comprising: a power capacitor; a power resistor, connected to the power capacitor; and a power integrated circuit, comprising: a GaN-based substrate; a power F ET on the substrate; a driver on the substrate, <~ wherein the driver is configured to charge a gate of the power FET using current from power node; and a first power voltage regulator on the substrate _-.C;Lvu t "n puwui-eceive a reference voltage and to cause current to flow to the power node and through the power resistor to charge the power capacitor, such that a substantially fixed voltage based on the reference wherein the driver is configured to receive current e substantially n xea vo it age v. from the p ower capac P ' and to cha the gate of the power FET th the received current., Currently amended
The power circuit of claim 1, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal. Original
The power circuit of claim 1, wherein the first power voltage regulator is configured to provide current to the capacitor in response to the voltage of the gate of the power F ET becoming greater than a threshold. Original
The power circuit of claim 1, wherein the first power voltage regulator is configured to provide current to the capacitor in response to the voltage of the drain of the power FET becoming less than a threshold. Original
7. The power circuit of claim 1, wherein the power integrated circuit further comprises a second power voltage regulator, wherein the first power voltage regulator is configured to provide current to a first portion of the driver and the first power voltage regulator is configured to provide current to a second portion of the driver. Original
A method of using a power circuit, the method comprising: with a power voltage regulator _ a to r eceive a reier ence vOI L, charging a capacitor resistor;f ence volt; and fn rst power vo it age regu l ator is con n gurea to receive a re f erence voltage and to cause current to flow to the power node and through the power resistor to charge the power capacitor, such that a substantially fixed voltage based on the reference voltage is with a driver connected to the series connected capacitor and resistor, r----------- --- m the -r ---------d capacito r f-I the substantiall y fixed voltage, a t charging a gate of a power FET with l e rece i current, Currently amended
The method of claim 8, wherein the power voltage regulator is configured to provide current to the capacitor while the driver does not charge the gate of the power F ET. Original
The method of claim 8, wherein the gate of the power FET is charged by the driver while the power voltage regulator does not charge the capacitor. Original
The method of claim 8, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the power voltage regulator is configured to provide current to the capacitor in response to the PWM signal. Original
The method of claim 8, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the driver is configured receive current from the capacitor in response to the PWM signal. Original
The of claim 8, wherein the power voltage regulator is configured to provide current to the capacitor in response to the voltage of the gate of the power FET becoming greater than a threshold. Currently amended
The of claim 8, wherein the power voltage regulator is configured to provide current to the capacitor in response to the voltage of the drain of the power FET becoming less than a threshold. Currently amended
A power integrated circuit, comprising: a GaN-based substrate; a power FET on the substrate; a driver on the substrate, 1---", -- wherein the driver is configured to charge a gate of the power FET using current from power node; and age regul a-input/output node, wherein the first power voltage regulator is configured to receive a reference input/output node, such that a voltage based on the reference voltage is generated at the power input/output node, wherein the driver is configured to receive current flowing into the power integrated circuit at the substantially fixed voltage from the power supply input/output node and to charge the gate of the power F ET with the received current., Currently amended
The integrated circuit of claim 15, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the first power voltage regulator is configured to provide current to the power node in response to the PWM signal. Currently amended
The integrated circuit of claim 15, wherein the driver is configured to charge the gate of the power FET according to a received pulse width modulation (PWM) signal, and wherein the L 1 L m m mm g in response to the PWM signal. Currently amended
The integrated circuit of claim 15, wherein the first power voltage regulator is configured to provide current in response to the voltage of the gate of the power FET becoming greater than a threshold. Currently amended
The integrated circuit of claim 15, wherein the first power voltage regulator I circuit, wherein the tra ns *° rr ° ~.'°n °r- °+'* ---A ""--+' ~ °- in response to the voltage of the drain of the power FET becoming less than a threshold. Currently amended
20. The integrated circuit of claim 15, further comprising a second power voltage regulator, wherein the first power voltage regulator is configured to provide current to a first portion of the driver and the first power voltage regulator is configured to provide current to a second portion of
Layer stacks claimed or described, ordered top of device to substrate.
power circuit with GaN-based power integrated circuit
power integrated circuit (GaN-based)
half bridge power conversion circuit
Materials described outside the worked examples.
GaN-based substrate
GaN on silicon
GaN on silicon carbide
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Related documents with shared materials, methods, properties, or citations.
GaN on sapphire
GaN on aluminum nitride
GaN/AlN
AlGaN
InGaN
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 38 is a schematic illustration of a Boost circuit having an integrated power FET and power FET driver. [0045]
FIG. 39 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0046]
FIG. 40 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0047]
FIG. 41 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0048]
FIG. 42 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0049]
FIG. 43 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0050]
FIG. 44 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0051]
FIG. 45 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0052]
FIG. 46 is as schematic illustration of an embodiment of an integrated power F ET and power FET driver. [0053]
FIG. 47 is as schematic illustration of an embodiment of a power FET driver
GaN on sapphire
GaN on aluminum nitride
GaN/AlN
AlGaN
InGaN
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 38 is a schematic illustration of a Boost circuit having an integrated power FET and power FET driver. [0045]
FIG. 39 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0046]
FIG. 40 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0047]
FIG. 41 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0048]
FIG. 42 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0049]
FIG. 43 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0050]
FIG. 44 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0051]
FIG. 45 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0052]
FIG. 46 is as schematic illustration of an embodiment of an integrated power F ET and power FET driver. [0053]
FIG. 47 is as schematic illustration of an embodiment of a power FET driver
GaN on sapphire
GaN on aluminum nitride
GaN/AlN
AlGaN
InGaN
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 38 is a schematic illustration of a Boost circuit having an integrated power FET and power FET driver. [0045]
FIG. 39 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0046]
FIG. 40 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0047]
FIG. 41 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0048]
FIG. 42 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0049]
FIG. 43 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0050]
FIG. 44 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0051]
FIG. 45 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0052]
FIG. 46 is as schematic illustration of an embodiment of an integrated power F ET and power FET driver. [0053]
FIG. 47 is as schematic illustration of an embodiment of a power FET driver
GaN on sapphire
GaN on aluminum nitride
GaN/AlN
AlGaN
InGaN
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 38 is a schematic illustration of a Boost circuit having an integrated power FET and power FET driver. [0045]
FIG. 39 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0046]
FIG. 40 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0047]
FIG. 41 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0048]
FIG. 42 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0049]
FIG. 43 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0050]
FIG. 44 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0051]
FIG. 45 is as schematic illustration of an embodiment of an integrated power FET and power FET driver. [0052]
FIG. 46 is as schematic illustration of an embodiment of an integrated power F ET and power FET driver. [0053]
FIG. 47 is as schematic illustration of an embodiment of a power FET driver