GRAPHENE DEVICES AND SEMICONDUCTOR FIELD EFFECT TRANSISTORS IN 3D HYBRID INTEGRATED CIRCUITS

Phaedon Avouris

Patent

Atlas literature

Patent

US 8,748,871

GRAPHENE DEVICES AND SEMICONDUCTOR FIELD EFFECT TRANSISTORS IN 3D HYBRID INTEGRATED CIRCUITS

Phaedon Avouris, Yanqing Wu, Wenjuan Zhu, Josephine B. Chang et al.

2014-06-10·US

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

13 independent · 5 dependent

1
Independentgraphenethree-dimensional integrated circuit with dual-gate graphene device
A three-dimensional integrated circuit comprising: a semiconductor device; an insulator formed on the semiconductor device; an interconnect formed in the insulator; and a graphene device formed on the insulator, the graphene device comprising: a ﬁrst gate electrode formed on the insulator; a ﬁrst g ate dielectric la y er formed on the ﬁrst g ate electrode; a graphene layer formed on the ﬁrst gate dielectric layer, a source region; a drain region; a second gate dielectric layer formed on the graphene layer; and a second gate electrode formed on the second gate dielectric layer.
1. 2
  Dependent← claim 1semiconductor device with contact via
  The circuit of claim 1, wherein the semiconductor device comprises: a semiconductor substrate; a source region; a drain region; a gate dielectric layer disposed on a substrate; Attorney Docket No. Y O R₉₂₀₁₀₀₄₁₀U S 2 Page 3 of 9 Application Serial No: 13/352,73 7 In Reply to Oﬃce Action dated: a gate electrode formed on the gate dielectric layer, wherein the insulator is formed on the source region, the drain region, the gate electrode and the semiconductor substrate; and a contact via formed in the insulator in contact with the source region, the drain region and a gate region.
2. 3
  Dependent← claim 1graphenetop-gate graphene field-effect transistor
  The circuit of claim 1, wherein the graphene device comprises: a graphene layer formed on the insulator, a source region; a drain region; a gate dielectric layer formed on a graphene channel of the graphene device, the source region and the drain region; and a gate electrode formed on the gate dielectric layer.
3. 4
  Dependent← claim 1graphenebottom-gate graphene field-effect transistor
  The circuit of claim 1, wherein the graphene device comprises: a gate electrode formed on the insulator; a gate dielectric layer formed on the gate electrode; a graphene layer formed on the gate dielectric layer, a source region; and a drain region.
4. 6
  Dependent← claim 1three-dimensional integrated circuit with dual-gate graphene device
  The circuit of claim 1, wherein the interconnect electrically connects the source region, the drain region, and a gate electrode in the semiconductor device to the source region, drain region, and the gate electrode in the graphene device.
5
Independent
canceled
8
Independentgraphenemulti-layer integrated circuit with stacked graphene devices
A multi-layer integrated circuit comprising: a semiconductor device; a ﬁrst insulator formed on the semiconductor device; a ﬁrst interconnect formed in the ﬁrst insulator; a ﬁrst graphene device formed on the ﬁrst insulator; a second insulator formed on the ﬁrst graphene device; a second interconnect formed in the second insulator; and a second graphene device formed on the second insulator s wherein the second interconnect forms a conductive path between at least one of a ﬁrst source material, ﬁrst drain material and ﬁrst gate material of the ﬁrst graphene device, and at least one of a second source material, second drain material and second gate material of the second graphene device.
9
Independentgraphenemulti-chip integrated circuit with through-wafer vias
A multi-chip integrated circuit comprising: Attorney Docket No. Y O R₉₂₀₁₀₀₄₁₀U S 2 Page of 9 Application Serial No: 13/352,73 7 In Reply to Oﬃce Action dated: a ﬁrst three-dimensional integrated circuit, the ﬁrst three-dimensional integrated circuit comprising:; a semiconductor device; an insulator la y er formed on the semiconductor device; an interconnect formed in the insulator; and a graphene device formed on the insulator; an insulator layer; a second three-dimensional integrated circuit; and through wafer vias connecting the ﬁrst three-dimensional integrated circuit and the second three-dimensional integrated circuit.
10
Independent
- 18. Attorney Docket No. Y O R₉₂₀₁₀₀₄₁₀U S 2 Page 6 of 9 canceled
11
Independent
canceled
12
Independent
canceled
13
Independent
canceled
14
Independent
canceled
15
Independent
canceled
16
Independent
canceled
17
Independent
canceled
18
Independent
canceled

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

three-dimensional integrated circuit with dual-gate graphene device

second_gate_electrodesecond gate electrode

second_gate_dielectricsecond gate dielectric

graphenechannel

first_gate_dielectricfirst gate dielectric

first_gate_electrodefirst gate electrode

Materials

Materials described outside the worked examples.

graphene

Channel Material

SiC

Semiconductor Substrate

Why these are connected

Related documents with shared materials, methods, properties, or citations.

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