Patent
US 8,698,201GATE METALLIZATION METHODS FOR SELF-ALIGNED SIDEWALL GATE GaN HEMT
Dean C. Regan
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,698,201Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A. FIG. lA shows that the top opening size shrinks and closes with increasing evaporation thickness, which may result in disconnected gate features, and …
FIG. 2 shows a flow diagram of a self-aligned sidewall gate fabrication process in accordance with the present disclosure; and [0013]
FIG. 3 shows scanning electron microscope (SEM) images of a demonstration of a self-aligned sidewall gate fabrication process in accordance with the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer over the buffer layer and a barrier layer over the channel layer, the method comprising: forming a gate, the gate comprising a first dielectric; forming first sidewal ls on either side and adjacent to the gate, the first sidewalls comprising a second dielectric; selectively etching into the buffer layer to form a mesa for the field effect transistor; depositing a dielectric layer over the mesa; planarizing the dielectric layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the dielectric layer over the mesa are on the same planarized surface; selectively etching and removing the gate to form a vacated region; and depositing metal in the vacated region by ALD to form a metal gate, or plating metal in the vacated region by using current flowing through the barrier layer to the channel layer to form a metal gate.
The method of claim 12 further comprising: forming second sidewalls on either side and adjacent to the first sidewalls, the second sidewall comprising a third dielectric; selectively etching the barrier layer and the channel layer to form a recess into the channel layer on either side of the second sidewalls; Preliminary amendment 4 removing the second sidewal ls to form self-aligned ledges on the epitaxial layer adjacent the first sidewal ls; forming an ohmic regrowth layer over the ledges and over the channel layer; selectively etching the ohmic regrowth layer and the channel layer to form the mesa for the field effect transistor; and forming ohmic contacts on the ohmic regrowth layer for source and drain contacts.
The method of claim 12 wherein the first dielectric comprises Si, SiO2, SiN, SiON, A₁₂₀ 3, HfO2, ZrO, or TiO2.
The method of claim 12 wherein: the barrier layer comprises A l GaN or InA l N; and the channel layer comprises InGaN.
The method of claim 12 wherein the dielectric layer over the mesa comprises Si, SiON, HF O 2, ZrO, or TiO.
The method of claim 12 wherein planarizing the dielectric layer over the mesa comprises chemical mechanical polishing (CMP).
The method of claim 12 wherein the step of depositing metal in the vacated region by ALD to form a metal gate, or plating metal in the vacated region by using current flowing through the barrier layer to the channel layer to form a metal gate further comprises a second chemical mechanical polishing (CMP) process to planarize and clean a gate interface. Preliminary amendment
The method of claim 12 further comprising: electron beam lithography to define a gate head design on the planarized surface; and metallizing a metal gate head using electroplating or evaporation deposition.
The method of claim 12 wherein the metal gate has an aspect ratio of a height of the metal gate to a length of a foot of the metal gate equal to or greater than 5.
A field effect transistor having a substrate, a channel layer, and a barrier layer, the field effect transistor comprising: a gate on the barrier layer, the gate having an aspect ratio of a height of the gate to a length of a foot of the gate equal to or greater than 5; a first sidewall on one side of the gate and adjacent to the gate; and a second sidewall on another side of the gate and adjacent to the gate.
The field effect transistor of claim 23 wherein the field effect transistor is a high electron mobility transistor.
The field effect transistor of claim 23 wherein: the first sidewall is a dielectric; the second sidewall is a dielectric; and the gate comprises a metal silicided gate.
The field effect transistor of claim 23 wherein: the first sidewall is a dielectric; the second sidewall is a dielectric; and the gate comprises a metal gate.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with self-aligned sidewall gate
Materials described outside the worked examples.
first dielectric (gate placeholder)
second dielectric (first sidewall spacer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A. FIG. lA shows that the top opening size shrinks and closes with increasing evaporation thickness, which may result in disconnected gate features, and …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,698,201Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A. FIG. lA shows that the top opening size shrinks and closes with increasing evaporation thickness, which may result in disconnected gate features, and …
FIG. 2 shows a flow diagram of a self-aligned sidewall gate fabrication process in accordance with the present disclosure; and [0013]
FIG. 3 shows scanning electron microscope (SEM) images of a demonstration of a self-aligned sidewall gate fabrication process in accordance with the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
canceled
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A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer over the buffer layer and a barrier layer over the channel layer, the method comprising: forming a gate, the gate comprising a first dielectric; forming first sidewal ls on either side and adjacent to the gate, the first sidewalls comprising a second dielectric; selectively etching into the buffer layer to form a mesa for the field effect transistor; depositing a dielectric layer over the mesa; planarizing the dielectric layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the dielectric layer over the mesa are on the same planarized surface; selectively etching and removing the gate to form a vacated region; and depositing metal in the vacated region by ALD to form a metal gate, or plating metal in the vacated region by using current flowing through the barrier layer to the channel layer to form a metal gate.
The method of claim 12 further comprising: forming second sidewalls on either side and adjacent to the first sidewalls, the second sidewall comprising a third dielectric; selectively etching the barrier layer and the channel layer to form a recess into the channel layer on either side of the second sidewalls; Preliminary amendment 4 removing the second sidewal ls to form self-aligned ledges on the epitaxial layer adjacent the first sidewal ls; forming an ohmic regrowth layer over the ledges and over the channel layer; selectively etching the ohmic regrowth layer and the channel layer to form the mesa for the field effect transistor; and forming ohmic contacts on the ohmic regrowth layer for source and drain contacts.
The method of claim 12 wherein the first dielectric comprises Si, SiO2, SiN, SiON, A₁₂₀ 3, HfO2, ZrO, or TiO2.
The method of claim 12 wherein: the barrier layer comprises A l GaN or InA l N; and the channel layer comprises InGaN.
The method of claim 12 wherein the dielectric layer over the mesa comprises Si, SiON, HF O 2, ZrO, or TiO.
The method of claim 12 wherein planarizing the dielectric layer over the mesa comprises chemical mechanical polishing (CMP).
The method of claim 12 wherein the step of depositing metal in the vacated region by ALD to form a metal gate, or plating metal in the vacated region by using current flowing through the barrier layer to the channel layer to form a metal gate further comprises a second chemical mechanical polishing (CMP) process to planarize and clean a gate interface. Preliminary amendment
The method of claim 12 further comprising: electron beam lithography to define a gate head design on the planarized surface; and metallizing a metal gate head using electroplating or evaporation deposition.
The method of claim 12 wherein the metal gate has an aspect ratio of a height of the metal gate to a length of a foot of the metal gate equal to or greater than 5.
A field effect transistor having a substrate, a channel layer, and a barrier layer, the field effect transistor comprising: a gate on the barrier layer, the gate having an aspect ratio of a height of the gate to a length of a foot of the gate equal to or greater than 5; a first sidewall on one side of the gate and adjacent to the gate; and a second sidewall on another side of the gate and adjacent to the gate.
The field effect transistor of claim 23 wherein the field effect transistor is a high electron mobility transistor.
The field effect transistor of claim 23 wherein: the first sidewall is a dielectric; the second sidewall is a dielectric; and the gate comprises a metal silicided gate.
The field effect transistor of claim 23 wherein: the first sidewall is a dielectric; the second sidewall is a dielectric; and the gate comprises a metal gate.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with self-aligned sidewall gate
Materials described outside the worked examples.
first dielectric (gate placeholder)
second dielectric (first sidewall spacer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A. FIG. lA shows that the top opening size shrinks and closes with increasing evaporation thickness, which may result in disconnected gate features, and …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,698,201Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A. FIG. lA shows that the top opening size shrinks and closes with increasing evaporation thickness, which may result in disconnected gate features, and …
FIG. 2 shows a flow diagram of a self-aligned sidewall gate fabrication process in accordance with the present disclosure; and [0013]
FIG. 3 shows scanning electron microscope (SEM) images of a demonstration of a self-aligned sidewall gate fabrication process in accordance with the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer over the buffer layer and a barrier layer over the channel layer, the method comprising: forming a gate, the gate comprising a first dielectric; forming first sidewal ls on either side and adjacent to the gate, the first sidewalls comprising a second dielectric; selectively etching into the buffer layer to form a mesa for the field effect transistor; depositing a dielectric layer over the mesa; planarizing the dielectric layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the dielectric layer over the mesa are on the same planarized surface; selectively etching and removing the gate to form a vacated region; and depositing metal in the vacated region by ALD to form a metal gate, or plating metal in the vacated region by using current flowing through the barrier layer to the channel layer to form a metal gate.
The method of claim 12 further comprising: forming second sidewalls on either side and adjacent to the first sidewalls, the second sidewall comprising a third dielectric; selectively etching the barrier layer and the channel layer to form a recess into the channel layer on either side of the second sidewalls; Preliminary amendment 4 removing the second sidewal ls to form self-aligned ledges on the epitaxial layer adjacent the first sidewal ls; forming an ohmic regrowth layer over the ledges and over the channel layer; selectively etching the ohmic regrowth layer and the channel layer to form the mesa for the field effect transistor; and forming ohmic contacts on the ohmic regrowth layer for source and drain contacts.
The method of claim 12 wherein the first dielectric comprises Si, SiO2, SiN, SiON, A₁₂₀ 3, HfO2, ZrO, or TiO2.
The method of claim 12 wherein: the barrier layer comprises A l GaN or InA l N; and the channel layer comprises InGaN.
The method of claim 12 wherein the dielectric layer over the mesa comprises Si, SiON, HF O 2, ZrO, or TiO.
The method of claim 12 wherein planarizing the dielectric layer over the mesa comprises chemical mechanical polishing (CMP).
The method of claim 12 wherein the step of depositing metal in the vacated region by ALD to form a metal gate, or plating metal in the vacated region by using current flowing through the barrier layer to the channel layer to form a metal gate further comprises a second chemical mechanical polishing (CMP) process to planarize and clean a gate interface. Preliminary amendment
The method of claim 12 further comprising: electron beam lithography to define a gate head design on the planarized surface; and metallizing a metal gate head using electroplating or evaporation deposition.
The method of claim 12 wherein the metal gate has an aspect ratio of a height of the metal gate to a length of a foot of the metal gate equal to or greater than 5.
A field effect transistor having a substrate, a channel layer, and a barrier layer, the field effect transistor comprising: a gate on the barrier layer, the gate having an aspect ratio of a height of the gate to a length of a foot of the gate equal to or greater than 5; a first sidewall on one side of the gate and adjacent to the gate; and a second sidewall on another side of the gate and adjacent to the gate.
The field effect transistor of claim 23 wherein the field effect transistor is a high electron mobility transistor.
The field effect transistor of claim 23 wherein: the first sidewall is a dielectric; the second sidewall is a dielectric; and the gate comprises a metal silicided gate.
The field effect transistor of claim 23 wherein: the first sidewall is a dielectric; the second sidewall is a dielectric; and the gate comprises a metal gate.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with self-aligned sidewall gate
Materials described outside the worked examples.
first dielectric (gate placeholder)
second dielectric (first sidewall spacer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A. FIG. lA shows that the top opening size shrinks and closes with increasing evaporation thickness, which may result in disconnected gate features, and …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,698,201Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A. FIG. lA shows that the top opening size shrinks and closes with increasing evaporation thickness, which may result in disconnected gate features, and …
FIG. 2 shows a flow diagram of a self-aligned sidewall gate fabrication process in accordance with the present disclosure; and [0013]
FIG. 3 shows scanning electron microscope (SEM) images of a demonstration of a self-aligned sidewall gate fabrication process in accordance with the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
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A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer over the buffer layer and a barrier layer over the channel layer, the method comprising: forming a gate, the gate comprising a first dielectric; forming first sidewal ls on either side and adjacent to the gate, the first sidewalls comprising a second dielectric; selectively etching into the buffer layer to form a mesa for the field effect transistor; depositing a dielectric layer over the mesa; planarizing the dielectric layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the dielectric layer over the mesa are on the same planarized surface; selectively etching and removing the gate to form a vacated region; and depositing metal in the vacated region by ALD to form a metal gate, or plating metal in the vacated region by using current flowing through the barrier layer to the channel layer to form a metal gate.
The method of claim 12 further comprising: forming second sidewalls on either side and adjacent to the first sidewalls, the second sidewall comprising a third dielectric; selectively etching the barrier layer and the channel layer to form a recess into the channel layer on either side of the second sidewalls; Preliminary amendment 4 removing the second sidewal ls to form self-aligned ledges on the epitaxial layer adjacent the first sidewal ls; forming an ohmic regrowth layer over the ledges and over the channel layer; selectively etching the ohmic regrowth layer and the channel layer to form the mesa for the field effect transistor; and forming ohmic contacts on the ohmic regrowth layer for source and drain contacts.
The method of claim 12 wherein the first dielectric comprises Si, SiO2, SiN, SiON, A₁₂₀ 3, HfO2, ZrO, or TiO2.
The method of claim 12 wherein: the barrier layer comprises A l GaN or InA l N; and the channel layer comprises InGaN.
The method of claim 12 wherein the dielectric layer over the mesa comprises Si, SiON, HF O 2, ZrO, or TiO.
The method of claim 12 wherein planarizing the dielectric layer over the mesa comprises chemical mechanical polishing (CMP).
The method of claim 12 wherein the step of depositing metal in the vacated region by ALD to form a metal gate, or plating metal in the vacated region by using current flowing through the barrier layer to the channel layer to form a metal gate further comprises a second chemical mechanical polishing (CMP) process to planarize and clean a gate interface. Preliminary amendment
The method of claim 12 further comprising: electron beam lithography to define a gate head design on the planarized surface; and metallizing a metal gate head using electroplating or evaporation deposition.
The method of claim 12 wherein the metal gate has an aspect ratio of a height of the metal gate to a length of a foot of the metal gate equal to or greater than 5.
A field effect transistor having a substrate, a channel layer, and a barrier layer, the field effect transistor comprising: a gate on the barrier layer, the gate having an aspect ratio of a height of the gate to a length of a foot of the gate equal to or greater than 5; a first sidewall on one side of the gate and adjacent to the gate; and a second sidewall on another side of the gate and adjacent to the gate.
The field effect transistor of claim 23 wherein the field effect transistor is a high electron mobility transistor.
The field effect transistor of claim 23 wherein: the first sidewall is a dielectric; the second sidewall is a dielectric; and the gate comprises a metal silicided gate.
The field effect transistor of claim 23 wherein: the first sidewall is a dielectric; the second sidewall is a dielectric; and the gate comprises a metal gate.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with self-aligned sidewall gate
Materials described outside the worked examples.
first dielectric (gate placeholder)
second dielectric (first sidewall spacer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A. FIG. lA shows that the top opening size shrinks and closes with increasing evaporation thickness, which may result in disconnected gate features, and …
Related documents with shared materials, methods, properties, or citations.
first dielectric
second dielectric
third dielectric
AlGaN
InAlN
InGaN
fourth dielectric (planarization layer over mesa)
GaN
n+ InN
InN
Al₂O₃ (high-k gate dielectric)
Al₂O₃
HfO₂ (high-k gate dielectric)
HfO₂
TiO₂ (high-k gate dielectric)
TiO₂
metal silicided gate
FIG. 3 shows scanning electron microscope (SEM) images of a demonstration of a self-aligned sidewall gate fabrication process in accordance with the present …
first dielectric
second dielectric
third dielectric
AlGaN
InAlN
InGaN
fourth dielectric (planarization layer over mesa)
GaN
n+ InN
InN
Al₂O₃ (high-k gate dielectric)
Al₂O₃
HfO₂ (high-k gate dielectric)
HfO₂
TiO₂ (high-k gate dielectric)
TiO₂
metal silicided gate
FIG. 3 shows scanning electron microscope (SEM) images of a demonstration of a self-aligned sidewall gate fabrication process in accordance with the present …
first dielectric
second dielectric
third dielectric
AlGaN
InAlN
InGaN
fourth dielectric (planarization layer over mesa)
GaN
n+ InN
InN
Al₂O₃ (high-k gate dielectric)
Al₂O₃
HfO₂ (high-k gate dielectric)
HfO₂
TiO₂ (high-k gate dielectric)
TiO₂
metal silicided gate
FIG. 3 shows scanning electron microscope (SEM) images of a demonstration of a self-aligned sidewall gate fabrication process in accordance with the present …
first dielectric
second dielectric
third dielectric
AlGaN
InAlN
InGaN
fourth dielectric (planarization layer over mesa)
GaN
n+ InN
InN
Al₂O₃ (high-k gate dielectric)
Al₂O₃
HfO₂ (high-k gate dielectric)
HfO₂
TiO₂ (high-k gate dielectric)
TiO₂
metal silicided gate
FIG. 3 shows scanning electron microscope (SEM) images of a demonstration of a self-aligned sidewall gate fabrication process in accordance with the present …