Patent
US 10,659,032GaN-ON-SAPPHIRE MONOLITHICALLY INTEGRATED POWER CONVERTER
Brian HUGHES
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,659,032Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 F shows a photograph of a fabricated half bridge circuit including gate drivers in accordance with the present disclosure; [0017]
FIG. 2C shows the temperature rise across each layer for a power switch fabricated with GaN-on-Si in accordance with the prior art compared the temperature …
FIG. 3 shows a comparison of the estimated costs for the epi, the substrate, and the processing for Si SJMOSFET, GaN-on-Si, and GaN-on-sapphire, and shows that …
FIG. 4 shows a graph of vertical power loop inductance vs. loop height h in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-15.. Canceled
Canceled
A method for fabricating a half bridge circuit comprising: growing GaN epitaxy on a sapphire wafer; fabricating an upper switch and a lower switch in the GaN epitaxy; forming a first gate driver in the GaN epitaxy; forming a second gate driver in the GaN epitaxy; forming a first metal post; forming a second metal post; forming a first conductor coupled to the upper switch, wherein a portion of the first conductor is supported by the first and second metal posts on a plane vertically separated from the upper switch and the lower switch by a height; forming a second conductor coupled to the lower switch, wherein a portion of the second conductor is supported by the first and second metal posts on a plane vertically separated from the upper switch and the lower switch by the a height; providing a capacitor coupled between the portion of the first conductor and the portion of the second conductor; and forming interconnects between the first gate driver, the upper switch, the second gate driver, the lower switch, the first metal post, the second metal post, the first conductor, and the second conductor to form one or more half bridge integrated circuits. Currently amended
The method of claim 16 further comprising: testing the half bridge integrated circuits on the wafer. Original
The method of claim 16 further comprising: dicing the sapphire wafer into half bridge die each having a sapphire substrate; and directly attaching the sapphire substrate to a heat sink, Original
The method of claim 16 wherein: the GaN epitaxy is about 2 m thick. Currently amended
The method of claim 16 wherein: a switched current passes through the upper switch and the lower switch; and a return current passes through the portion of the first conductor and the portion of the second conductor; wherein a power loop inductance in a path for the switched current and the return current depends on the height; and wherein the height ranges from 1 m to 100 m. Currently amended
The method of claim 16 wherein a switching voltage ranges from 10 volts to 1000 volts. Original
A method of providing a half bridge circuit comprising: providing a sapphire substrate; providing a GaN upper switch on the sapphire substrate; providing a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch; providing a first conductor coupled to the upper switch; providing a second conductor coupled to the lower switch; providing a portion of the first conductor and a portion of the second conductor on a plane vertically separated by a height from the upper switch and the lower switch; providing a first post coupled between the upper switch and the portion of the first conductor for supporting the portion of the first conductor and the portion of the second conductor on the plane vertically separated by the height from the upper switch and the lower switch; providing a second post coupled between the lower switch and the portion of the second conductor for supporting the portion of the first conductor and the portion of the second conductor on the plane vertically separated by the height from the upper switch and the lower switch; and providing a capacitor coupled between the portion of the first conductor and the portion of the second conductor. New
The method of claim 24 further comprising: passing a switched current passes through the upper switch and the lower switch; and passing a return current passes through the portion of the first conductor and the portion of the second conductor; wherein a power loop inductance in a path for the switched current and the return current depends on the height. New
The method of claim 24 wherein the height ranges from 1 m to 100 m. New
The method of claim 24 wherein the power loop inductance ranges from less than 50 pH to 200 pH. New
The method of claim 24 wherein a switching voltage ranges from 10 volts to 1000 volts. New
The method of claim 24 wherein the upper switch and the lower switch comprise normally-off n-channel GaN transistors. New
The method of claim 24 wherein a space between the plane and the upper and lower switches comprises gas, air, polyimide or benzocyclobutene (BCB). New
The method of claim 24: wherein the first post is a first bump contact, a first metallic post, or a first nonmetallic post comprising a second portion of the first conductor; and wherein the second post is a second bump contact, a second metallic post, or a second nonmetallic post comprising a second portion of the second conductor. New
The method of claim 24 further comprising: providing a first gate driver; and providing a second gate driver; wherein the upper switch comprises a first field effect transistor having a source, a drain, and a gate coupled to the first gate driver; wherein the lower switch comprises a second field effect transistor having a source, a drain, and a gate coupled to the second gate driver; wherein the source of the upper switch is connected to the drain of the lower switch; wherein the source of the upper switch is coupled to the first gate driver; wherein the source of the lower switch is coupled to the second gate driver; wherein an alternating circuit source is connected to the source of the upper switch and the drain of the lower switch; wherein a positive voltage source is connected to the capacitor and the drain of the upper switch; and wherein a negative voltage source is connected to the capacitor and the source of the lower switch. New
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-sapphire monolithically integrated half bridge circuit
Materials described outside the worked examples.
GaN epitaxy
GaN
sapphire substrate
Al₂O₃
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 shows a graph of vertical power loop inductance vs. loop height h in accordance with the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
claimed power loop inductance range | ≤ 200 | — |
estimated power loop inductance at height h=5 µm for 200W 400V half bridge | ≤ 50 | — |
enabled switching frequency range due to ultra-low inductance |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,659,032Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 F shows a photograph of a fabricated half bridge circuit including gate drivers in accordance with the present disclosure; [0017]
FIG. 2C shows the temperature rise across each layer for a power switch fabricated with GaN-on-Si in accordance with the prior art compared the temperature …
FIG. 3 shows a comparison of the estimated costs for the epi, the substrate, and the processing for Si SJMOSFET, GaN-on-Si, and GaN-on-sapphire, and shows that …
FIG. 4 shows a graph of vertical power loop inductance vs. loop height h in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-15.. Canceled
Canceled
A method for fabricating a half bridge circuit comprising: growing GaN epitaxy on a sapphire wafer; fabricating an upper switch and a lower switch in the GaN epitaxy; forming a first gate driver in the GaN epitaxy; forming a second gate driver in the GaN epitaxy; forming a first metal post; forming a second metal post; forming a first conductor coupled to the upper switch, wherein a portion of the first conductor is supported by the first and second metal posts on a plane vertically separated from the upper switch and the lower switch by a height; forming a second conductor coupled to the lower switch, wherein a portion of the second conductor is supported by the first and second metal posts on a plane vertically separated from the upper switch and the lower switch by the a height; providing a capacitor coupled between the portion of the first conductor and the portion of the second conductor; and forming interconnects between the first gate driver, the upper switch, the second gate driver, the lower switch, the first metal post, the second metal post, the first conductor, and the second conductor to form one or more half bridge integrated circuits. Currently amended
The method of claim 16 further comprising: testing the half bridge integrated circuits on the wafer. Original
The method of claim 16 further comprising: dicing the sapphire wafer into half bridge die each having a sapphire substrate; and directly attaching the sapphire substrate to a heat sink, Original
The method of claim 16 wherein: the GaN epitaxy is about 2 m thick. Currently amended
The method of claim 16 wherein: a switched current passes through the upper switch and the lower switch; and a return current passes through the portion of the first conductor and the portion of the second conductor; wherein a power loop inductance in a path for the switched current and the return current depends on the height; and wherein the height ranges from 1 m to 100 m. Currently amended
The method of claim 16 wherein a switching voltage ranges from 10 volts to 1000 volts. Original
A method of providing a half bridge circuit comprising: providing a sapphire substrate; providing a GaN upper switch on the sapphire substrate; providing a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch; providing a first conductor coupled to the upper switch; providing a second conductor coupled to the lower switch; providing a portion of the first conductor and a portion of the second conductor on a plane vertically separated by a height from the upper switch and the lower switch; providing a first post coupled between the upper switch and the portion of the first conductor for supporting the portion of the first conductor and the portion of the second conductor on the plane vertically separated by the height from the upper switch and the lower switch; providing a second post coupled between the lower switch and the portion of the second conductor for supporting the portion of the first conductor and the portion of the second conductor on the plane vertically separated by the height from the upper switch and the lower switch; and providing a capacitor coupled between the portion of the first conductor and the portion of the second conductor. New
The method of claim 24 further comprising: passing a switched current passes through the upper switch and the lower switch; and passing a return current passes through the portion of the first conductor and the portion of the second conductor; wherein a power loop inductance in a path for the switched current and the return current depends on the height. New
The method of claim 24 wherein the height ranges from 1 m to 100 m. New
The method of claim 24 wherein the power loop inductance ranges from less than 50 pH to 200 pH. New
The method of claim 24 wherein a switching voltage ranges from 10 volts to 1000 volts. New
The method of claim 24 wherein the upper switch and the lower switch comprise normally-off n-channel GaN transistors. New
The method of claim 24 wherein a space between the plane and the upper and lower switches comprises gas, air, polyimide or benzocyclobutene (BCB). New
The method of claim 24: wherein the first post is a first bump contact, a first metallic post, or a first nonmetallic post comprising a second portion of the first conductor; and wherein the second post is a second bump contact, a second metallic post, or a second nonmetallic post comprising a second portion of the second conductor. New
The method of claim 24 further comprising: providing a first gate driver; and providing a second gate driver; wherein the upper switch comprises a first field effect transistor having a source, a drain, and a gate coupled to the first gate driver; wherein the lower switch comprises a second field effect transistor having a source, a drain, and a gate coupled to the second gate driver; wherein the source of the upper switch is connected to the drain of the lower switch; wherein the source of the upper switch is coupled to the first gate driver; wherein the source of the lower switch is coupled to the second gate driver; wherein an alternating circuit source is connected to the source of the upper switch and the drain of the lower switch; wherein a positive voltage source is connected to the capacitor and the drain of the upper switch; and wherein a negative voltage source is connected to the capacitor and the source of the lower switch. New
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-sapphire monolithically integrated half bridge circuit
Materials described outside the worked examples.
GaN epitaxy
GaN
sapphire substrate
Al₂O₃
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 shows a graph of vertical power loop inductance vs. loop height h in accordance with the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
claimed power loop inductance range | ≤ 200 | — |
estimated power loop inductance at height h=5 µm for 200W 400V half bridge | ≤ 50 | — |
enabled switching frequency range due to ultra-low inductance |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,659,032Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 F shows a photograph of a fabricated half bridge circuit including gate drivers in accordance with the present disclosure; [0017]
FIG. 2C shows the temperature rise across each layer for a power switch fabricated with GaN-on-Si in accordance with the prior art compared the temperature …
FIG. 3 shows a comparison of the estimated costs for the epi, the substrate, and the processing for Si SJMOSFET, GaN-on-Si, and GaN-on-sapphire, and shows that …
FIG. 4 shows a graph of vertical power loop inductance vs. loop height h in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-15.. Canceled
Canceled
A method for fabricating a half bridge circuit comprising: growing GaN epitaxy on a sapphire wafer; fabricating an upper switch and a lower switch in the GaN epitaxy; forming a first gate driver in the GaN epitaxy; forming a second gate driver in the GaN epitaxy; forming a first metal post; forming a second metal post; forming a first conductor coupled to the upper switch, wherein a portion of the first conductor is supported by the first and second metal posts on a plane vertically separated from the upper switch and the lower switch by a height; forming a second conductor coupled to the lower switch, wherein a portion of the second conductor is supported by the first and second metal posts on a plane vertically separated from the upper switch and the lower switch by the a height; providing a capacitor coupled between the portion of the first conductor and the portion of the second conductor; and forming interconnects between the first gate driver, the upper switch, the second gate driver, the lower switch, the first metal post, the second metal post, the first conductor, and the second conductor to form one or more half bridge integrated circuits. Currently amended
The method of claim 16 further comprising: testing the half bridge integrated circuits on the wafer. Original
The method of claim 16 further comprising: dicing the sapphire wafer into half bridge die each having a sapphire substrate; and directly attaching the sapphire substrate to a heat sink, Original
The method of claim 16 wherein: the GaN epitaxy is about 2 m thick. Currently amended
The method of claim 16 wherein: a switched current passes through the upper switch and the lower switch; and a return current passes through the portion of the first conductor and the portion of the second conductor; wherein a power loop inductance in a path for the switched current and the return current depends on the height; and wherein the height ranges from 1 m to 100 m. Currently amended
The method of claim 16 wherein a switching voltage ranges from 10 volts to 1000 volts. Original
A method of providing a half bridge circuit comprising: providing a sapphire substrate; providing a GaN upper switch on the sapphire substrate; providing a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch; providing a first conductor coupled to the upper switch; providing a second conductor coupled to the lower switch; providing a portion of the first conductor and a portion of the second conductor on a plane vertically separated by a height from the upper switch and the lower switch; providing a first post coupled between the upper switch and the portion of the first conductor for supporting the portion of the first conductor and the portion of the second conductor on the plane vertically separated by the height from the upper switch and the lower switch; providing a second post coupled between the lower switch and the portion of the second conductor for supporting the portion of the first conductor and the portion of the second conductor on the plane vertically separated by the height from the upper switch and the lower switch; and providing a capacitor coupled between the portion of the first conductor and the portion of the second conductor. New
The method of claim 24 further comprising: passing a switched current passes through the upper switch and the lower switch; and passing a return current passes through the portion of the first conductor and the portion of the second conductor; wherein a power loop inductance in a path for the switched current and the return current depends on the height. New
The method of claim 24 wherein the height ranges from 1 m to 100 m. New
The method of claim 24 wherein the power loop inductance ranges from less than 50 pH to 200 pH. New
The method of claim 24 wherein a switching voltage ranges from 10 volts to 1000 volts. New
The method of claim 24 wherein the upper switch and the lower switch comprise normally-off n-channel GaN transistors. New
The method of claim 24 wherein a space between the plane and the upper and lower switches comprises gas, air, polyimide or benzocyclobutene (BCB). New
The method of claim 24: wherein the first post is a first bump contact, a first metallic post, or a first nonmetallic post comprising a second portion of the first conductor; and wherein the second post is a second bump contact, a second metallic post, or a second nonmetallic post comprising a second portion of the second conductor. New
The method of claim 24 further comprising: providing a first gate driver; and providing a second gate driver; wherein the upper switch comprises a first field effect transistor having a source, a drain, and a gate coupled to the first gate driver; wherein the lower switch comprises a second field effect transistor having a source, a drain, and a gate coupled to the second gate driver; wherein the source of the upper switch is connected to the drain of the lower switch; wherein the source of the upper switch is coupled to the first gate driver; wherein the source of the lower switch is coupled to the second gate driver; wherein an alternating circuit source is connected to the source of the upper switch and the drain of the lower switch; wherein a positive voltage source is connected to the capacitor and the drain of the upper switch; and wherein a negative voltage source is connected to the capacitor and the source of the lower switch. New
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-sapphire monolithically integrated half bridge circuit
Materials described outside the worked examples.
GaN epitaxy
GaN
sapphire substrate
Al₂O₃
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 shows a graph of vertical power loop inductance vs. loop height h in accordance with the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
claimed power loop inductance range | ≤ 200 | — |
estimated power loop inductance at height h=5 µm for 200W 400V half bridge | ≤ 50 | — |
enabled switching frequency range due to ultra-low inductance |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,659,032Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 F shows a photograph of a fabricated half bridge circuit including gate drivers in accordance with the present disclosure; [0017]
FIG. 2C shows the temperature rise across each layer for a power switch fabricated with GaN-on-Si in accordance with the prior art compared the temperature …
FIG. 3 shows a comparison of the estimated costs for the epi, the substrate, and the processing for Si SJMOSFET, GaN-on-Si, and GaN-on-sapphire, and shows that …
FIG. 4 shows a graph of vertical power loop inductance vs. loop height h in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-15.. Canceled
Canceled
A method for fabricating a half bridge circuit comprising: growing GaN epitaxy on a sapphire wafer; fabricating an upper switch and a lower switch in the GaN epitaxy; forming a first gate driver in the GaN epitaxy; forming a second gate driver in the GaN epitaxy; forming a first metal post; forming a second metal post; forming a first conductor coupled to the upper switch, wherein a portion of the first conductor is supported by the first and second metal posts on a plane vertically separated from the upper switch and the lower switch by a height; forming a second conductor coupled to the lower switch, wherein a portion of the second conductor is supported by the first and second metal posts on a plane vertically separated from the upper switch and the lower switch by the a height; providing a capacitor coupled between the portion of the first conductor and the portion of the second conductor; and forming interconnects between the first gate driver, the upper switch, the second gate driver, the lower switch, the first metal post, the second metal post, the first conductor, and the second conductor to form one or more half bridge integrated circuits. Currently amended
The method of claim 16 further comprising: testing the half bridge integrated circuits on the wafer. Original
The method of claim 16 further comprising: dicing the sapphire wafer into half bridge die each having a sapphire substrate; and directly attaching the sapphire substrate to a heat sink, Original
The method of claim 16 wherein: the GaN epitaxy is about 2 m thick. Currently amended
The method of claim 16 wherein: a switched current passes through the upper switch and the lower switch; and a return current passes through the portion of the first conductor and the portion of the second conductor; wherein a power loop inductance in a path for the switched current and the return current depends on the height; and wherein the height ranges from 1 m to 100 m. Currently amended
The method of claim 16 wherein a switching voltage ranges from 10 volts to 1000 volts. Original
A method of providing a half bridge circuit comprising: providing a sapphire substrate; providing a GaN upper switch on the sapphire substrate; providing a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch; providing a first conductor coupled to the upper switch; providing a second conductor coupled to the lower switch; providing a portion of the first conductor and a portion of the second conductor on a plane vertically separated by a height from the upper switch and the lower switch; providing a first post coupled between the upper switch and the portion of the first conductor for supporting the portion of the first conductor and the portion of the second conductor on the plane vertically separated by the height from the upper switch and the lower switch; providing a second post coupled between the lower switch and the portion of the second conductor for supporting the portion of the first conductor and the portion of the second conductor on the plane vertically separated by the height from the upper switch and the lower switch; and providing a capacitor coupled between the portion of the first conductor and the portion of the second conductor. New
The method of claim 24 further comprising: passing a switched current passes through the upper switch and the lower switch; and passing a return current passes through the portion of the first conductor and the portion of the second conductor; wherein a power loop inductance in a path for the switched current and the return current depends on the height. New
The method of claim 24 wherein the height ranges from 1 m to 100 m. New
The method of claim 24 wherein the power loop inductance ranges from less than 50 pH to 200 pH. New
The method of claim 24 wherein a switching voltage ranges from 10 volts to 1000 volts. New
The method of claim 24 wherein the upper switch and the lower switch comprise normally-off n-channel GaN transistors. New
The method of claim 24 wherein a space between the plane and the upper and lower switches comprises gas, air, polyimide or benzocyclobutene (BCB). New
The method of claim 24: wherein the first post is a first bump contact, a first metallic post, or a first nonmetallic post comprising a second portion of the first conductor; and wherein the second post is a second bump contact, a second metallic post, or a second nonmetallic post comprising a second portion of the second conductor. New
The method of claim 24 further comprising: providing a first gate driver; and providing a second gate driver; wherein the upper switch comprises a first field effect transistor having a source, a drain, and a gate coupled to the first gate driver; wherein the lower switch comprises a second field effect transistor having a source, a drain, and a gate coupled to the second gate driver; wherein the source of the upper switch is connected to the drain of the lower switch; wherein the source of the upper switch is coupled to the first gate driver; wherein the source of the lower switch is coupled to the second gate driver; wherein an alternating circuit source is connected to the source of the upper switch and the drain of the lower switch; wherein a positive voltage source is connected to the capacitor and the drain of the upper switch; and wherein a negative voltage source is connected to the capacitor and the source of the lower switch. New
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-sapphire monolithically integrated half bridge circuit
Materials described outside the worked examples.
GaN epitaxy
GaN
sapphire substrate
Al₂O₃
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 shows a graph of vertical power loop inductance vs. loop height h in accordance with the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
claimed power loop inductance range | ≤ 200 | — |
estimated power loop inductance at height h=5 µm for 200W 400V half bridge | ≤ 50 | — |
enabled switching frequency range due to ultra-low inductance |
Related documents with shared materials, methods, properties, or citations.
polyimide
benzocyclobutene (BCB)
air/gas
| 1–100 |
| — |
claimed switching voltage range | 10–1000 | — |
voltage overshoot limit during switching | ≤ 20 | — |
claimed gate driver drive voltage upper limit | ≤ 20 | — |
polyimide
benzocyclobutene (BCB)
air/gas
| 1–100 |
| — |
claimed switching voltage range | 10–1000 | — |
voltage overshoot limit during switching | ≤ 20 | — |
claimed gate driver drive voltage upper limit | ≤ 20 | — |
polyimide
benzocyclobutene (BCB)
air/gas
| 1–100 |
| — |
claimed switching voltage range | 10–1000 | — |
voltage overshoot limit during switching | ≤ 20 | — |
claimed gate driver drive voltage upper limit | ≤ 20 | — |
polyimide
benzocyclobutene (BCB)
air/gas
| 1–100 |
| — |
claimed switching voltage range | 10–1000 | — |
voltage overshoot limit during switching | ≤ 20 | — |
claimed gate driver drive voltage upper limit | ≤ 20 | — |