Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 schematically shows a cross-sectional diagram of a folded channel gallium nitride based field-effect transistor according to an embodiment of the present …
FIG. 2 schematically shows a flowchart of a method of manufacturing a folded channel gallium nitride based field- effect transistor according to an embodiment of …
FIGS. 3A to 3K schematically show cross-sectional dia- grams obtained after performing some steps in a method of manufacturing a folded channel gallium nitride …
FIG. 4 schematically shows a cross-sectional diagram of a multi-heterojunction layer of a folded channel gallium nitride based field-effect transistor according …
FIG. 5 schematically shows two cross-sectional diagrams of gate grooves of a folded channel gallium nitride based field-effect transistor according to an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A folded channel gallium nitride based field-effect transistor, comprising: a base layer, comprising a nitride buffer layer and a gallium nitride semi-insulating layer formed sequen-tially on a substrate from bottom to top, wherein a channel region comprising at least one parallel extended groove is formed on an upper surface of the gallium nitride semi-insulating layer; a multi-heterojunction layer, comprising a channel layer and a barrier layer alternatingly stacked from bottom to top on the gallium nitride semi-insulating layer, wherein a heterojunction is formed between the barrier layer and the channel layer that are adjacent; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove, so as to adjust a charge B₂ balance within the channel region corresponding to on and off states of the field-effect transistor; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the chan-nel region and separated from the gallium nitride control layer by another part of the groove, wherein the current collapse suppression structure is applicable to provide, when a voltage of a drain electrode is high, a hole injection to the drain electrode, so that a charge balance on the drain electrode is achieved; a source electrode and the drain electrode that are respec-tively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer, wherein the drain electrode is in contact with a side surface of the current collapse suppression struc-ture and a part of an upper surface of the current collapse suppression structure; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.
The field-effect transistor of claim 1, wherein, in the multi-heterojunction layer, a thickness of the barrier layer is in a range of 1 nm to 50 nm, and a thickness of the channel layer is in a range of 5 nm to 500 nm; a material of the barrier layer is one of AlN, AlGaN, AlInN, or AlInGaN.
The field-effect transistor of claim 1, wherein, the gallium nitride control layer comprises a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked from bottom to top, and the current collapse suppression structure comprises a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked from bottom to top; a thickness of the lightly doped P-type gallium nitride layer is in a range of 3 nm to 150 nm, and a thickness of the heavily doped P-type gallium nitride layer is in a range of 5 nm to 30 nm.
The field-effect transistor of claim 1, wherein, a cross-sectional area of each groove is set as an inverted trapezoid; and an etching angle of a bottom of each groove is set between 90 degrees and 180 degrees; a depth of each groove is in a range of 0.1 µm to 5 µm; and an etching angle of each groove is in a range of degrees to 175 degrees.
The field-effect transistor of claim 1, wherein, a material of the source electrode is an ohmic contact metal, a material of the drain electrode is an ohmic contact metal, and a material of the gate electrode is a schottky contact metal; the ohmic contact metal comprises at least one of Ti, Al, Ni or Au; the schottky contact metal comprises at least one of Pt, Ti, Al, Ni or TiN.
The field-effect transistor of claim 1, further compris-ing: a gate dielectric disposed between the gate electrode and the multi-heterojunction layer, and disposed on the source electrode, the drain electrode, the gallium nitride control layer, the current collapse suppression structure and an exposed multi-heterojunction layer; wherein the gate dielectric comprises one of aluminum oxide, aluminum nitride, silicon oxide or silicon nitride. 13 14
The field-effect transistor of claim 1, further compris-ing: a passivation dielectric layer formed on the gate dielectric and an exposed multi-heterojunction layer; wherein a material of the passivation dielectric layer is at least one of aluminum oxide, aluminum nitride, silicon oxide or silicon nitride.
The field-effect transistor of claim 1, wherein an auxiliary groove which matches with a shape of the groove is formed in the multi-heterojunction layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
folded channel gallium nitride based field-effect transistor
Materials described outside the worked examples.
nitride buffer layer
gallium nitride semi-insulating layer
GaN
channel layer
barrier layer
AlN barrier layer
AlN
AlGaN barrier layer
AlGaN
AlInN barrier layer
AlInN
AlInGaN barrier layer
AlInGaN
ohmic contact metal
schottky contact metal
gate dielectric
passivation dielectric layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 schematically shows a cross-sectional diagram of a folded channel gallium nitride based field-effect transistor according to an embodiment of the present …
FIG. 2 schematically shows a flowchart of a method of manufacturing a folded channel gallium nitride based field- effect transistor according to an embodiment of …
FIGS. 3A to 3K schematically show cross-sectional dia- grams obtained after performing some steps in a method of manufacturing a folded channel gallium nitride …
FIG. 4 schematically shows a cross-sectional diagram of a multi-heterojunction layer of a folded channel gallium nitride based field-effect transistor according …
FIG. 5 schematically shows two cross-sectional diagrams of gate grooves of a folded channel gallium nitride based field-effect transistor according to an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–50 nm | — |
Thickness | 5–500 nm | — |
Thickness | 3–150 nm | — |
Thickness | 5–30 nm | — |
Thickness | 0.1–5 µm | — |
Thickness | 0–20 nm | — |
Thickness | 0–5 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 schematically shows a cross-sectional diagram of a folded channel gallium nitride based field-effect transistor according to an embodiment of the present …
FIG. 2 schematically shows a flowchart of a method of manufacturing a folded channel gallium nitride based field- effect transistor according to an embodiment of …
FIGS. 3A to 3K schematically show cross-sectional dia- grams obtained after performing some steps in a method of manufacturing a folded channel gallium nitride …
FIG. 4 schematically shows a cross-sectional diagram of a multi-heterojunction layer of a folded channel gallium nitride based field-effect transistor according …
FIG. 5 schematically shows two cross-sectional diagrams of gate grooves of a folded channel gallium nitride based field-effect transistor according to an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A folded channel gallium nitride based field-effect transistor, comprising: a base layer, comprising a nitride buffer layer and a gallium nitride semi-insulating layer formed sequen-tially on a substrate from bottom to top, wherein a channel region comprising at least one parallel extended groove is formed on an upper surface of the gallium nitride semi-insulating layer; a multi-heterojunction layer, comprising a channel layer and a barrier layer alternatingly stacked from bottom to top on the gallium nitride semi-insulating layer, wherein a heterojunction is formed between the barrier layer and the channel layer that are adjacent; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove, so as to adjust a charge B₂ balance within the channel region corresponding to on and off states of the field-effect transistor; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the chan-nel region and separated from the gallium nitride control layer by another part of the groove, wherein the current collapse suppression structure is applicable to provide, when a voltage of a drain electrode is high, a hole injection to the drain electrode, so that a charge balance on the drain electrode is achieved; a source electrode and the drain electrode that are respec-tively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer, wherein the drain electrode is in contact with a side surface of the current collapse suppression struc-ture and a part of an upper surface of the current collapse suppression structure; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.
The field-effect transistor of claim 1, wherein, in the multi-heterojunction layer, a thickness of the barrier layer is in a range of 1 nm to 50 nm, and a thickness of the channel layer is in a range of 5 nm to 500 nm; a material of the barrier layer is one of AlN, AlGaN, AlInN, or AlInGaN.
The field-effect transistor of claim 1, wherein, the gallium nitride control layer comprises a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked from bottom to top, and the current collapse suppression structure comprises a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked from bottom to top; a thickness of the lightly doped P-type gallium nitride layer is in a range of 3 nm to 150 nm, and a thickness of the heavily doped P-type gallium nitride layer is in a range of 5 nm to 30 nm.
The field-effect transistor of claim 1, wherein, a cross-sectional area of each groove is set as an inverted trapezoid; and an etching angle of a bottom of each groove is set between 90 degrees and 180 degrees; a depth of each groove is in a range of 0.1 µm to 5 µm; and an etching angle of each groove is in a range of degrees to 175 degrees.
The field-effect transistor of claim 1, wherein, a material of the source electrode is an ohmic contact metal, a material of the drain electrode is an ohmic contact metal, and a material of the gate electrode is a schottky contact metal; the ohmic contact metal comprises at least one of Ti, Al, Ni or Au; the schottky contact metal comprises at least one of Pt, Ti, Al, Ni or TiN.
The field-effect transistor of claim 1, further compris-ing: a gate dielectric disposed between the gate electrode and the multi-heterojunction layer, and disposed on the source electrode, the drain electrode, the gallium nitride control layer, the current collapse suppression structure and an exposed multi-heterojunction layer; wherein the gate dielectric comprises one of aluminum oxide, aluminum nitride, silicon oxide or silicon nitride. 13 14
The field-effect transistor of claim 1, further compris-ing: a passivation dielectric layer formed on the gate dielectric and an exposed multi-heterojunction layer; wherein a material of the passivation dielectric layer is at least one of aluminum oxide, aluminum nitride, silicon oxide or silicon nitride.
The field-effect transistor of claim 1, wherein an auxiliary groove which matches with a shape of the groove is formed in the multi-heterojunction layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
folded channel gallium nitride based field-effect transistor
Materials described outside the worked examples.
nitride buffer layer
gallium nitride semi-insulating layer
GaN
channel layer
barrier layer
AlN barrier layer
AlN
AlGaN barrier layer
AlGaN
AlInN barrier layer
AlInN
AlInGaN barrier layer
AlInGaN
ohmic contact metal
schottky contact metal
gate dielectric
passivation dielectric layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 schematically shows a cross-sectional diagram of a folded channel gallium nitride based field-effect transistor according to an embodiment of the present …
FIG. 2 schematically shows a flowchart of a method of manufacturing a folded channel gallium nitride based field- effect transistor according to an embodiment of …
FIGS. 3A to 3K schematically show cross-sectional dia- grams obtained after performing some steps in a method of manufacturing a folded channel gallium nitride …
FIG. 4 schematically shows a cross-sectional diagram of a multi-heterojunction layer of a folded channel gallium nitride based field-effect transistor according …
FIG. 5 schematically shows two cross-sectional diagrams of gate grooves of a folded channel gallium nitride based field-effect transistor according to an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–50 nm | — |
Thickness | 5–500 nm | — |
Thickness | 3–150 nm | — |
Thickness | 5–30 nm | — |
Thickness | 0.1–5 µm | — |
Thickness | 0–20 nm | — |
Thickness | 0–5 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 schematically shows a cross-sectional diagram of a folded channel gallium nitride based field-effect transistor according to an embodiment of the present …
FIG. 2 schematically shows a flowchart of a method of manufacturing a folded channel gallium nitride based field- effect transistor according to an embodiment of …
FIGS. 3A to 3K schematically show cross-sectional dia- grams obtained after performing some steps in a method of manufacturing a folded channel gallium nitride …
FIG. 4 schematically shows a cross-sectional diagram of a multi-heterojunction layer of a folded channel gallium nitride based field-effect transistor according …
FIG. 5 schematically shows two cross-sectional diagrams of gate grooves of a folded channel gallium nitride based field-effect transistor according to an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A folded channel gallium nitride based field-effect transistor, comprising: a base layer, comprising a nitride buffer layer and a gallium nitride semi-insulating layer formed sequen-tially on a substrate from bottom to top, wherein a channel region comprising at least one parallel extended groove is formed on an upper surface of the gallium nitride semi-insulating layer; a multi-heterojunction layer, comprising a channel layer and a barrier layer alternatingly stacked from bottom to top on the gallium nitride semi-insulating layer, wherein a heterojunction is formed between the barrier layer and the channel layer that are adjacent; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove, so as to adjust a charge B₂ balance within the channel region corresponding to on and off states of the field-effect transistor; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the chan-nel region and separated from the gallium nitride control layer by another part of the groove, wherein the current collapse suppression structure is applicable to provide, when a voltage of a drain electrode is high, a hole injection to the drain electrode, so that a charge balance on the drain electrode is achieved; a source electrode and the drain electrode that are respec-tively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer, wherein the drain electrode is in contact with a side surface of the current collapse suppression struc-ture and a part of an upper surface of the current collapse suppression structure; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.
The field-effect transistor of claim 1, wherein, in the multi-heterojunction layer, a thickness of the barrier layer is in a range of 1 nm to 50 nm, and a thickness of the channel layer is in a range of 5 nm to 500 nm; a material of the barrier layer is one of AlN, AlGaN, AlInN, or AlInGaN.
The field-effect transistor of claim 1, wherein, the gallium nitride control layer comprises a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked from bottom to top, and the current collapse suppression structure comprises a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked from bottom to top; a thickness of the lightly doped P-type gallium nitride layer is in a range of 3 nm to 150 nm, and a thickness of the heavily doped P-type gallium nitride layer is in a range of 5 nm to 30 nm.
The field-effect transistor of claim 1, wherein, a cross-sectional area of each groove is set as an inverted trapezoid; and an etching angle of a bottom of each groove is set between 90 degrees and 180 degrees; a depth of each groove is in a range of 0.1 µm to 5 µm; and an etching angle of each groove is in a range of degrees to 175 degrees.
The field-effect transistor of claim 1, wherein, a material of the source electrode is an ohmic contact metal, a material of the drain electrode is an ohmic contact metal, and a material of the gate electrode is a schottky contact metal; the ohmic contact metal comprises at least one of Ti, Al, Ni or Au; the schottky contact metal comprises at least one of Pt, Ti, Al, Ni or TiN.
The field-effect transistor of claim 1, further compris-ing: a gate dielectric disposed between the gate electrode and the multi-heterojunction layer, and disposed on the source electrode, the drain electrode, the gallium nitride control layer, the current collapse suppression structure and an exposed multi-heterojunction layer; wherein the gate dielectric comprises one of aluminum oxide, aluminum nitride, silicon oxide or silicon nitride. 13 14
The field-effect transistor of claim 1, further compris-ing: a passivation dielectric layer formed on the gate dielectric and an exposed multi-heterojunction layer; wherein a material of the passivation dielectric layer is at least one of aluminum oxide, aluminum nitride, silicon oxide or silicon nitride.
The field-effect transistor of claim 1, wherein an auxiliary groove which matches with a shape of the groove is formed in the multi-heterojunction layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
folded channel gallium nitride based field-effect transistor
Materials described outside the worked examples.
nitride buffer layer
gallium nitride semi-insulating layer
GaN
channel layer
barrier layer
AlN barrier layer
AlN
AlGaN barrier layer
AlGaN
AlInN barrier layer
AlInN
AlInGaN barrier layer
AlInGaN
ohmic contact metal
schottky contact metal
gate dielectric
passivation dielectric layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 schematically shows a cross-sectional diagram of a folded channel gallium nitride based field-effect transistor according to an embodiment of the present …
FIG. 2 schematically shows a flowchart of a method of manufacturing a folded channel gallium nitride based field- effect transistor according to an embodiment of …
FIGS. 3A to 3K schematically show cross-sectional dia- grams obtained after performing some steps in a method of manufacturing a folded channel gallium nitride …
FIG. 4 schematically shows a cross-sectional diagram of a multi-heterojunction layer of a folded channel gallium nitride based field-effect transistor according …
FIG. 5 schematically shows two cross-sectional diagrams of gate grooves of a folded channel gallium nitride based field-effect transistor according to an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–50 nm | — |
Thickness | 5–500 nm | — |
Thickness | 3–150 nm | — |
Thickness | 5–30 nm | — |
Thickness | 0.1–5 µm | — |
Thickness | 0–20 nm | — |
Thickness | 0–5 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 schematically shows a cross-sectional diagram of a folded channel gallium nitride based field-effect transistor according to an embodiment of the present …
FIG. 2 schematically shows a flowchart of a method of manufacturing a folded channel gallium nitride based field- effect transistor according to an embodiment of …
FIGS. 3A to 3K schematically show cross-sectional dia- grams obtained after performing some steps in a method of manufacturing a folded channel gallium nitride …
FIG. 4 schematically shows a cross-sectional diagram of a multi-heterojunction layer of a folded channel gallium nitride based field-effect transistor according …
FIG. 5 schematically shows two cross-sectional diagrams of gate grooves of a folded channel gallium nitride based field-effect transistor according to an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A folded channel gallium nitride based field-effect transistor, comprising: a base layer, comprising a nitride buffer layer and a gallium nitride semi-insulating layer formed sequen-tially on a substrate from bottom to top, wherein a channel region comprising at least one parallel extended groove is formed on an upper surface of the gallium nitride semi-insulating layer; a multi-heterojunction layer, comprising a channel layer and a barrier layer alternatingly stacked from bottom to top on the gallium nitride semi-insulating layer, wherein a heterojunction is formed between the barrier layer and the channel layer that are adjacent; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove, so as to adjust a charge B₂ balance within the channel region corresponding to on and off states of the field-effect transistor; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the chan-nel region and separated from the gallium nitride control layer by another part of the groove, wherein the current collapse suppression structure is applicable to provide, when a voltage of a drain electrode is high, a hole injection to the drain electrode, so that a charge balance on the drain electrode is achieved; a source electrode and the drain electrode that are respec-tively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer, wherein the drain electrode is in contact with a side surface of the current collapse suppression struc-ture and a part of an upper surface of the current collapse suppression structure; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.
The field-effect transistor of claim 1, wherein, in the multi-heterojunction layer, a thickness of the barrier layer is in a range of 1 nm to 50 nm, and a thickness of the channel layer is in a range of 5 nm to 500 nm; a material of the barrier layer is one of AlN, AlGaN, AlInN, or AlInGaN.
The field-effect transistor of claim 1, wherein, the gallium nitride control layer comprises a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked from bottom to top, and the current collapse suppression structure comprises a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked from bottom to top; a thickness of the lightly doped P-type gallium nitride layer is in a range of 3 nm to 150 nm, and a thickness of the heavily doped P-type gallium nitride layer is in a range of 5 nm to 30 nm.
The field-effect transistor of claim 1, wherein, a cross-sectional area of each groove is set as an inverted trapezoid; and an etching angle of a bottom of each groove is set between 90 degrees and 180 degrees; a depth of each groove is in a range of 0.1 µm to 5 µm; and an etching angle of each groove is in a range of degrees to 175 degrees.
The field-effect transistor of claim 1, wherein, a material of the source electrode is an ohmic contact metal, a material of the drain electrode is an ohmic contact metal, and a material of the gate electrode is a schottky contact metal; the ohmic contact metal comprises at least one of Ti, Al, Ni or Au; the schottky contact metal comprises at least one of Pt, Ti, Al, Ni or TiN.
The field-effect transistor of claim 1, further compris-ing: a gate dielectric disposed between the gate electrode and the multi-heterojunction layer, and disposed on the source electrode, the drain electrode, the gallium nitride control layer, the current collapse suppression structure and an exposed multi-heterojunction layer; wherein the gate dielectric comprises one of aluminum oxide, aluminum nitride, silicon oxide or silicon nitride. 13 14
The field-effect transistor of claim 1, further compris-ing: a passivation dielectric layer formed on the gate dielectric and an exposed multi-heterojunction layer; wherein a material of the passivation dielectric layer is at least one of aluminum oxide, aluminum nitride, silicon oxide or silicon nitride.
The field-effect transistor of claim 1, wherein an auxiliary groove which matches with a shape of the groove is formed in the multi-heterojunction layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
folded channel gallium nitride based field-effect transistor
Materials described outside the worked examples.
nitride buffer layer
gallium nitride semi-insulating layer
GaN
channel layer
barrier layer
AlN barrier layer
AlN
AlGaN barrier layer
AlGaN
AlInN barrier layer
AlInN
AlInGaN barrier layer
AlInGaN
ohmic contact metal
schottky contact metal
gate dielectric
passivation dielectric layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 schematically shows a cross-sectional diagram of a folded channel gallium nitride based field-effect transistor according to an embodiment of the present …
FIG. 2 schematically shows a flowchart of a method of manufacturing a folded channel gallium nitride based field- effect transistor according to an embodiment of …
FIGS. 3A to 3K schematically show cross-sectional dia- grams obtained after performing some steps in a method of manufacturing a folded channel gallium nitride …
FIG. 4 schematically shows a cross-sectional diagram of a multi-heterojunction layer of a folded channel gallium nitride based field-effect transistor according …
FIG. 5 schematically shows two cross-sectional diagrams of gate grooves of a folded channel gallium nitride based field-effect transistor according to an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–50 nm | — |
Thickness | 5–500 nm | — |
Thickness | 3–150 nm | — |
Thickness | 5–30 nm | — |
Thickness | 0.1–5 µm | — |
Thickness | 0–20 nm | — |
Thickness | 0–5 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Related documents with shared materials, methods, properties, or citations.
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CMOS CIRCUITS USING N-CHANNEL AND P-CHANNEL GALLIUM NITRIDE TRANSISTORS
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ENHANCEMENT-MODE GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR
