Patent
US 8,912,530ELECTRODE STRUCTURE INCLUDING GRAPHENE AND FIELD EFFECT TRANSISTOR HAVING THE SAME
Hee-jun Yang
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,912,530Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, a graphene 120 is formed on a semiconductor substrate 110, and an electrode metal 130 is formed on the graphene 120. The graphene 120 contacts the …
FIG. 2 is a general energy band diagram illustrating an energy barrier between a metal and a semiconductor; [0031] FI G. 3 is an energy band diagram …
FIG. 3, EF refer s to the Fermi level, E c refers to the conduction band energy, and Ev refers to the valence band energy. [0052] Referring to FI G. 3, the g …
FIG. 4 is a cross-sectional view of a field effect transistor (F ET) according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electrode structure comprising: a graphene layer on a semiconductor layer; and an electrode containing metal directly on the graphene layer, the graphene layer having no band gap, and the graphene layer being between the semiconductor layer and an entire surface of the electrode containing metal facing the semiconductor layer so the electrode containing metal does not directly contact the semiconductor layer.
The electrode structure of claim 1, wherein the semiconductor layer includes one of silicon, germanium, silicon-germanium, a group III -V semiconductor, and a group I I -VI semiconductor.
The electrode structure of claim 1, wherein the graphene layer is one of a single-layered structure and a bi-layered structure.
The electrode structure of claim 1, wherein the electrode containing metal has a size of greater than 0 nm and less than 30 nm. original
The electrode structure of claim 1, wherein the semiconductor layer includes an impurity, the graphene layer is configured to change a Schottky energy barrier between the semiconductor layer and the electrode containing metal, based on the impurity of the semiconductor layer changing a work function of the graphene layer.
The electrode structure of claim 1, wherein a Fermi level of the graphene layer equals a Fermi level of the electrode containing metal.
The electrode structure of claim 1, wherein the electrode containing metal includes one of aluminum, gold, silver, and palladium.
The electrode structure of claim 1, wherein one of a long side and a diameter of the electrode containing metal is greater than 0 nm and less than 30 nm.
The electrode structure of claim 1, wherein a width of the graphene layer is substantially equal to a width of the electrode containing metal.
The electrode structure of claim 1, wherein the graphene layer is directly connected to the semiconductor layer.
. canceled
A field effect transistor (FET) comprising: a semiconductor substrate doped with a first impurity, the semiconductor substrate including a source region and a drain region doped with a second impurity, SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850193.4.1374.142.2285.291.svg 0.497 3.037 Graph Black and white the second impurity having an opposite polarity to a polarity of the first impurity; a first graphene layer and a second graphene layer on the semiconductor substrate and spaced apart from each other, the first graphene layer on the source region and the second graphene layer on the drain region of the substrate; a source electrode containing metal and a drain electrode containing metal that are respectively on the first graphene layer and the second graphene layer, SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850193.15.246.1193.2119.1257.svg 0.213 6.243 Graph Black and white source electrode, the second graphene layer contacting at least one of the substrate and the drain electrode; a gate insulating layer between the source electrode and the drain electrode on the semiconductor layer; and a gate electrode on the gate insulating layer.
The FET of claim 11, wherein the semiconductor substrate includes one of silicon, germanium, silicon-germanium, a group I II -V semiconductor, and a group I I -VI semiconductor.
The FET of claim 11, wherein at least one of the first graphene layer and the second graphene layer is one of a single-layered structure and a bi-layered structure. SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850194.1.81.53.2585.290.svg 0.79 8.347 Graph Black and white
The FET of claim 11, wherein the source electrode and the drain electrode each have a size of greater than 0 nm and less than 30 nm.
The FET of claim 11, wherein the first graphene la y er and the second graphene layer[[s]] contact the semiconductor layer, the source electrode contacts the first graphene layer, and the drain electrode contacts the second graphene layer.
The FET of claim 11, wherein the first graphene layer is configured to change a Schottky energy barrier between the semiconductor substrate and the source electrode.
The F ET of claim 11, wherein the second graphene layer is configured to change a Schottky energy barrier between the semiconductor substrate and the drain electrode.
The FET of claim 11, wherein the first graphene la y er and the second graphene layer [[s]] contact the source and drain electrodes, respectively; and a Fermi level of the first graphene la y er and a Fermi level of the second graphene layer[[s]], respectively, equal[[s]] a Fermi level of the source electrode SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850195.4.1370.139.2281.289.svg 0.5 3.037 Graph Black and white containing metal and a Fermi level of the drain electrode containing metal, respectively.
A contact comprising: a graphene layer sandwiched between a doped-semiconductor structure and an entire surface of an electrode containing metal facing the doped-semiconductor structure, the graphene layer being configured to change a Schottky energy barrier between the doped-semiconductor structure and the electrode containing metal, and the graphene layer having no band gap.
The contact of claim 20, wherein one of a long side and a diameter of the electrode containing metal is greater than 0 nm and less than 30 nm.
The contact of claim 20, wherein a width of the graphene layer is substantially equal to a width of the electrode containing metal. Application No. 13/431,031 Attorney Docket No. 2557S I -001728-US Page 7 of 8
The contact of claim 20, wherein the graphene layer is directly connected to the doped-semiconductor structure. *** END CLAIM LISTING
Layer stacks claimed or described, ordered top of device to substrate.
electrode structure with graphene interlayer
field effect transistor (FET) with graphene source/drain interlayers
Materials described outside the worked examples.
graphene
semiconductor layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, EF refer s to the Fermi level, E c refers to the conduction band energy, and Ev refers to the valence band energy. [0052] Referring to FI G. 3, the g …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–25 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,912,530Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, a graphene 120 is formed on a semiconductor substrate 110, and an electrode metal 130 is formed on the graphene 120. The graphene 120 contacts the …
FIG. 2 is a general energy band diagram illustrating an energy barrier between a metal and a semiconductor; [0031] FI G. 3 is an energy band diagram …
FIG. 3, EF refer s to the Fermi level, E c refers to the conduction band energy, and Ev refers to the valence band energy. [0052] Referring to FI G. 3, the g …
FIG. 4 is a cross-sectional view of a field effect transistor (F ET) according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electrode structure comprising: a graphene layer on a semiconductor layer; and an electrode containing metal directly on the graphene layer, the graphene layer having no band gap, and the graphene layer being between the semiconductor layer and an entire surface of the electrode containing metal facing the semiconductor layer so the electrode containing metal does not directly contact the semiconductor layer.
The electrode structure of claim 1, wherein the semiconductor layer includes one of silicon, germanium, silicon-germanium, a group III -V semiconductor, and a group I I -VI semiconductor.
The electrode structure of claim 1, wherein the graphene layer is one of a single-layered structure and a bi-layered structure.
The electrode structure of claim 1, wherein the electrode containing metal has a size of greater than 0 nm and less than 30 nm. original
The electrode structure of claim 1, wherein the semiconductor layer includes an impurity, the graphene layer is configured to change a Schottky energy barrier between the semiconductor layer and the electrode containing metal, based on the impurity of the semiconductor layer changing a work function of the graphene layer.
The electrode structure of claim 1, wherein a Fermi level of the graphene layer equals a Fermi level of the electrode containing metal.
The electrode structure of claim 1, wherein the electrode containing metal includes one of aluminum, gold, silver, and palladium.
The electrode structure of claim 1, wherein one of a long side and a diameter of the electrode containing metal is greater than 0 nm and less than 30 nm.
The electrode structure of claim 1, wherein a width of the graphene layer is substantially equal to a width of the electrode containing metal.
The electrode structure of claim 1, wherein the graphene layer is directly connected to the semiconductor layer.
. canceled
A field effect transistor (FET) comprising: a semiconductor substrate doped with a first impurity, the semiconductor substrate including a source region and a drain region doped with a second impurity, SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850193.4.1374.142.2285.291.svg 0.497 3.037 Graph Black and white the second impurity having an opposite polarity to a polarity of the first impurity; a first graphene layer and a second graphene layer on the semiconductor substrate and spaced apart from each other, the first graphene layer on the source region and the second graphene layer on the drain region of the substrate; a source electrode containing metal and a drain electrode containing metal that are respectively on the first graphene layer and the second graphene layer, SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850193.15.246.1193.2119.1257.svg 0.213 6.243 Graph Black and white source electrode, the second graphene layer contacting at least one of the substrate and the drain electrode; a gate insulating layer between the source electrode and the drain electrode on the semiconductor layer; and a gate electrode on the gate insulating layer.
The FET of claim 11, wherein the semiconductor substrate includes one of silicon, germanium, silicon-germanium, a group I II -V semiconductor, and a group I I -VI semiconductor.
The FET of claim 11, wherein at least one of the first graphene layer and the second graphene layer is one of a single-layered structure and a bi-layered structure. SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850194.1.81.53.2585.290.svg 0.79 8.347 Graph Black and white
The FET of claim 11, wherein the source electrode and the drain electrode each have a size of greater than 0 nm and less than 30 nm.
The FET of claim 11, wherein the first graphene la y er and the second graphene layer[[s]] contact the semiconductor layer, the source electrode contacts the first graphene layer, and the drain electrode contacts the second graphene layer.
The FET of claim 11, wherein the first graphene layer is configured to change a Schottky energy barrier between the semiconductor substrate and the source electrode.
The F ET of claim 11, wherein the second graphene layer is configured to change a Schottky energy barrier between the semiconductor substrate and the drain electrode.
The FET of claim 11, wherein the first graphene la y er and the second graphene layer [[s]] contact the source and drain electrodes, respectively; and a Fermi level of the first graphene la y er and a Fermi level of the second graphene layer[[s]], respectively, equal[[s]] a Fermi level of the source electrode SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850195.4.1370.139.2281.289.svg 0.5 3.037 Graph Black and white containing metal and a Fermi level of the drain electrode containing metal, respectively.
A contact comprising: a graphene layer sandwiched between a doped-semiconductor structure and an entire surface of an electrode containing metal facing the doped-semiconductor structure, the graphene layer being configured to change a Schottky energy barrier between the doped-semiconductor structure and the electrode containing metal, and the graphene layer having no band gap.
The contact of claim 20, wherein one of a long side and a diameter of the electrode containing metal is greater than 0 nm and less than 30 nm.
The contact of claim 20, wherein a width of the graphene layer is substantially equal to a width of the electrode containing metal. Application No. 13/431,031 Attorney Docket No. 2557S I -001728-US Page 7 of 8
The contact of claim 20, wherein the graphene layer is directly connected to the doped-semiconductor structure. *** END CLAIM LISTING
Layer stacks claimed or described, ordered top of device to substrate.
electrode structure with graphene interlayer
field effect transistor (FET) with graphene source/drain interlayers
Materials described outside the worked examples.
graphene
semiconductor layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, EF refer s to the Fermi level, E c refers to the conduction band energy, and Ev refers to the valence band energy. [0052] Referring to FI G. 3, the g …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–25 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,912,530Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, a graphene 120 is formed on a semiconductor substrate 110, and an electrode metal 130 is formed on the graphene 120. The graphene 120 contacts the …
FIG. 2 is a general energy band diagram illustrating an energy barrier between a metal and a semiconductor; [0031] FI G. 3 is an energy band diagram …
FIG. 3, EF refer s to the Fermi level, E c refers to the conduction band energy, and Ev refers to the valence band energy. [0052] Referring to FI G. 3, the g …
FIG. 4 is a cross-sectional view of a field effect transistor (F ET) according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electrode structure comprising: a graphene layer on a semiconductor layer; and an electrode containing metal directly on the graphene layer, the graphene layer having no band gap, and the graphene layer being between the semiconductor layer and an entire surface of the electrode containing metal facing the semiconductor layer so the electrode containing metal does not directly contact the semiconductor layer.
The electrode structure of claim 1, wherein the semiconductor layer includes one of silicon, germanium, silicon-germanium, a group III -V semiconductor, and a group I I -VI semiconductor.
The electrode structure of claim 1, wherein the graphene layer is one of a single-layered structure and a bi-layered structure.
The electrode structure of claim 1, wherein the electrode containing metal has a size of greater than 0 nm and less than 30 nm. original
The electrode structure of claim 1, wherein the semiconductor layer includes an impurity, the graphene layer is configured to change a Schottky energy barrier between the semiconductor layer and the electrode containing metal, based on the impurity of the semiconductor layer changing a work function of the graphene layer.
The electrode structure of claim 1, wherein a Fermi level of the graphene layer equals a Fermi level of the electrode containing metal.
The electrode structure of claim 1, wherein the electrode containing metal includes one of aluminum, gold, silver, and palladium.
The electrode structure of claim 1, wherein one of a long side and a diameter of the electrode containing metal is greater than 0 nm and less than 30 nm.
The electrode structure of claim 1, wherein a width of the graphene layer is substantially equal to a width of the electrode containing metal.
The electrode structure of claim 1, wherein the graphene layer is directly connected to the semiconductor layer.
. canceled
A field effect transistor (FET) comprising: a semiconductor substrate doped with a first impurity, the semiconductor substrate including a source region and a drain region doped with a second impurity, SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850193.4.1374.142.2285.291.svg 0.497 3.037 Graph Black and white the second impurity having an opposite polarity to a polarity of the first impurity; a first graphene layer and a second graphene layer on the semiconductor substrate and spaced apart from each other, the first graphene layer on the source region and the second graphene layer on the drain region of the substrate; a source electrode containing metal and a drain electrode containing metal that are respectively on the first graphene layer and the second graphene layer, SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850193.15.246.1193.2119.1257.svg 0.213 6.243 Graph Black and white source electrode, the second graphene layer contacting at least one of the substrate and the drain electrode; a gate insulating layer between the source electrode and the drain electrode on the semiconductor layer; and a gate electrode on the gate insulating layer.
The FET of claim 11, wherein the semiconductor substrate includes one of silicon, germanium, silicon-germanium, a group I II -V semiconductor, and a group I I -VI semiconductor.
The FET of claim 11, wherein at least one of the first graphene layer and the second graphene layer is one of a single-layered structure and a bi-layered structure. SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850194.1.81.53.2585.290.svg 0.79 8.347 Graph Black and white
The FET of claim 11, wherein the source electrode and the drain electrode each have a size of greater than 0 nm and less than 30 nm.
The FET of claim 11, wherein the first graphene la y er and the second graphene layer[[s]] contact the semiconductor layer, the source electrode contacts the first graphene layer, and the drain electrode contacts the second graphene layer.
The FET of claim 11, wherein the first graphene layer is configured to change a Schottky energy barrier between the semiconductor substrate and the source electrode.
The F ET of claim 11, wherein the second graphene layer is configured to change a Schottky energy barrier between the semiconductor substrate and the drain electrode.
The FET of claim 11, wherein the first graphene la y er and the second graphene layer [[s]] contact the source and drain electrodes, respectively; and a Fermi level of the first graphene la y er and a Fermi level of the second graphene layer[[s]], respectively, equal[[s]] a Fermi level of the source electrode SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850195.4.1370.139.2281.289.svg 0.5 3.037 Graph Black and white containing metal and a Fermi level of the drain electrode containing metal, respectively.
A contact comprising: a graphene layer sandwiched between a doped-semiconductor structure and an entire surface of an electrode containing metal facing the doped-semiconductor structure, the graphene layer being configured to change a Schottky energy barrier between the doped-semiconductor structure and the electrode containing metal, and the graphene layer having no band gap.
The contact of claim 20, wherein one of a long side and a diameter of the electrode containing metal is greater than 0 nm and less than 30 nm.
The contact of claim 20, wherein a width of the graphene layer is substantially equal to a width of the electrode containing metal. Application No. 13/431,031 Attorney Docket No. 2557S I -001728-US Page 7 of 8
The contact of claim 20, wherein the graphene layer is directly connected to the doped-semiconductor structure. *** END CLAIM LISTING
Layer stacks claimed or described, ordered top of device to substrate.
electrode structure with graphene interlayer
field effect transistor (FET) with graphene source/drain interlayers
Materials described outside the worked examples.
graphene
semiconductor layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, EF refer s to the Fermi level, E c refers to the conduction band energy, and Ev refers to the valence band energy. [0052] Referring to FI G. 3, the g …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–25 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,912,530Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, a graphene 120 is formed on a semiconductor substrate 110, and an electrode metal 130 is formed on the graphene 120. The graphene 120 contacts the …
FIG. 2 is a general energy band diagram illustrating an energy barrier between a metal and a semiconductor; [0031] FI G. 3 is an energy band diagram …
FIG. 3, EF refer s to the Fermi level, E c refers to the conduction band energy, and Ev refers to the valence band energy. [0052] Referring to FI G. 3, the g …
FIG. 4 is a cross-sectional view of a field effect transistor (F ET) according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electrode structure comprising: a graphene layer on a semiconductor layer; and an electrode containing metal directly on the graphene layer, the graphene layer having no band gap, and the graphene layer being between the semiconductor layer and an entire surface of the electrode containing metal facing the semiconductor layer so the electrode containing metal does not directly contact the semiconductor layer.
The electrode structure of claim 1, wherein the semiconductor layer includes one of silicon, germanium, silicon-germanium, a group III -V semiconductor, and a group I I -VI semiconductor.
The electrode structure of claim 1, wherein the graphene layer is one of a single-layered structure and a bi-layered structure.
The electrode structure of claim 1, wherein the electrode containing metal has a size of greater than 0 nm and less than 30 nm. original
The electrode structure of claim 1, wherein the semiconductor layer includes an impurity, the graphene layer is configured to change a Schottky energy barrier between the semiconductor layer and the electrode containing metal, based on the impurity of the semiconductor layer changing a work function of the graphene layer.
The electrode structure of claim 1, wherein a Fermi level of the graphene layer equals a Fermi level of the electrode containing metal.
The electrode structure of claim 1, wherein the electrode containing metal includes one of aluminum, gold, silver, and palladium.
The electrode structure of claim 1, wherein one of a long side and a diameter of the electrode containing metal is greater than 0 nm and less than 30 nm.
The electrode structure of claim 1, wherein a width of the graphene layer is substantially equal to a width of the electrode containing metal.
The electrode structure of claim 1, wherein the graphene layer is directly connected to the semiconductor layer.
. canceled
A field effect transistor (FET) comprising: a semiconductor substrate doped with a first impurity, the semiconductor substrate including a source region and a drain region doped with a second impurity, SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850193.4.1374.142.2285.291.svg 0.497 3.037 Graph Black and white the second impurity having an opposite polarity to a polarity of the first impurity; a first graphene layer and a second graphene layer on the semiconductor substrate and spaced apart from each other, the first graphene layer on the source region and the second graphene layer on the drain region of the substrate; a source electrode containing metal and a drain electrode containing metal that are respectively on the first graphene layer and the second graphene layer, SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850193.15.246.1193.2119.1257.svg 0.213 6.243 Graph Black and white source electrode, the second graphene layer contacting at least one of the substrate and the drain electrode; a gate insulating layer between the source electrode and the drain electrode on the semiconductor layer; and a gate electrode on the gate insulating layer.
The FET of claim 11, wherein the semiconductor substrate includes one of silicon, germanium, silicon-germanium, a group I II -V semiconductor, and a group I I -VI semiconductor.
The FET of claim 11, wherein at least one of the first graphene layer and the second graphene layer is one of a single-layered structure and a bi-layered structure. SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850194.1.81.53.2585.290.svg 0.79 8.347 Graph Black and white
The FET of claim 11, wherein the source electrode and the drain electrode each have a size of greater than 0 nm and less than 30 nm.
The FET of claim 11, wherein the first graphene la y er and the second graphene layer[[s]] contact the semiconductor layer, the source electrode contacts the first graphene layer, and the drain electrode contacts the second graphene layer.
The FET of claim 11, wherein the first graphene layer is configured to change a Schottky energy barrier between the semiconductor substrate and the source electrode.
The F ET of claim 11, wherein the second graphene layer is configured to change a Schottky energy barrier between the semiconductor substrate and the drain electrode.
The FET of claim 11, wherein the first graphene la y er and the second graphene layer [[s]] contact the source and drain electrodes, respectively; and a Fermi level of the first graphene la y er and a Fermi level of the second graphene layer[[s]], respectively, equal[[s]] a Fermi level of the source electrode SVG 13431031.10-17-2014.I₁T₆M₆Z₆PXXIFW4.CLM33850195.4.1370.139.2281.289.svg 0.5 3.037 Graph Black and white containing metal and a Fermi level of the drain electrode containing metal, respectively.
A contact comprising: a graphene layer sandwiched between a doped-semiconductor structure and an entire surface of an electrode containing metal facing the doped-semiconductor structure, the graphene layer being configured to change a Schottky energy barrier between the doped-semiconductor structure and the electrode containing metal, and the graphene layer having no band gap.
The contact of claim 20, wherein one of a long side and a diameter of the electrode containing metal is greater than 0 nm and less than 30 nm.
The contact of claim 20, wherein a width of the graphene layer is substantially equal to a width of the electrode containing metal. Application No. 13/431,031 Attorney Docket No. 2557S I -001728-US Page 7 of 8
The contact of claim 20, wherein the graphene layer is directly connected to the doped-semiconductor structure. *** END CLAIM LISTING
Layer stacks claimed or described, ordered top of device to substrate.
electrode structure with graphene interlayer
field effect transistor (FET) with graphene source/drain interlayers
Materials described outside the worked examples.
graphene
semiconductor layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, EF refer s to the Fermi level, E c refers to the conduction band energy, and Ev refers to the valence band energy. [0052] Referring to FI G. 3, the g …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–25 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
contact with graphene sandwiched between doped semiconductor and metal electrode
silicon, germanium, silicon-germanium, group III-V semiconductor, group II-VI semiconductor
electrode containing metal
aluminum, gold, silver, palladium
gate insulating layer
FIG. 4 is a cross-sectional view of a field effect transistor (F ET) according to example embodiments.
| 10–20 nm |
| — |
Thickness | ≤ 30 nm | — |
Thickness | ≥ 0 nm | — |
contact with graphene sandwiched between doped semiconductor and metal electrode
silicon, germanium, silicon-germanium, group III-V semiconductor, group II-VI semiconductor
electrode containing metal
aluminum, gold, silver, palladium
gate insulating layer
FIG. 4 is a cross-sectional view of a field effect transistor (F ET) according to example embodiments.
| 10–20 nm |
| — |
Thickness | ≤ 30 nm | — |
Thickness | ≥ 0 nm | — |
contact with graphene sandwiched between doped semiconductor and metal electrode
silicon, germanium, silicon-germanium, group III-V semiconductor, group II-VI semiconductor
electrode containing metal
aluminum, gold, silver, palladium
gate insulating layer
FIG. 4 is a cross-sectional view of a field effect transistor (F ET) according to example embodiments.
| 10–20 nm |
| — |
Thickness | ≤ 30 nm | — |
Thickness | ≥ 0 nm | — |
contact with graphene sandwiched between doped semiconductor and metal electrode
silicon, germanium, silicon-germanium, group III-V semiconductor, group II-VI semiconductor
electrode containing metal
aluminum, gold, silver, palladium
gate insulating layer
FIG. 4 is a cross-sectional view of a field effect transistor (F ET) according to example embodiments.
| 10–20 nm |
| — |
Thickness | ≤ 30 nm | — |
Thickness | ≥ 0 nm | — |