Patent
US 8,735,242GRAPHENE-BASED EFUSE DEVICE
Wenjuan Zhu
US
Copyright © 2026 Matter42. All rights reserved.
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US 8,735,242Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A illustrates a semiconductor device 100, according to an exemplary aspect of the present invention;
Figure 1 B illustrates the semiconductor device 100 after a high cu rr ent has been introduced 5 on the graphene layer 150 (e.g., after programming of the device 100), according to an exemplary aspect of the present invention;
Figure 2 illustrates a semiconductor device 200, according to another exemplary aspect of the present invention;
Figure 3 illustrates a method 300 of manufacturing a semiconductor device (e.g., an eFuse 1 0 device), according to an exemplary aspect of the present invention;
Figure 4A illustrates forming of a field-effect transistor (FET) (e.g., a metal oxide semiconductor field-effect transistor (MOSFET)) using a complementary metal oxide semiconductor (CMOS) processing flow, according to an exemplary aspect of the present invention; 1 5
Figure 4B illustrates forming (e.g., depositing) a graphene layer 450 (e.g., a plurality of graphene layers) on a surface (e.g., top surface) of the isolation region 404, and patterning the graphene layer 450, according to an exemplary aspect of the present invention;
Figure 4C illustrates forming an insulating layer 420 on the graphene layer 450 and planarizing the surface of the insulating layer 420 using, for example, chemical-mechanical 20 polishing (CMP), according to an exemplary aspect of the present invention;
Figure 4D illustrates forming a source terminal 414, fuse terminal 416 and drain terminal 412 in the insulating layer 420, according to an exemplary aspect of the present invention;
Figure 5A illustrates forming a field-effect transistor (FET), according to an exemplary aspect of the present invention;
Figure 5B illustrates depositing a graphene layer 550 (e.g., a plurality of graphene layers) on a surface (e.g., top surface) of the first insulating layer 520 (e.g., oxide layer), and patterning the 5 graphene layer 550 by using lithography and oxygen plasma, according to an exemplary aspect of the …
Figure 5C illustrates forming a second insulating film 505 on the insulating layer, and forming source and drain contacts 524, 522 on the source and drain terminals 514, 512, respectively, and on the graphene layer 550, according to an exemplary aspect of the present 1 0 invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a semiconductor device comprising: forming a field-effect transistor (FET) comprising: forming source and drain regions in a substrate; forming source and drain terminals on the source and drain regions, respectively; and forming a channel region between the source and drain regions; and forming a fuse which includes a graphene layer which an d is electrically connected to the source terminal of the FET.
The method of forming a semiconductor device of claim 1, wherein the forming of the fuse comprises forming the fuse in series with the FET.
The method of forming a semiconductor device of claim 1, wherein the forming of the fuse comprises forming the fuse in parallel with the FET.
The method of forming a semiconductor device of claim 1, wherein the graphene layer has a length in a range from 0.0 1 m to 2 p m, a width in a range from 0. 1 m to 20k m and a thickness in a range from 1 atomic layer to 10 atomic layers.
A method of forming a semiconductor device comprising: forming an isolation region in a substrate; forming a well region in the substrate; forming source and drain regions in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric; forming a graphene layer comprising a first end portion on the source region and a second end portion on a surface of the isolation region; forming an insulating film on the graphene layer, gate electrode, source region, drain region and isolation region; forming a fuse terminal on the first end portion of the graphene layer and on the source region; forming a source terminal on the second end portion of the graphene layer; and forming a drain terminal on the drain region.
The method of forming a semiconductor device of claim 16, wherein the source terminal, drain terminal, gate electrode and fuse terminal comprise at least one member selected from the group consisting of polysilicon, titanium, palladium, gold, aluminum, copper and tungsten.
(Cu rr ently amended) A method of forming a semiconductor device comprising: forming a well region in a substrate; forming source and drain regions in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric; forming a first insulating film on the gate electrode, source region and drain region; forming source and drain terminals in the first insulating film and contacting the source and drain regions, respectively; Docket No. Y O R₉₂₀₁₁₀₅₆₇US₁ 6 Serial No. 13/563,673 forming a graphene layer on the first insulating film, the graphene layer including and -inelude s a first end portion which contacts the drain terminal and a second end portion which contacts the source terminal; forming a second insulating film on the graphene layer; forming a drain contact on the first end portion of the graphene layer and contacting the drain terminal; and forming a source contact on the second end portion of the graphene layer and contacting the source terminal.
A method of forming a semiconductor device comprising: forming a field-effect transistor (FET) comprising: forming source and drain regions in a substrate; forming source and drain terminals on the source and drain regions, respectively; and forming a channel region between the source and drain regions; and forming a fuse which includes a graphene layer which and is electrically connected to the source terminal of the FET, the forming of the fuse comprising one of: forming the fuse in series with the FET; and forming the fuse in parallel with the FET.
The method of forming a semiconductor device of claim 19, wherein the forming of the fuse comprises forming the fuse in series with the FET, wherein the forming of the fuse further comprises forming a fuse terminal on an end portion of the graphene layer, and wherein the forming of the FET comprises: forming an isolation region in t he a substrate; forming a well region in the substrate, the;-for ming source and drain regions being formed in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric; forming a silicide layer on the source and drain regions; Docket No. Y O R₉₂₀₁₁₀₅₆₇US₁ 7 Serial No. 13/563,673 forming a pair of spacers on a side of the gate electrode and the gate dielectric layer; forming a pair of extension regions in the well region and adjacent to the source and drain regions; and forming an insulating film on the graphene layer, gate electrode, source region, drain region and isolation region, [[;]] wherein the forming of the a drain terminal comprises forming the drain terminal in the insulating film and contacting the drain region; and wherein the forming of the a source terminal comprises forming the source terminal on an end portion of the graphene layer.
(Cu rr ently amended) The method of forming a semiconductor device of claim 19, wherein the forming of the fuse comprises forming the fuse in parallel with the FET, wherein the forming of the fuse further comprises: forming an insulating film on the graphene layer; forming a drain contact in the insulating film and contacting a first end portion of the graphene layer; and forming a source contact in the insulating film and contacting a second end portion of the graphene layer, and wherein the forming of the FET comprises: forming a well region in the substrate, the;-fefm ing sour c e and drain regions being formed in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric layer; and forming a first insulating film on the gate electrode, source region and drain region,; Docket No. Y O R₉₂₀₁₁₀₅₆₇US₁ 8 Serial No. 13/563,673 wherein the forming of the source and drain terminals co m prises forming the source and drain terminals in the first insulating film and contacting the source and drain regions, respectively.
The method of forming a semiconductor device of claim 19, wherein the graphene layer has a length in a range from 0.0 1 m to 2 p m, a width in a range from 1 atomic layer to 10 atomic layers.
The method of forming a semiconductor device at least one member selected from the group silicon carbide, silicon germanium, germanium, a material in a range from 0. 1 m to 20k m and a thickness of claim 19, wherein the substrate comprises consisting of silicon, silicon-on- insulator (SO I), group I I-VI compound and a group I II -V
Layer stacks claimed or described, ordered top of device to substrate.
FET with series graphene fuse (eFuse)
Materials described outside the worked examples.
graphene layer
gate dielectric
Measurements and analyses referenced in the patent, with their drawing references.
Figure 4A illustrates forming of a field-effect transistor (FET) (e.g., a metal oxide semiconductor field-effect transistor (MOSFET)) using a complementary metal oxide semiconductor (CMOS) processing flow, according to an exemplary aspect of the present invention; 1 5
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene strip length range | 0.01–2 µm | graphene layer |
graphene strip width range | 0.1–20 µm |
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US 8,735,242Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A illustrates a semiconductor device 100, according to an exemplary aspect of the present invention;
Figure 1 B illustrates the semiconductor device 100 after a high cu rr ent has been introduced 5 on the graphene layer 150 (e.g., after programming of the device 100), according to an exemplary aspect of the present invention;
Figure 2 illustrates a semiconductor device 200, according to another exemplary aspect of the present invention;
Figure 3 illustrates a method 300 of manufacturing a semiconductor device (e.g., an eFuse 1 0 device), according to an exemplary aspect of the present invention;
Figure 4A illustrates forming of a field-effect transistor (FET) (e.g., a metal oxide semiconductor field-effect transistor (MOSFET)) using a complementary metal oxide semiconductor (CMOS) processing flow, according to an exemplary aspect of the present invention; 1 5
Figure 4B illustrates forming (e.g., depositing) a graphene layer 450 (e.g., a plurality of graphene layers) on a surface (e.g., top surface) of the isolation region 404, and patterning the graphene layer 450, according to an exemplary aspect of the present invention;
Figure 4C illustrates forming an insulating layer 420 on the graphene layer 450 and planarizing the surface of the insulating layer 420 using, for example, chemical-mechanical 20 polishing (CMP), according to an exemplary aspect of the present invention;
Figure 4D illustrates forming a source terminal 414, fuse terminal 416 and drain terminal 412 in the insulating layer 420, according to an exemplary aspect of the present invention;
Figure 5A illustrates forming a field-effect transistor (FET), according to an exemplary aspect of the present invention;
Figure 5B illustrates depositing a graphene layer 550 (e.g., a plurality of graphene layers) on a surface (e.g., top surface) of the first insulating layer 520 (e.g., oxide layer), and patterning the 5 graphene layer 550 by using lithography and oxygen plasma, according to an exemplary aspect of the …
Figure 5C illustrates forming a second insulating film 505 on the insulating layer, and forming source and drain contacts 524, 522 on the source and drain terminals 514, 512, respectively, and on the graphene layer 550, according to an exemplary aspect of the present 1 0 invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a semiconductor device comprising: forming a field-effect transistor (FET) comprising: forming source and drain regions in a substrate; forming source and drain terminals on the source and drain regions, respectively; and forming a channel region between the source and drain regions; and forming a fuse which includes a graphene layer which an d is electrically connected to the source terminal of the FET.
The method of forming a semiconductor device of claim 1, wherein the forming of the fuse comprises forming the fuse in series with the FET.
The method of forming a semiconductor device of claim 1, wherein the forming of the fuse comprises forming the fuse in parallel with the FET.
The method of forming a semiconductor device of claim 1, wherein the graphene layer has a length in a range from 0.0 1 m to 2 p m, a width in a range from 0. 1 m to 20k m and a thickness in a range from 1 atomic layer to 10 atomic layers.
A method of forming a semiconductor device comprising: forming an isolation region in a substrate; forming a well region in the substrate; forming source and drain regions in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric; forming a graphene layer comprising a first end portion on the source region and a second end portion on a surface of the isolation region; forming an insulating film on the graphene layer, gate electrode, source region, drain region and isolation region; forming a fuse terminal on the first end portion of the graphene layer and on the source region; forming a source terminal on the second end portion of the graphene layer; and forming a drain terminal on the drain region.
The method of forming a semiconductor device of claim 16, wherein the source terminal, drain terminal, gate electrode and fuse terminal comprise at least one member selected from the group consisting of polysilicon, titanium, palladium, gold, aluminum, copper and tungsten.
(Cu rr ently amended) A method of forming a semiconductor device comprising: forming a well region in a substrate; forming source and drain regions in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric; forming a first insulating film on the gate electrode, source region and drain region; forming source and drain terminals in the first insulating film and contacting the source and drain regions, respectively; Docket No. Y O R₉₂₀₁₁₀₅₆₇US₁ 6 Serial No. 13/563,673 forming a graphene layer on the first insulating film, the graphene layer including and -inelude s a first end portion which contacts the drain terminal and a second end portion which contacts the source terminal; forming a second insulating film on the graphene layer; forming a drain contact on the first end portion of the graphene layer and contacting the drain terminal; and forming a source contact on the second end portion of the graphene layer and contacting the source terminal.
A method of forming a semiconductor device comprising: forming a field-effect transistor (FET) comprising: forming source and drain regions in a substrate; forming source and drain terminals on the source and drain regions, respectively; and forming a channel region between the source and drain regions; and forming a fuse which includes a graphene layer which and is electrically connected to the source terminal of the FET, the forming of the fuse comprising one of: forming the fuse in series with the FET; and forming the fuse in parallel with the FET.
The method of forming a semiconductor device of claim 19, wherein the forming of the fuse comprises forming the fuse in series with the FET, wherein the forming of the fuse further comprises forming a fuse terminal on an end portion of the graphene layer, and wherein the forming of the FET comprises: forming an isolation region in t he a substrate; forming a well region in the substrate, the;-for ming source and drain regions being formed in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric; forming a silicide layer on the source and drain regions; Docket No. Y O R₉₂₀₁₁₀₅₆₇US₁ 7 Serial No. 13/563,673 forming a pair of spacers on a side of the gate electrode and the gate dielectric layer; forming a pair of extension regions in the well region and adjacent to the source and drain regions; and forming an insulating film on the graphene layer, gate electrode, source region, drain region and isolation region, [[;]] wherein the forming of the a drain terminal comprises forming the drain terminal in the insulating film and contacting the drain region; and wherein the forming of the a source terminal comprises forming the source terminal on an end portion of the graphene layer.
(Cu rr ently amended) The method of forming a semiconductor device of claim 19, wherein the forming of the fuse comprises forming the fuse in parallel with the FET, wherein the forming of the fuse further comprises: forming an insulating film on the graphene layer; forming a drain contact in the insulating film and contacting a first end portion of the graphene layer; and forming a source contact in the insulating film and contacting a second end portion of the graphene layer, and wherein the forming of the FET comprises: forming a well region in the substrate, the;-fefm ing sour c e and drain regions being formed in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric layer; and forming a first insulating film on the gate electrode, source region and drain region,; Docket No. Y O R₉₂₀₁₁₀₅₆₇US₁ 8 Serial No. 13/563,673 wherein the forming of the source and drain terminals co m prises forming the source and drain terminals in the first insulating film and contacting the source and drain regions, respectively.
The method of forming a semiconductor device of claim 19, wherein the graphene layer has a length in a range from 0.0 1 m to 2 p m, a width in a range from 1 atomic layer to 10 atomic layers.
The method of forming a semiconductor device at least one member selected from the group silicon carbide, silicon germanium, germanium, a material in a range from 0. 1 m to 20k m and a thickness of claim 19, wherein the substrate comprises consisting of silicon, silicon-on- insulator (SO I), group I I-VI compound and a group I II -V
Layer stacks claimed or described, ordered top of device to substrate.
FET with series graphene fuse (eFuse)
Materials described outside the worked examples.
graphene layer
gate dielectric
Measurements and analyses referenced in the patent, with their drawing references.
Figure 4A illustrates forming of a field-effect transistor (FET) (e.g., a metal oxide semiconductor field-effect transistor (MOSFET)) using a complementary metal oxide semiconductor (CMOS) processing flow, according to an exemplary aspect of the present invention; 1 5
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene strip length range | 0.01–2 µm | graphene layer |
graphene strip width range | 0.1–20 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 8,735,242Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A illustrates a semiconductor device 100, according to an exemplary aspect of the present invention;
Figure 1 B illustrates the semiconductor device 100 after a high cu rr ent has been introduced 5 on the graphene layer 150 (e.g., after programming of the device 100), according to an exemplary aspect of the present invention;
Figure 2 illustrates a semiconductor device 200, according to another exemplary aspect of the present invention;
Figure 3 illustrates a method 300 of manufacturing a semiconductor device (e.g., an eFuse 1 0 device), according to an exemplary aspect of the present invention;
Figure 4A illustrates forming of a field-effect transistor (FET) (e.g., a metal oxide semiconductor field-effect transistor (MOSFET)) using a complementary metal oxide semiconductor (CMOS) processing flow, according to an exemplary aspect of the present invention; 1 5
Figure 4B illustrates forming (e.g., depositing) a graphene layer 450 (e.g., a plurality of graphene layers) on a surface (e.g., top surface) of the isolation region 404, and patterning the graphene layer 450, according to an exemplary aspect of the present invention;
Figure 4C illustrates forming an insulating layer 420 on the graphene layer 450 and planarizing the surface of the insulating layer 420 using, for example, chemical-mechanical 20 polishing (CMP), according to an exemplary aspect of the present invention;
Figure 4D illustrates forming a source terminal 414, fuse terminal 416 and drain terminal 412 in the insulating layer 420, according to an exemplary aspect of the present invention;
Figure 5A illustrates forming a field-effect transistor (FET), according to an exemplary aspect of the present invention;
Figure 5B illustrates depositing a graphene layer 550 (e.g., a plurality of graphene layers) on a surface (e.g., top surface) of the first insulating layer 520 (e.g., oxide layer), and patterning the 5 graphene layer 550 by using lithography and oxygen plasma, according to an exemplary aspect of the …
Figure 5C illustrates forming a second insulating film 505 on the insulating layer, and forming source and drain contacts 524, 522 on the source and drain terminals 514, 512, respectively, and on the graphene layer 550, according to an exemplary aspect of the present 1 0 invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a semiconductor device comprising: forming a field-effect transistor (FET) comprising: forming source and drain regions in a substrate; forming source and drain terminals on the source and drain regions, respectively; and forming a channel region between the source and drain regions; and forming a fuse which includes a graphene layer which an d is electrically connected to the source terminal of the FET.
The method of forming a semiconductor device of claim 1, wherein the forming of the fuse comprises forming the fuse in series with the FET.
The method of forming a semiconductor device of claim 1, wherein the forming of the fuse comprises forming the fuse in parallel with the FET.
The method of forming a semiconductor device of claim 1, wherein the graphene layer has a length in a range from 0.0 1 m to 2 p m, a width in a range from 0. 1 m to 20k m and a thickness in a range from 1 atomic layer to 10 atomic layers.
A method of forming a semiconductor device comprising: forming an isolation region in a substrate; forming a well region in the substrate; forming source and drain regions in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric; forming a graphene layer comprising a first end portion on the source region and a second end portion on a surface of the isolation region; forming an insulating film on the graphene layer, gate electrode, source region, drain region and isolation region; forming a fuse terminal on the first end portion of the graphene layer and on the source region; forming a source terminal on the second end portion of the graphene layer; and forming a drain terminal on the drain region.
The method of forming a semiconductor device of claim 16, wherein the source terminal, drain terminal, gate electrode and fuse terminal comprise at least one member selected from the group consisting of polysilicon, titanium, palladium, gold, aluminum, copper and tungsten.
(Cu rr ently amended) A method of forming a semiconductor device comprising: forming a well region in a substrate; forming source and drain regions in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric; forming a first insulating film on the gate electrode, source region and drain region; forming source and drain terminals in the first insulating film and contacting the source and drain regions, respectively; Docket No. Y O R₉₂₀₁₁₀₅₆₇US₁ 6 Serial No. 13/563,673 forming a graphene layer on the first insulating film, the graphene layer including and -inelude s a first end portion which contacts the drain terminal and a second end portion which contacts the source terminal; forming a second insulating film on the graphene layer; forming a drain contact on the first end portion of the graphene layer and contacting the drain terminal; and forming a source contact on the second end portion of the graphene layer and contacting the source terminal.
A method of forming a semiconductor device comprising: forming a field-effect transistor (FET) comprising: forming source and drain regions in a substrate; forming source and drain terminals on the source and drain regions, respectively; and forming a channel region between the source and drain regions; and forming a fuse which includes a graphene layer which and is electrically connected to the source terminal of the FET, the forming of the fuse comprising one of: forming the fuse in series with the FET; and forming the fuse in parallel with the FET.
The method of forming a semiconductor device of claim 19, wherein the forming of the fuse comprises forming the fuse in series with the FET, wherein the forming of the fuse further comprises forming a fuse terminal on an end portion of the graphene layer, and wherein the forming of the FET comprises: forming an isolation region in t he a substrate; forming a well region in the substrate, the;-for ming source and drain regions being formed in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric; forming a silicide layer on the source and drain regions; Docket No. Y O R₉₂₀₁₁₀₅₆₇US₁ 7 Serial No. 13/563,673 forming a pair of spacers on a side of the gate electrode and the gate dielectric layer; forming a pair of extension regions in the well region and adjacent to the source and drain regions; and forming an insulating film on the graphene layer, gate electrode, source region, drain region and isolation region, [[;]] wherein the forming of the a drain terminal comprises forming the drain terminal in the insulating film and contacting the drain region; and wherein the forming of the a source terminal comprises forming the source terminal on an end portion of the graphene layer.
(Cu rr ently amended) The method of forming a semiconductor device of claim 19, wherein the forming of the fuse comprises forming the fuse in parallel with the FET, wherein the forming of the fuse further comprises: forming an insulating film on the graphene layer; forming a drain contact in the insulating film and contacting a first end portion of the graphene layer; and forming a source contact in the insulating film and contacting a second end portion of the graphene layer, and wherein the forming of the FET comprises: forming a well region in the substrate, the;-fefm ing sour c e and drain regions being formed in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric layer; and forming a first insulating film on the gate electrode, source region and drain region,; Docket No. Y O R₉₂₀₁₁₀₅₆₇US₁ 8 Serial No. 13/563,673 wherein the forming of the source and drain terminals co m prises forming the source and drain terminals in the first insulating film and contacting the source and drain regions, respectively.
The method of forming a semiconductor device of claim 19, wherein the graphene layer has a length in a range from 0.0 1 m to 2 p m, a width in a range from 1 atomic layer to 10 atomic layers.
The method of forming a semiconductor device at least one member selected from the group silicon carbide, silicon germanium, germanium, a material in a range from 0. 1 m to 20k m and a thickness of claim 19, wherein the substrate comprises consisting of silicon, silicon-on- insulator (SO I), group I I-VI compound and a group I II -V
Layer stacks claimed or described, ordered top of device to substrate.
FET with series graphene fuse (eFuse)
Materials described outside the worked examples.
graphene layer
gate dielectric
Measurements and analyses referenced in the patent, with their drawing references.
Figure 4A illustrates forming of a field-effect transistor (FET) (e.g., a metal oxide semiconductor field-effect transistor (MOSFET)) using a complementary metal oxide semiconductor (CMOS) processing flow, according to an exemplary aspect of the present invention; 1 5
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene strip length range | 0.01–2 µm | graphene layer |
graphene strip width range | 0.1–20 µm |
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Patent
Atlas literature
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US 8,735,242Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A illustrates a semiconductor device 100, according to an exemplary aspect of the present invention;
Figure 1 B illustrates the semiconductor device 100 after a high cu rr ent has been introduced 5 on the graphene layer 150 (e.g., after programming of the device 100), according to an exemplary aspect of the present invention;
Figure 2 illustrates a semiconductor device 200, according to another exemplary aspect of the present invention;
Figure 3 illustrates a method 300 of manufacturing a semiconductor device (e.g., an eFuse 1 0 device), according to an exemplary aspect of the present invention;
Figure 4A illustrates forming of a field-effect transistor (FET) (e.g., a metal oxide semiconductor field-effect transistor (MOSFET)) using a complementary metal oxide semiconductor (CMOS) processing flow, according to an exemplary aspect of the present invention; 1 5
Figure 4B illustrates forming (e.g., depositing) a graphene layer 450 (e.g., a plurality of graphene layers) on a surface (e.g., top surface) of the isolation region 404, and patterning the graphene layer 450, according to an exemplary aspect of the present invention;
Figure 4C illustrates forming an insulating layer 420 on the graphene layer 450 and planarizing the surface of the insulating layer 420 using, for example, chemical-mechanical 20 polishing (CMP), according to an exemplary aspect of the present invention;
Figure 4D illustrates forming a source terminal 414, fuse terminal 416 and drain terminal 412 in the insulating layer 420, according to an exemplary aspect of the present invention;
Figure 5A illustrates forming a field-effect transistor (FET), according to an exemplary aspect of the present invention;
Figure 5B illustrates depositing a graphene layer 550 (e.g., a plurality of graphene layers) on a surface (e.g., top surface) of the first insulating layer 520 (e.g., oxide layer), and patterning the 5 graphene layer 550 by using lithography and oxygen plasma, according to an exemplary aspect of the …
Figure 5C illustrates forming a second insulating film 505 on the insulating layer, and forming source and drain contacts 524, 522 on the source and drain terminals 514, 512, respectively, and on the graphene layer 550, according to an exemplary aspect of the present 1 0 invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a semiconductor device comprising: forming a field-effect transistor (FET) comprising: forming source and drain regions in a substrate; forming source and drain terminals on the source and drain regions, respectively; and forming a channel region between the source and drain regions; and forming a fuse which includes a graphene layer which an d is electrically connected to the source terminal of the FET.
The method of forming a semiconductor device of claim 1, wherein the forming of the fuse comprises forming the fuse in series with the FET.
The method of forming a semiconductor device of claim 1, wherein the forming of the fuse comprises forming the fuse in parallel with the FET.
The method of forming a semiconductor device of claim 1, wherein the graphene layer has a length in a range from 0.0 1 m to 2 p m, a width in a range from 0. 1 m to 20k m and a thickness in a range from 1 atomic layer to 10 atomic layers.
A method of forming a semiconductor device comprising: forming an isolation region in a substrate; forming a well region in the substrate; forming source and drain regions in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric; forming a graphene layer comprising a first end portion on the source region and a second end portion on a surface of the isolation region; forming an insulating film on the graphene layer, gate electrode, source region, drain region and isolation region; forming a fuse terminal on the first end portion of the graphene layer and on the source region; forming a source terminal on the second end portion of the graphene layer; and forming a drain terminal on the drain region.
The method of forming a semiconductor device of claim 16, wherein the source terminal, drain terminal, gate electrode and fuse terminal comprise at least one member selected from the group consisting of polysilicon, titanium, palladium, gold, aluminum, copper and tungsten.
(Cu rr ently amended) A method of forming a semiconductor device comprising: forming a well region in a substrate; forming source and drain regions in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric; forming a first insulating film on the gate electrode, source region and drain region; forming source and drain terminals in the first insulating film and contacting the source and drain regions, respectively; Docket No. Y O R₉₂₀₁₁₀₅₆₇US₁ 6 Serial No. 13/563,673 forming a graphene layer on the first insulating film, the graphene layer including and -inelude s a first end portion which contacts the drain terminal and a second end portion which contacts the source terminal; forming a second insulating film on the graphene layer; forming a drain contact on the first end portion of the graphene layer and contacting the drain terminal; and forming a source contact on the second end portion of the graphene layer and contacting the source terminal.
A method of forming a semiconductor device comprising: forming a field-effect transistor (FET) comprising: forming source and drain regions in a substrate; forming source and drain terminals on the source and drain regions, respectively; and forming a channel region between the source and drain regions; and forming a fuse which includes a graphene layer which and is electrically connected to the source terminal of the FET, the forming of the fuse comprising one of: forming the fuse in series with the FET; and forming the fuse in parallel with the FET.
The method of forming a semiconductor device of claim 19, wherein the forming of the fuse comprises forming the fuse in series with the FET, wherein the forming of the fuse further comprises forming a fuse terminal on an end portion of the graphene layer, and wherein the forming of the FET comprises: forming an isolation region in t he a substrate; forming a well region in the substrate, the;-for ming source and drain regions being formed in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric; forming a silicide layer on the source and drain regions; Docket No. Y O R₉₂₀₁₁₀₅₆₇US₁ 7 Serial No. 13/563,673 forming a pair of spacers on a side of the gate electrode and the gate dielectric layer; forming a pair of extension regions in the well region and adjacent to the source and drain regions; and forming an insulating film on the graphene layer, gate electrode, source region, drain region and isolation region, [[;]] wherein the forming of the a drain terminal comprises forming the drain terminal in the insulating film and contacting the drain region; and wherein the forming of the a source terminal comprises forming the source terminal on an end portion of the graphene layer.
(Cu rr ently amended) The method of forming a semiconductor device of claim 19, wherein the forming of the fuse comprises forming the fuse in parallel with the FET, wherein the forming of the fuse further comprises: forming an insulating film on the graphene layer; forming a drain contact in the insulating film and contacting a first end portion of the graphene layer; and forming a source contact in the insulating film and contacting a second end portion of the graphene layer, and wherein the forming of the FET comprises: forming a well region in the substrate, the;-fefm ing sour c e and drain regions being formed in the well region; forming a gate dielectric layer on the well region; forming a gate electrode on the gate dielectric layer; and forming a first insulating film on the gate electrode, source region and drain region,; Docket No. Y O R₉₂₀₁₁₀₅₆₇US₁ 8 Serial No. 13/563,673 wherein the forming of the source and drain terminals co m prises forming the source and drain terminals in the first insulating film and contacting the source and drain regions, respectively.
The method of forming a semiconductor device of claim 19, wherein the graphene layer has a length in a range from 0.0 1 m to 2 p m, a width in a range from 1 atomic layer to 10 atomic layers.
The method of forming a semiconductor device at least one member selected from the group silicon carbide, silicon germanium, germanium, a material in a range from 0. 1 m to 20k m and a thickness of claim 19, wherein the substrate comprises consisting of silicon, silicon-on- insulator (SO I), group I I-VI compound and a group I II -V
Layer stacks claimed or described, ordered top of device to substrate.
FET with series graphene fuse (eFuse)
Materials described outside the worked examples.
graphene layer
gate dielectric
Measurements and analyses referenced in the patent, with their drawing references.
Figure 4A illustrates forming of a field-effect transistor (FET) (e.g., a metal oxide semiconductor field-effect transistor (MOSFET)) using a complementary metal oxide semiconductor (CMOS) processing flow, according to an exemplary aspect of the present invention; 1 5
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene strip length range | 0.01–2 µm | graphene layer |
graphene strip width range | 0.1–20 µm |
Related documents with shared materials, methods, properties, or citations.
FET with parallel graphene fuse (eFuse)
silicide layer
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Figure 5A illustrates forming a field-effect transistor (FET), according to an exemplary aspect of the present invention;
graphene strip thickness range | 1–10 atomic layers | graphene layer |
programming voltage for graphene blow (length > 2 µm) | ≥ 5 V | graphene layer |
programming voltage target for effective blow (length < 2 µm) | ≤ 5 V | graphene layer |
FET with parallel graphene fuse (eFuse)
silicide layer
substrate material
terminal/electrode material
Figure 5A illustrates forming a field-effect transistor (FET), according to an exemplary aspect of the present invention;
graphene strip thickness range | 1–10 atomic layers | graphene layer |
programming voltage for graphene blow (length > 2 µm) | ≥ 5 V | graphene layer |
programming voltage target for effective blow (length < 2 µm) | ≤ 5 V | graphene layer |
FET with parallel graphene fuse (eFuse)
silicide layer
substrate material
terminal/electrode material
Figure 5A illustrates forming a field-effect transistor (FET), according to an exemplary aspect of the present invention;
graphene strip thickness range | 1–10 atomic layers | graphene layer |
programming voltage for graphene blow (length > 2 µm) | ≥ 5 V | graphene layer |
programming voltage target for effective blow (length < 2 µm) | ≤ 5 V | graphene layer |
FET with parallel graphene fuse (eFuse)
silicide layer
substrate material
terminal/electrode material
Figure 5A illustrates forming a field-effect transistor (FET), according to an exemplary aspect of the present invention;
graphene strip thickness range | 1–10 atomic layers | graphene layer |
programming voltage for graphene blow (length > 2 µm) | ≥ 5 V | graphene layer |
programming voltage target for effective blow (length < 2 µm) | ≤ 5 V | graphene layer |