Patent
US 8,368,053MULTILAYER-INTERCONNECTION FIRST INTEGRATION SCHEME FOR GRAPHENE AND CARBON NANOTUBE TRANSISTOR BASED INTEGRATION
Zihong Liu
US
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Patent
Atlas literature
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US 8,368,053Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Specifically, cross-sectional area can be quantified as the product of the cross-sectional width and the cross-sectional height. Thus, in this example, …
FIG. 2 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a first layer v 1 of vias …
FIG. 3 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a second metal interconnect …
FIG. 4 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a second layer of vias v2 …
FIG. 5 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating both a bottom-gated carbon …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating an integrated circuit, comprising the steps of: providing a substrate; forming a plurality of interconnect layers on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack; and forming at least one transistor on a top-most layer of the stack.
The method of claim 1, wherein the metal lines in the given interconnect layer have a cross-sectional area that is greater than a cross-sectional area of the metal lines in the interconnect layers, if any, that are present above the given interconnect layer in the stack and wherein the cross-sectional area of the metal lines in the given interconnect layer is less than a cross-sectional area of the metal lines in the interconnect layers, if any, that are present below the given interconnect layer in the stack.
The method of claim 1, further comprising the step of: forming a layer of conductive vias between each interconnect layer in the stack.
The method of claim 1, wherein the substrate comprises glass, metal, plastic, a semiconductor material or a bulk silicon substrate.
The method of claim 1, wherein the step of forming the transistor comprises the steps of: forming a bottom gate on the stack; depositing a gate dielectric material over the bottom gate; YO R₉₂₀₁₀₀₄₁₅US₁ 13 forming a carbon-based material on the gate dielectric material which serves as a channel of the transistor; and forming source and drain regions in contact with the carbon-based material.
The method of claim 1, wherein the step of forming the transistor comprises the steps o f: forming a carbon-based material on the stack which serves as a channel of the transistor; depositing a gate dielectric material over the carbon-based material; forming a top gate separated from the carbon-based material by the gate dielectric material; and forming source and drain regions in contact with the carbon-based material.
An integrated circuit, comprising: a substrate; a plurality of interconnect layers on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack; and YO R₉₂₀₁₀₀₄₁₅US₁ 14 at least one transistor on a top-most layer of the stack.
The integrated circuit of claim 11, wherein the substrate comprises glass, metal, plastic, a semiconductor material or a bulk silicon substrate.
The integrated circuit of claim 11, wherein the transistor comprises: a bottom gate on the stack; a gate dielectric material disposed over the bottom gate; a carbon-based material on the gate dielectric material which serves as a channel of the transistor; and source and drain regions in contact with the carbon-based material.
The integrated circuit of claim 11, wherein the transistor comprises: a carbon-based material on the stack which serves as a channel of the transistor; a gate dielectric material over the carbon-based material; a top gate separated from the carbon-based material by the gate dielectric; and source and drain regions in contact with the carbon-based material.
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit with tapered interconnect stack
bottom-gated carbon-material transistor on interconnect stack
Materials described outside the worked examples.
substrate material
carbon-based material
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. Specifically, cross-sectional area can be quantified as the product of the cross-sectional width and the cross-sectional height. Thus, in this example, …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,368,053Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Specifically, cross-sectional area can be quantified as the product of the cross-sectional width and the cross-sectional height. Thus, in this example, …
FIG. 2 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a first layer v 1 of vias …
FIG. 3 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a second metal interconnect …
FIG. 4 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a second layer of vias v2 …
FIG. 5 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating both a bottom-gated carbon …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating an integrated circuit, comprising the steps of: providing a substrate; forming a plurality of interconnect layers on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack; and forming at least one transistor on a top-most layer of the stack.
The method of claim 1, wherein the metal lines in the given interconnect layer have a cross-sectional area that is greater than a cross-sectional area of the metal lines in the interconnect layers, if any, that are present above the given interconnect layer in the stack and wherein the cross-sectional area of the metal lines in the given interconnect layer is less than a cross-sectional area of the metal lines in the interconnect layers, if any, that are present below the given interconnect layer in the stack.
The method of claim 1, further comprising the step of: forming a layer of conductive vias between each interconnect layer in the stack.
The method of claim 1, wherein the substrate comprises glass, metal, plastic, a semiconductor material or a bulk silicon substrate.
The method of claim 1, wherein the step of forming the transistor comprises the steps of: forming a bottom gate on the stack; depositing a gate dielectric material over the bottom gate; YO R₉₂₀₁₀₀₄₁₅US₁ 13 forming a carbon-based material on the gate dielectric material which serves as a channel of the transistor; and forming source and drain regions in contact with the carbon-based material.
The method of claim 1, wherein the step of forming the transistor comprises the steps o f: forming a carbon-based material on the stack which serves as a channel of the transistor; depositing a gate dielectric material over the carbon-based material; forming a top gate separated from the carbon-based material by the gate dielectric material; and forming source and drain regions in contact with the carbon-based material.
An integrated circuit, comprising: a substrate; a plurality of interconnect layers on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack; and YO R₉₂₀₁₀₀₄₁₅US₁ 14 at least one transistor on a top-most layer of the stack.
The integrated circuit of claim 11, wherein the substrate comprises glass, metal, plastic, a semiconductor material or a bulk silicon substrate.
The integrated circuit of claim 11, wherein the transistor comprises: a bottom gate on the stack; a gate dielectric material disposed over the bottom gate; a carbon-based material on the gate dielectric material which serves as a channel of the transistor; and source and drain regions in contact with the carbon-based material.
The integrated circuit of claim 11, wherein the transistor comprises: a carbon-based material on the stack which serves as a channel of the transistor; a gate dielectric material over the carbon-based material; a top gate separated from the carbon-based material by the gate dielectric; and source and drain regions in contact with the carbon-based material.
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit with tapered interconnect stack
bottom-gated carbon-material transistor on interconnect stack
Materials described outside the worked examples.
substrate material
carbon-based material
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. Specifically, cross-sectional area can be quantified as the product of the cross-sectional width and the cross-sectional height. Thus, in this example, …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,368,053Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Specifically, cross-sectional area can be quantified as the product of the cross-sectional width and the cross-sectional height. Thus, in this example, …
FIG. 2 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a first layer v 1 of vias …
FIG. 3 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a second metal interconnect …
FIG. 4 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a second layer of vias v2 …
FIG. 5 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating both a bottom-gated carbon …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating an integrated circuit, comprising the steps of: providing a substrate; forming a plurality of interconnect layers on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack; and forming at least one transistor on a top-most layer of the stack.
The method of claim 1, wherein the metal lines in the given interconnect layer have a cross-sectional area that is greater than a cross-sectional area of the metal lines in the interconnect layers, if any, that are present above the given interconnect layer in the stack and wherein the cross-sectional area of the metal lines in the given interconnect layer is less than a cross-sectional area of the metal lines in the interconnect layers, if any, that are present below the given interconnect layer in the stack.
The method of claim 1, further comprising the step of: forming a layer of conductive vias between each interconnect layer in the stack.
The method of claim 1, wherein the substrate comprises glass, metal, plastic, a semiconductor material or a bulk silicon substrate.
The method of claim 1, wherein the step of forming the transistor comprises the steps of: forming a bottom gate on the stack; depositing a gate dielectric material over the bottom gate; YO R₉₂₀₁₀₀₄₁₅US₁ 13 forming a carbon-based material on the gate dielectric material which serves as a channel of the transistor; and forming source and drain regions in contact with the carbon-based material.
The method of claim 1, wherein the step of forming the transistor comprises the steps o f: forming a carbon-based material on the stack which serves as a channel of the transistor; depositing a gate dielectric material over the carbon-based material; forming a top gate separated from the carbon-based material by the gate dielectric material; and forming source and drain regions in contact with the carbon-based material.
An integrated circuit, comprising: a substrate; a plurality of interconnect layers on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack; and YO R₉₂₀₁₀₀₄₁₅US₁ 14 at least one transistor on a top-most layer of the stack.
The integrated circuit of claim 11, wherein the substrate comprises glass, metal, plastic, a semiconductor material or a bulk silicon substrate.
The integrated circuit of claim 11, wherein the transistor comprises: a bottom gate on the stack; a gate dielectric material disposed over the bottom gate; a carbon-based material on the gate dielectric material which serves as a channel of the transistor; and source and drain regions in contact with the carbon-based material.
The integrated circuit of claim 11, wherein the transistor comprises: a carbon-based material on the stack which serves as a channel of the transistor; a gate dielectric material over the carbon-based material; a top gate separated from the carbon-based material by the gate dielectric; and source and drain regions in contact with the carbon-based material.
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit with tapered interconnect stack
bottom-gated carbon-material transistor on interconnect stack
Materials described outside the worked examples.
substrate material
carbon-based material
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. Specifically, cross-sectional area can be quantified as the product of the cross-sectional width and the cross-sectional height. Thus, in this example, …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,368,053Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Specifically, cross-sectional area can be quantified as the product of the cross-sectional width and the cross-sectional height. Thus, in this example, …
FIG. 2 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a first layer v 1 of vias …
FIG. 3 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a second metal interconnect …
FIG. 4 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a second layer of vias v2 …
FIG. 5 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating both a bottom-gated carbon …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating an integrated circuit, comprising the steps of: providing a substrate; forming a plurality of interconnect layers on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack; and forming at least one transistor on a top-most layer of the stack.
The method of claim 1, wherein the metal lines in the given interconnect layer have a cross-sectional area that is greater than a cross-sectional area of the metal lines in the interconnect layers, if any, that are present above the given interconnect layer in the stack and wherein the cross-sectional area of the metal lines in the given interconnect layer is less than a cross-sectional area of the metal lines in the interconnect layers, if any, that are present below the given interconnect layer in the stack.
The method of claim 1, further comprising the step of: forming a layer of conductive vias between each interconnect layer in the stack.
The method of claim 1, wherein the substrate comprises glass, metal, plastic, a semiconductor material or a bulk silicon substrate.
The method of claim 1, wherein the step of forming the transistor comprises the steps of: forming a bottom gate on the stack; depositing a gate dielectric material over the bottom gate; YO R₉₂₀₁₀₀₄₁₅US₁ 13 forming a carbon-based material on the gate dielectric material which serves as a channel of the transistor; and forming source and drain regions in contact with the carbon-based material.
The method of claim 1, wherein the step of forming the transistor comprises the steps o f: forming a carbon-based material on the stack which serves as a channel of the transistor; depositing a gate dielectric material over the carbon-based material; forming a top gate separated from the carbon-based material by the gate dielectric material; and forming source and drain regions in contact with the carbon-based material.
An integrated circuit, comprising: a substrate; a plurality of interconnect layers on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack; and YO R₉₂₀₁₀₀₄₁₅US₁ 14 at least one transistor on a top-most layer of the stack.
The integrated circuit of claim 11, wherein the substrate comprises glass, metal, plastic, a semiconductor material or a bulk silicon substrate.
The integrated circuit of claim 11, wherein the transistor comprises: a bottom gate on the stack; a gate dielectric material disposed over the bottom gate; a carbon-based material on the gate dielectric material which serves as a channel of the transistor; and source and drain regions in contact with the carbon-based material.
The integrated circuit of claim 11, wherein the transistor comprises: a carbon-based material on the stack which serves as a channel of the transistor; a gate dielectric material over the carbon-based material; a top gate separated from the carbon-based material by the gate dielectric; and source and drain regions in contact with the carbon-based material.
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit with tapered interconnect stack
bottom-gated carbon-material transistor on interconnect stack
Materials described outside the worked examples.
substrate material
carbon-based material
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. Specifically, cross-sectional area can be quantified as the product of the cross-sectional width and the cross-sectional height. Thus, in this example, …
Related documents with shared materials, methods, properties, or citations.
top-gated carbon-material transistor on interconnect stack
graphene
carbon nanotubes
copper
Cu
silicon dioxide
SiO₂
FIG. 4 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a second layer of vias v2 …
FIG. 5 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating both a bottom-gated carbon …
top-gated carbon-material transistor on interconnect stack
graphene
carbon nanotubes
copper
Cu
silicon dioxide
SiO₂
FIG. 4 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a second layer of vias v2 …
FIG. 5 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating both a bottom-gated carbon …
top-gated carbon-material transistor on interconnect stack
graphene
carbon nanotubes
copper
Cu
silicon dioxide
SiO₂
FIG. 4 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a second layer of vias v2 …
FIG. 5 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating both a bottom-gated carbon …
top-gated carbon-material transistor on interconnect stack
graphene
carbon nanotubes
copper
Cu
silicon dioxide
SiO₂
FIG. 4 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating a second layer of vias v2 …
FIG. 5 is a diagram showing a cross-sectional cut through a three-dimensional representation of the integrated circuit illustrating both a bottom-gated carbon …