Patent
US 9,337,273GRAPHENE-BASED SEMICONDUCTOR DEVICE
Amirhasan Nourbakhsh
IMEC·US
Copyright © 2026 Matter42. All rights reserved.
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US 9,337,273Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
FIG. 2, for the preparation of a f ield-effect transistor (3) using 10 an e lectrically insulating layer (5), the same procedure as described in Example 1 is …
FIG. 3 (circles, line n ° 3), the deprotonation procedure shifted the 20 neutrality point towards negative values. In order to achieve p-doping (triangles, …
FIG. 4 shows the transfer characteristics of BLG-FET (Length/W idth = 2) at room temperature. Back-gate dielectric stack consists of Si * wafer/300 nm SiO2. 10 …
FIG. 5 shows the total density of states (DOS) for F₄-TCN Q -SLG with the projection of the DOS (PDOS) onto SLG and F₄-TCN Q components in 3 eV vicinity of the …
FIG. 6, the potential (V) in the inter-layer space is flat which means that no electric field (E) is set up in this region, while the hybrid configuration shows a …
FIG. 7 compares the band structure of pristine trilayer graphene (TLG) (left) with trilayer graphene comprising a native oxide layer (right). The pristine TLG …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a bilayer graphene comprising a first graphene layer adjacent to and in contact with a second graphene layer; a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising: a first electrically insulating material, and a first dopant providing either n-type doping or p-type doping substance configured to create free charge carriers of a first type in the first graphene layer, wherein the first dopant is dispersed within in the first electrically insulating material; and an electrically insulating region contacting the second graphene layer, the electrically insulating region comprising: a second electrically insulating material, and a second substance configured to create free charge carriers dopant providing, in the second g raphene layer, doping of a second type[[,]] opposite to the first in the second graphene layer type of doping provided by the first dopant.
The semiconductor device of Claim 1, wherein the first electrically insulating material is a homogeneous film.
The semiconductor device of Claim 1, wherein the first electrically insulating material is bound to the first substance dopant.
The semiconductor device of Claim 1, further comprising a first electrode coupled to the first electrically insulating layer and a second electrode coupled to the electrically insulating region. -2- Application No.: 13/853572 Filing Date:
The semiconductor device of Claim 1, wherein the first electrically insulating material is chemically inert toward graphene.
The semiconductor device of Claim 1, wherein the first electrically insulating layer is a graphene oxide layer.
The semiconductor device of Claim 1, wherein the electrically insulating region has a relative permittivity of at least 3.9.
The semiconductor device of Claim 1, wherein the electrically insulating region comprises a second electrically insulating layer bound to a dopant layer, wherein the dopant layer is configured to create the free charge carriers of the second type in the second graphene layer.
The semiconductor device of Claim 1, wherein the first do p ant creates electrons as free charge carriers of the first type are electrons and the second do p ant creates holes as free charge carriers of the second type are holes.
The semiconductor device of Claim 1, wherein the first electrically insulating material has a relative permittivity of at least 2.3.
The semiconductor device of Claim 1, wherein the first electrically insulating material has a relative permittivity of at least 10.
The semiconductor device of Claim 1, wherein the first substance dopant comprises from 1 wt. % to 10 wt. % of the first electrically insulating layer.
The semiconductor device of Claim 1, further comprising a source electrode, a drain electrode and a channel between the source electrode and the drain electrode, wherein the channel is the bilayer graphene, and wherein the semiconductor device is a field effect transistor.
The semiconductor device of Claim 1, wherein the first electrically insulating material is a matrix within which the first substance is dispersed and wherein the first substance dopant is F 4-TCNQ. -3- Application No.: 13/853572 Filing Date:
A method for manufacturing a semiconductor device, comprising: providing an electrically insulating region, wherein the electrically insulating region comprises a second electrically insulating material [[,]] and a second substance dopant configured to create free charge carriers of a second type, opposite to a first type, in a second graphene layer; depositing a bilayer graphene above the electrically insulating region, the bilayer graphene comprising a first graphene layer and a second graphene layer; and depositing an electrically insulating layer on the bilayer graphene, the electrically insulating layer comprising a first electrically insulating material and a first substance dopant dispersed in the first electrically insulating material, wherein the first dopant provides either n-type doping or p-type doping configured to create free charge carriers of the first type in the first graphene layer, and wherein the second dopant provides, in the second graphene layer, doping of a type opposite to the type of doping provided by the first dopant, whereby the semiconductor device of Claim 1 is obtained.
canceled
canceled
2 1-26. canceled
Layer stacks claimed or described, ordered top of device to substrate.
bilayer graphene semiconductor device
bilayer graphene field effect transistor
Materials described outside the worked examples.
bilayer graphene
first electrically insulating material
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,337,273Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
FIG. 2, for the preparation of a f ield-effect transistor (3) using 10 an e lectrically insulating layer (5), the same procedure as described in Example 1 is …
FIG. 3 (circles, line n ° 3), the deprotonation procedure shifted the 20 neutrality point towards negative values. In order to achieve p-doping (triangles, …
FIG. 4 shows the transfer characteristics of BLG-FET (Length/W idth = 2) at room temperature. Back-gate dielectric stack consists of Si * wafer/300 nm SiO2. 10 …
FIG. 5 shows the total density of states (DOS) for F₄-TCN Q -SLG with the projection of the DOS (PDOS) onto SLG and F₄-TCN Q components in 3 eV vicinity of the …
FIG. 6, the potential (V) in the inter-layer space is flat which means that no electric field (E) is set up in this region, while the hybrid configuration shows a …
FIG. 7 compares the band structure of pristine trilayer graphene (TLG) (left) with trilayer graphene comprising a native oxide layer (right). The pristine TLG …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a bilayer graphene comprising a first graphene layer adjacent to and in contact with a second graphene layer; a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising: a first electrically insulating material, and a first dopant providing either n-type doping or p-type doping substance configured to create free charge carriers of a first type in the first graphene layer, wherein the first dopant is dispersed within in the first electrically insulating material; and an electrically insulating region contacting the second graphene layer, the electrically insulating region comprising: a second electrically insulating material, and a second substance configured to create free charge carriers dopant providing, in the second g raphene layer, doping of a second type[[,]] opposite to the first in the second graphene layer type of doping provided by the first dopant.
The semiconductor device of Claim 1, wherein the first electrically insulating material is a homogeneous film.
The semiconductor device of Claim 1, wherein the first electrically insulating material is bound to the first substance dopant.
The semiconductor device of Claim 1, further comprising a first electrode coupled to the first electrically insulating layer and a second electrode coupled to the electrically insulating region. -2- Application No.: 13/853572 Filing Date:
The semiconductor device of Claim 1, wherein the first electrically insulating material is chemically inert toward graphene.
The semiconductor device of Claim 1, wherein the first electrically insulating layer is a graphene oxide layer.
The semiconductor device of Claim 1, wherein the electrically insulating region has a relative permittivity of at least 3.9.
The semiconductor device of Claim 1, wherein the electrically insulating region comprises a second electrically insulating layer bound to a dopant layer, wherein the dopant layer is configured to create the free charge carriers of the second type in the second graphene layer.
The semiconductor device of Claim 1, wherein the first do p ant creates electrons as free charge carriers of the first type are electrons and the second do p ant creates holes as free charge carriers of the second type are holes.
The semiconductor device of Claim 1, wherein the first electrically insulating material has a relative permittivity of at least 2.3.
The semiconductor device of Claim 1, wherein the first electrically insulating material has a relative permittivity of at least 10.
The semiconductor device of Claim 1, wherein the first substance dopant comprises from 1 wt. % to 10 wt. % of the first electrically insulating layer.
The semiconductor device of Claim 1, further comprising a source electrode, a drain electrode and a channel between the source electrode and the drain electrode, wherein the channel is the bilayer graphene, and wherein the semiconductor device is a field effect transistor.
The semiconductor device of Claim 1, wherein the first electrically insulating material is a matrix within which the first substance is dispersed and wherein the first substance dopant is F 4-TCNQ. -3- Application No.: 13/853572 Filing Date:
A method for manufacturing a semiconductor device, comprising: providing an electrically insulating region, wherein the electrically insulating region comprises a second electrically insulating material [[,]] and a second substance dopant configured to create free charge carriers of a second type, opposite to a first type, in a second graphene layer; depositing a bilayer graphene above the electrically insulating region, the bilayer graphene comprising a first graphene layer and a second graphene layer; and depositing an electrically insulating layer on the bilayer graphene, the electrically insulating layer comprising a first electrically insulating material and a first substance dopant dispersed in the first electrically insulating material, wherein the first dopant provides either n-type doping or p-type doping configured to create free charge carriers of the first type in the first graphene layer, and wherein the second dopant provides, in the second graphene layer, doping of a type opposite to the type of doping provided by the first dopant, whereby the semiconductor device of Claim 1 is obtained.
canceled
canceled
2 1-26. canceled
Layer stacks claimed or described, ordered top of device to substrate.
bilayer graphene semiconductor device
bilayer graphene field effect transistor
Materials described outside the worked examples.
bilayer graphene
first electrically insulating material
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,337,273Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
FIG. 2, for the preparation of a f ield-effect transistor (3) using 10 an e lectrically insulating layer (5), the same procedure as described in Example 1 is …
FIG. 3 (circles, line n ° 3), the deprotonation procedure shifted the 20 neutrality point towards negative values. In order to achieve p-doping (triangles, …
FIG. 4 shows the transfer characteristics of BLG-FET (Length/W idth = 2) at room temperature. Back-gate dielectric stack consists of Si * wafer/300 nm SiO2. 10 …
FIG. 5 shows the total density of states (DOS) for F₄-TCN Q -SLG with the projection of the DOS (PDOS) onto SLG and F₄-TCN Q components in 3 eV vicinity of the …
FIG. 6, the potential (V) in the inter-layer space is flat which means that no electric field (E) is set up in this region, while the hybrid configuration shows a …
FIG. 7 compares the band structure of pristine trilayer graphene (TLG) (left) with trilayer graphene comprising a native oxide layer (right). The pristine TLG …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a bilayer graphene comprising a first graphene layer adjacent to and in contact with a second graphene layer; a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising: a first electrically insulating material, and a first dopant providing either n-type doping or p-type doping substance configured to create free charge carriers of a first type in the first graphene layer, wherein the first dopant is dispersed within in the first electrically insulating material; and an electrically insulating region contacting the second graphene layer, the electrically insulating region comprising: a second electrically insulating material, and a second substance configured to create free charge carriers dopant providing, in the second g raphene layer, doping of a second type[[,]] opposite to the first in the second graphene layer type of doping provided by the first dopant.
The semiconductor device of Claim 1, wherein the first electrically insulating material is a homogeneous film.
The semiconductor device of Claim 1, wherein the first electrically insulating material is bound to the first substance dopant.
The semiconductor device of Claim 1, further comprising a first electrode coupled to the first electrically insulating layer and a second electrode coupled to the electrically insulating region. -2- Application No.: 13/853572 Filing Date:
The semiconductor device of Claim 1, wherein the first electrically insulating material is chemically inert toward graphene.
The semiconductor device of Claim 1, wherein the first electrically insulating layer is a graphene oxide layer.
The semiconductor device of Claim 1, wherein the electrically insulating region has a relative permittivity of at least 3.9.
The semiconductor device of Claim 1, wherein the electrically insulating region comprises a second electrically insulating layer bound to a dopant layer, wherein the dopant layer is configured to create the free charge carriers of the second type in the second graphene layer.
The semiconductor device of Claim 1, wherein the first do p ant creates electrons as free charge carriers of the first type are electrons and the second do p ant creates holes as free charge carriers of the second type are holes.
The semiconductor device of Claim 1, wherein the first electrically insulating material has a relative permittivity of at least 2.3.
The semiconductor device of Claim 1, wherein the first electrically insulating material has a relative permittivity of at least 10.
The semiconductor device of Claim 1, wherein the first substance dopant comprises from 1 wt. % to 10 wt. % of the first electrically insulating layer.
The semiconductor device of Claim 1, further comprising a source electrode, a drain electrode and a channel between the source electrode and the drain electrode, wherein the channel is the bilayer graphene, and wherein the semiconductor device is a field effect transistor.
The semiconductor device of Claim 1, wherein the first electrically insulating material is a matrix within which the first substance is dispersed and wherein the first substance dopant is F 4-TCNQ. -3- Application No.: 13/853572 Filing Date:
A method for manufacturing a semiconductor device, comprising: providing an electrically insulating region, wherein the electrically insulating region comprises a second electrically insulating material [[,]] and a second substance dopant configured to create free charge carriers of a second type, opposite to a first type, in a second graphene layer; depositing a bilayer graphene above the electrically insulating region, the bilayer graphene comprising a first graphene layer and a second graphene layer; and depositing an electrically insulating layer on the bilayer graphene, the electrically insulating layer comprising a first electrically insulating material and a first substance dopant dispersed in the first electrically insulating material, wherein the first dopant provides either n-type doping or p-type doping configured to create free charge carriers of the first type in the first graphene layer, and wherein the second dopant provides, in the second graphene layer, doping of a type opposite to the type of doping provided by the first dopant, whereby the semiconductor device of Claim 1 is obtained.
canceled
canceled
2 1-26. canceled
Layer stacks claimed or described, ordered top of device to substrate.
bilayer graphene semiconductor device
bilayer graphene field effect transistor
Materials described outside the worked examples.
bilayer graphene
first electrically insulating material
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,337,273Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
FIG. 2, for the preparation of a f ield-effect transistor (3) using 10 an e lectrically insulating layer (5), the same procedure as described in Example 1 is …
FIG. 3 (circles, line n ° 3), the deprotonation procedure shifted the 20 neutrality point towards negative values. In order to achieve p-doping (triangles, …
FIG. 4 shows the transfer characteristics of BLG-FET (Length/W idth = 2) at room temperature. Back-gate dielectric stack consists of Si * wafer/300 nm SiO2. 10 …
FIG. 5 shows the total density of states (DOS) for F₄-TCN Q -SLG with the projection of the DOS (PDOS) onto SLG and F₄-TCN Q components in 3 eV vicinity of the …
FIG. 6, the potential (V) in the inter-layer space is flat which means that no electric field (E) is set up in this region, while the hybrid configuration shows a …
FIG. 7 compares the band structure of pristine trilayer graphene (TLG) (left) with trilayer graphene comprising a native oxide layer (right). The pristine TLG …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a bilayer graphene comprising a first graphene layer adjacent to and in contact with a second graphene layer; a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising: a first electrically insulating material, and a first dopant providing either n-type doping or p-type doping substance configured to create free charge carriers of a first type in the first graphene layer, wherein the first dopant is dispersed within in the first electrically insulating material; and an electrically insulating region contacting the second graphene layer, the electrically insulating region comprising: a second electrically insulating material, and a second substance configured to create free charge carriers dopant providing, in the second g raphene layer, doping of a second type[[,]] opposite to the first in the second graphene layer type of doping provided by the first dopant.
The semiconductor device of Claim 1, wherein the first electrically insulating material is a homogeneous film.
The semiconductor device of Claim 1, wherein the first electrically insulating material is bound to the first substance dopant.
The semiconductor device of Claim 1, further comprising a first electrode coupled to the first electrically insulating layer and a second electrode coupled to the electrically insulating region. -2- Application No.: 13/853572 Filing Date:
The semiconductor device of Claim 1, wherein the first electrically insulating material is chemically inert toward graphene.
The semiconductor device of Claim 1, wherein the first electrically insulating layer is a graphene oxide layer.
The semiconductor device of Claim 1, wherein the electrically insulating region has a relative permittivity of at least 3.9.
The semiconductor device of Claim 1, wherein the electrically insulating region comprises a second electrically insulating layer bound to a dopant layer, wherein the dopant layer is configured to create the free charge carriers of the second type in the second graphene layer.
The semiconductor device of Claim 1, wherein the first do p ant creates electrons as free charge carriers of the first type are electrons and the second do p ant creates holes as free charge carriers of the second type are holes.
The semiconductor device of Claim 1, wherein the first electrically insulating material has a relative permittivity of at least 2.3.
The semiconductor device of Claim 1, wherein the first electrically insulating material has a relative permittivity of at least 10.
The semiconductor device of Claim 1, wherein the first substance dopant comprises from 1 wt. % to 10 wt. % of the first electrically insulating layer.
The semiconductor device of Claim 1, further comprising a source electrode, a drain electrode and a channel between the source electrode and the drain electrode, wherein the channel is the bilayer graphene, and wherein the semiconductor device is a field effect transistor.
The semiconductor device of Claim 1, wherein the first electrically insulating material is a matrix within which the first substance is dispersed and wherein the first substance dopant is F 4-TCNQ. -3- Application No.: 13/853572 Filing Date:
A method for manufacturing a semiconductor device, comprising: providing an electrically insulating region, wherein the electrically insulating region comprises a second electrically insulating material [[,]] and a second substance dopant configured to create free charge carriers of a second type, opposite to a first type, in a second graphene layer; depositing a bilayer graphene above the electrically insulating region, the bilayer graphene comprising a first graphene layer and a second graphene layer; and depositing an electrically insulating layer on the bilayer graphene, the electrically insulating layer comprising a first electrically insulating material and a first substance dopant dispersed in the first electrically insulating material, wherein the first dopant provides either n-type doping or p-type doping configured to create free charge carriers of the first type in the first graphene layer, and wherein the second dopant provides, in the second graphene layer, doping of a type opposite to the type of doping provided by the first dopant, whereby the semiconductor device of Claim 1 is obtained.
canceled
canceled
2 1-26. canceled
Layer stacks claimed or described, ordered top of device to substrate.
bilayer graphene semiconductor device
bilayer graphene field effect transistor
Materials described outside the worked examples.
bilayer graphene
first electrically insulating material
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
Related documents with shared materials, methods, properties, or citations.
first dopant
second electrically insulating material
polymer
fluoropolymer
graphene oxide
dopant layer
second dopant
F₄-TCNQ
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
FIG. 2, for the preparation of a f ield-effect transistor (3) using 10 an e lectrically insulating layer (5), the same procedure as described in Example 1 is …
FIG. 3 (circles, line n ° 3), the deprotonation procedure shifted the 20 neutrality point towards negative values. In order to achieve p-doping (triangles, …
FIG. 4 shows the transfer characteristics of BLG-FET (Length/W idth = 2) at room temperature. Back-gate dielectric stack consists of Si * wafer/300 nm SiO2. 10 …
FIG. 5 shows the total density of states (DOS) for F₄-TCN Q -SLG with the projection of the DOS (PDOS) onto SLG and F₄-TCN Q components in 3 eV vicinity of the …
FIG. 7 compares the band structure of pristine trilayer graphene (TLG) (left) with trilayer graphene comprising a native oxide layer (right). The pristine TLG …
first dopant
second electrically insulating material
polymer
fluoropolymer
graphene oxide
dopant layer
second dopant
F₄-TCNQ
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
FIG. 2, for the preparation of a f ield-effect transistor (3) using 10 an e lectrically insulating layer (5), the same procedure as described in Example 1 is …
FIG. 3 (circles, line n ° 3), the deprotonation procedure shifted the 20 neutrality point towards negative values. In order to achieve p-doping (triangles, …
FIG. 4 shows the transfer characteristics of BLG-FET (Length/W idth = 2) at room temperature. Back-gate dielectric stack consists of Si * wafer/300 nm SiO2. 10 …
FIG. 5 shows the total density of states (DOS) for F₄-TCN Q -SLG with the projection of the DOS (PDOS) onto SLG and F₄-TCN Q components in 3 eV vicinity of the …
FIG. 7 compares the band structure of pristine trilayer graphene (TLG) (left) with trilayer graphene comprising a native oxide layer (right). The pristine TLG …
first dopant
second electrically insulating material
polymer
fluoropolymer
graphene oxide
dopant layer
second dopant
F₄-TCNQ
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
FIG. 2, for the preparation of a f ield-effect transistor (3) using 10 an e lectrically insulating layer (5), the same procedure as described in Example 1 is …
FIG. 3 (circles, line n ° 3), the deprotonation procedure shifted the 20 neutrality point towards negative values. In order to achieve p-doping (triangles, …
FIG. 4 shows the transfer characteristics of BLG-FET (Length/W idth = 2) at room temperature. Back-gate dielectric stack consists of Si * wafer/300 nm SiO2. 10 …
FIG. 5 shows the total density of states (DOS) for F₄-TCN Q -SLG with the projection of the DOS (PDOS) onto SLG and F₄-TCN Q components in 3 eV vicinity of the …
FIG. 7 compares the band structure of pristine trilayer graphene (TLG) (left) with trilayer graphene comprising a native oxide layer (right). The pristine TLG …
first dopant
second electrically insulating material
polymer
fluoropolymer
graphene oxide
dopant layer
second dopant
F₄-TCNQ
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
FIG. 1 (b) (right). BLG then becomes a semiconductor with a bandgap that depends on the strength of the applied electric field. The maximum value of the bandgap …
FIG. 2, for the preparation of a f ield-effect transistor (3) using 10 an e lectrically insulating layer (5), the same procedure as described in Example 1 is …
FIG. 3 (circles, line n ° 3), the deprotonation procedure shifted the 20 neutrality point towards negative values. In order to achieve p-doping (triangles, …
FIG. 4 shows the transfer characteristics of BLG-FET (Length/W idth = 2) at room temperature. Back-gate dielectric stack consists of Si * wafer/300 nm SiO2. 10 …
FIG. 5 shows the total density of states (DOS) for F₄-TCN Q -SLG with the projection of the DOS (PDOS) onto SLG and F₄-TCN Q components in 3 eV vicinity of the …
FIG. 7 compares the band structure of pristine trilayer graphene (TLG) (left) with trilayer graphene comprising a native oxide layer (right). The pristine TLG …