Patent
US 9,299,789MEMORY DEVICES INCLUDING GRAPHENE SWITCHING DEVICES
David SEO
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,299,789Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic circuit diagram of a memory array including graphene switching devices according to an example embodiment; [0022]
FIG. 2 is a schematic cross-sectional view of a graphene switching device according to an example embodiment; [0023]
FIGS. 3A through 3D are energy band diagrams for explaining example functionality of the graphene switching device of
FIG. 4 is an example current-voltage (1 -V) characteristic curve for an n-type graphene switching device according to an example embodiment; [0025]
FIG. 5 is an example I -V characteristic curve for a p-type graphene switching device according to an example embodiment; [0026]
FIG. 6 is a graph showing example drain current characteristics for an example embodiment of the graphene switching device of
FIG. 7 is a graph showing example drain current characteristics depending on application of a programming voltage; [0028]
FIG. 8 is a circuit diagram illustrating an example read operation; [0029]
FIG. 9 is a schematic cross-sectional view of a graphene switching device according to another example embodiment; [0030]
FIG. 10 is a diagram for explaining example functionality of the graphene switching device of
FIG. 11 is a schematic cross-sectional view of another example embodiment of a graphene switching device; and [0032]
FIG. 12 is a schematic cross-sectional view of yet another example embodiment of a graphene switching device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A memory device comprising: a graphene switching device having a source electrode, a drain electrode, and a gate electrode, and the graphene switching device including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode, wherein the graphene switching device further includes a conductive semiconductor substrate, wherein the drain electrode is on a first region of the conductive semiconductor substrate, and an insulating layer is on a second region of the conductive semiconductor substrate, the first and second regions being spaced apart from each other; a semimetal layer on the conductive semiconductor substrate between the drain electrode and the insulating layer, the semi-metal layer extending onto the insulating layer, the semi-metal layer being a conductive layer, and the semi-metal layer being configured to function as the channel, wherein the source electrode is on the semi-metal layer; and a gate oxide layer on the semi-metal layer, wherein the gate electrode is on the gate oxide layer, and the conductive semiconductor substrate forms the Schottky barrier between the semi-metal layer and the drain electrode: Page 2 Application No. 13/943,006 Attorney Docket No. 2557 SI -001965-US the insulating layer is between the semi-metal layer and the conductive semiconductor substrate, and the insulating layer is entirely above the surface of the conductive semiconductor substrate.
The memory device of claim 1, further comprising: a plurality of graphene switching devices arranged in a plurality of rows and a plurality of columns, each of the plurality of graphene switching devices having a source electrode, a drain electrode, and a gate electrode, and each of the plurality of graphene switching devices including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode.
The memory device of claim 1, wherein the substrate includes at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), a Group I II -V semiconductor, a Group I I -VI semiconductor, semiconductor Page 3 Application No. 13/943,006 Attorney Docket No. 2557 SI -001965-US carbon nanotube (CNT), molybdenum sulfide (MoS₂), indium zinc oxide (IZO), and gallium indium zin c oxide (GIZO).
The memory device of claim 1, wherein the drain electrode is spaced apart from the semimetal layer.
The memory device of claim 1, wherein the semi- metal layer is a graphene layer or a metal carbon nanotube (CNT) mesh.
The memory device of claim 1, wherein the drain electrode and the source electrode are formed of a metal or polysilicon (poly-Si).
The memory device of claim 1, wherein a height of the Schottky barrier varies according to a voltage applied to the gate electrode.
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A memory device comprising: a graphene switching device having a source electrode, a drain electrode, and a gate electrode, and the graphene switching device including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode, the graphene switching device further including Page 4 Application No. 13/943,006 Attorney Docket No. 2557S I -001965-US a conductive semiconductor substrate, wherein the drain electrode is on a first region of the substrate, and an insulating layer is on a second region of the substrate; a plurality of metal bumps on the substrate between the first region and the second region; a semi-metal layer on the plurality of metal bumps and extending onto the insulating layer, wherein the source electrode is on the semi-metal layer in the second region; and a gate oxide layer on the semi-metal layer, wherein the gate electrode on the gate oxide layer, and the substrate forms the Schottky barrier between the semi-metal layer and the drain electrode.
The memory device of claim 12, further comprising: a plurality of grooves on a surface of the substrate, the plurality of grooves corresponding to the plurality of metal bumps; and an insulating material filling the plurality of grooves.
The memory device of claim 12, wherein the plurality of metal bumps have a size of about 1 nm to about 10 nm.
The memory device of claim 12, wherein the plurality of metal bumps are arranged at intervals of about 10 nm to about 30 nm.
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A memory device comprising: a graphene switching device having a source electrode, a drain electrode, and a gate electrode, and the graphene switching device including a Schott k y barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode, wherein the graphene switching device further includes a conductive semiconductor substrate, wherein Page 6 Application No. 13/943,006 Attorney Docket No. 2557SI- 00 1965-US the drain electrode is on a first region of the conductive semiconductor substrate, and an insulating layer is on a second region of the conductive semiconductor substrate, the first and second regions being spaced apart from each other; a semi-metal layer on the conductive semiconductor substrate between the drain electrode and the insulating layer, the semi-metal layer extending onto the insulating layer such that a first portion of the semi-metal layer is on a surface of the conductive semiconductor substrate and a second portion of the semimetal layer is on a surface of the insulating layer, the semi-metal layer being a conductive layer, and the semi-metal layer being configured to electrode is on the semi-metal layer; and a gate gate electrode is on the gate oxide layer, the Schottky barrier between the semi-metal layer and the second portion of the semi-metal layer on the surface of the first portion of the semi-metal layer substrate. Page 7 function as the channel, wherein the source oxide layer on the semi-metal layer, wherein the conductive semiconductor substrate forms the drain electrode, and a bottom surface of insulating layer is raised relative to a bottom on the surface of the conductive semiconductor
Layer stacks claimed or described, ordered top of device to substrate.
graphene switching device (memory device, claim 1 embodiment)
graphene switching device with metal bumps (claim 12 embodiment)
Materials described outside the worked examples.
graphene
conductive semiconductor substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic cross-sectional view of a graphene switching device according to an example embodiment; [0023]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–30 nm | — |
Thickness | 1–10 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,299,789Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic circuit diagram of a memory array including graphene switching devices according to an example embodiment; [0022]
FIG. 2 is a schematic cross-sectional view of a graphene switching device according to an example embodiment; [0023]
FIGS. 3A through 3D are energy band diagrams for explaining example functionality of the graphene switching device of
FIG. 4 is an example current-voltage (1 -V) characteristic curve for an n-type graphene switching device according to an example embodiment; [0025]
FIG. 5 is an example I -V characteristic curve for a p-type graphene switching device according to an example embodiment; [0026]
FIG. 6 is a graph showing example drain current characteristics for an example embodiment of the graphene switching device of
FIG. 7 is a graph showing example drain current characteristics depending on application of a programming voltage; [0028]
FIG. 8 is a circuit diagram illustrating an example read operation; [0029]
FIG. 9 is a schematic cross-sectional view of a graphene switching device according to another example embodiment; [0030]
FIG. 10 is a diagram for explaining example functionality of the graphene switching device of
FIG. 11 is a schematic cross-sectional view of another example embodiment of a graphene switching device; and [0032]
FIG. 12 is a schematic cross-sectional view of yet another example embodiment of a graphene switching device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A memory device comprising: a graphene switching device having a source electrode, a drain electrode, and a gate electrode, and the graphene switching device including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode, wherein the graphene switching device further includes a conductive semiconductor substrate, wherein the drain electrode is on a first region of the conductive semiconductor substrate, and an insulating layer is on a second region of the conductive semiconductor substrate, the first and second regions being spaced apart from each other; a semimetal layer on the conductive semiconductor substrate between the drain electrode and the insulating layer, the semi-metal layer extending onto the insulating layer, the semi-metal layer being a conductive layer, and the semi-metal layer being configured to function as the channel, wherein the source electrode is on the semi-metal layer; and a gate oxide layer on the semi-metal layer, wherein the gate electrode is on the gate oxide layer, and the conductive semiconductor substrate forms the Schottky barrier between the semi-metal layer and the drain electrode: Page 2 Application No. 13/943,006 Attorney Docket No. 2557 SI -001965-US the insulating layer is between the semi-metal layer and the conductive semiconductor substrate, and the insulating layer is entirely above the surface of the conductive semiconductor substrate.
The memory device of claim 1, further comprising: a plurality of graphene switching devices arranged in a plurality of rows and a plurality of columns, each of the plurality of graphene switching devices having a source electrode, a drain electrode, and a gate electrode, and each of the plurality of graphene switching devices including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode.
The memory device of claim 1, wherein the substrate includes at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), a Group I II -V semiconductor, a Group I I -VI semiconductor, semiconductor Page 3 Application No. 13/943,006 Attorney Docket No. 2557 SI -001965-US carbon nanotube (CNT), molybdenum sulfide (MoS₂), indium zinc oxide (IZO), and gallium indium zin c oxide (GIZO).
The memory device of claim 1, wherein the drain electrode is spaced apart from the semimetal layer.
The memory device of claim 1, wherein the semi- metal layer is a graphene layer or a metal carbon nanotube (CNT) mesh.
The memory device of claim 1, wherein the drain electrode and the source electrode are formed of a metal or polysilicon (poly-Si).
The memory device of claim 1, wherein a height of the Schottky barrier varies according to a voltage applied to the gate electrode.
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A memory device comprising: a graphene switching device having a source electrode, a drain electrode, and a gate electrode, and the graphene switching device including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode, the graphene switching device further including Page 4 Application No. 13/943,006 Attorney Docket No. 2557S I -001965-US a conductive semiconductor substrate, wherein the drain electrode is on a first region of the substrate, and an insulating layer is on a second region of the substrate; a plurality of metal bumps on the substrate between the first region and the second region; a semi-metal layer on the plurality of metal bumps and extending onto the insulating layer, wherein the source electrode is on the semi-metal layer in the second region; and a gate oxide layer on the semi-metal layer, wherein the gate electrode on the gate oxide layer, and the substrate forms the Schottky barrier between the semi-metal layer and the drain electrode.
The memory device of claim 12, further comprising: a plurality of grooves on a surface of the substrate, the plurality of grooves corresponding to the plurality of metal bumps; and an insulating material filling the plurality of grooves.
The memory device of claim 12, wherein the plurality of metal bumps have a size of about 1 nm to about 10 nm.
The memory device of claim 12, wherein the plurality of metal bumps are arranged at intervals of about 10 nm to about 30 nm.
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A memory device comprising: a graphene switching device having a source electrode, a drain electrode, and a gate electrode, and the graphene switching device including a Schott k y barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode, wherein the graphene switching device further includes a conductive semiconductor substrate, wherein Page 6 Application No. 13/943,006 Attorney Docket No. 2557SI- 00 1965-US the drain electrode is on a first region of the conductive semiconductor substrate, and an insulating layer is on a second region of the conductive semiconductor substrate, the first and second regions being spaced apart from each other; a semi-metal layer on the conductive semiconductor substrate between the drain electrode and the insulating layer, the semi-metal layer extending onto the insulating layer such that a first portion of the semi-metal layer is on a surface of the conductive semiconductor substrate and a second portion of the semimetal layer is on a surface of the insulating layer, the semi-metal layer being a conductive layer, and the semi-metal layer being configured to electrode is on the semi-metal layer; and a gate gate electrode is on the gate oxide layer, the Schottky barrier between the semi-metal layer and the second portion of the semi-metal layer on the surface of the first portion of the semi-metal layer substrate. Page 7 function as the channel, wherein the source oxide layer on the semi-metal layer, wherein the conductive semiconductor substrate forms the drain electrode, and a bottom surface of insulating layer is raised relative to a bottom on the surface of the conductive semiconductor
Layer stacks claimed or described, ordered top of device to substrate.
graphene switching device (memory device, claim 1 embodiment)
graphene switching device with metal bumps (claim 12 embodiment)
Materials described outside the worked examples.
graphene
conductive semiconductor substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic cross-sectional view of a graphene switching device according to an example embodiment; [0023]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–30 nm | — |
Thickness | 1–10 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,299,789Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic circuit diagram of a memory array including graphene switching devices according to an example embodiment; [0022]
FIG. 2 is a schematic cross-sectional view of a graphene switching device according to an example embodiment; [0023]
FIGS. 3A through 3D are energy band diagrams for explaining example functionality of the graphene switching device of
FIG. 4 is an example current-voltage (1 -V) characteristic curve for an n-type graphene switching device according to an example embodiment; [0025]
FIG. 5 is an example I -V characteristic curve for a p-type graphene switching device according to an example embodiment; [0026]
FIG. 6 is a graph showing example drain current characteristics for an example embodiment of the graphene switching device of
FIG. 7 is a graph showing example drain current characteristics depending on application of a programming voltage; [0028]
FIG. 8 is a circuit diagram illustrating an example read operation; [0029]
FIG. 9 is a schematic cross-sectional view of a graphene switching device according to another example embodiment; [0030]
FIG. 10 is a diagram for explaining example functionality of the graphene switching device of
FIG. 11 is a schematic cross-sectional view of another example embodiment of a graphene switching device; and [0032]
FIG. 12 is a schematic cross-sectional view of yet another example embodiment of a graphene switching device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A memory device comprising: a graphene switching device having a source electrode, a drain electrode, and a gate electrode, and the graphene switching device including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode, wherein the graphene switching device further includes a conductive semiconductor substrate, wherein the drain electrode is on a first region of the conductive semiconductor substrate, and an insulating layer is on a second region of the conductive semiconductor substrate, the first and second regions being spaced apart from each other; a semimetal layer on the conductive semiconductor substrate between the drain electrode and the insulating layer, the semi-metal layer extending onto the insulating layer, the semi-metal layer being a conductive layer, and the semi-metal layer being configured to function as the channel, wherein the source electrode is on the semi-metal layer; and a gate oxide layer on the semi-metal layer, wherein the gate electrode is on the gate oxide layer, and the conductive semiconductor substrate forms the Schottky barrier between the semi-metal layer and the drain electrode: Page 2 Application No. 13/943,006 Attorney Docket No. 2557 SI -001965-US the insulating layer is between the semi-metal layer and the conductive semiconductor substrate, and the insulating layer is entirely above the surface of the conductive semiconductor substrate.
The memory device of claim 1, further comprising: a plurality of graphene switching devices arranged in a plurality of rows and a plurality of columns, each of the plurality of graphene switching devices having a source electrode, a drain electrode, and a gate electrode, and each of the plurality of graphene switching devices including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode.
The memory device of claim 1, wherein the substrate includes at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), a Group I II -V semiconductor, a Group I I -VI semiconductor, semiconductor Page 3 Application No. 13/943,006 Attorney Docket No. 2557 SI -001965-US carbon nanotube (CNT), molybdenum sulfide (MoS₂), indium zinc oxide (IZO), and gallium indium zin c oxide (GIZO).
The memory device of claim 1, wherein the drain electrode is spaced apart from the semimetal layer.
The memory device of claim 1, wherein the semi- metal layer is a graphene layer or a metal carbon nanotube (CNT) mesh.
The memory device of claim 1, wherein the drain electrode and the source electrode are formed of a metal or polysilicon (poly-Si).
The memory device of claim 1, wherein a height of the Schottky barrier varies according to a voltage applied to the gate electrode.
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A memory device comprising: a graphene switching device having a source electrode, a drain electrode, and a gate electrode, and the graphene switching device including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode, the graphene switching device further including Page 4 Application No. 13/943,006 Attorney Docket No. 2557S I -001965-US a conductive semiconductor substrate, wherein the drain electrode is on a first region of the substrate, and an insulating layer is on a second region of the substrate; a plurality of metal bumps on the substrate between the first region and the second region; a semi-metal layer on the plurality of metal bumps and extending onto the insulating layer, wherein the source electrode is on the semi-metal layer in the second region; and a gate oxide layer on the semi-metal layer, wherein the gate electrode on the gate oxide layer, and the substrate forms the Schottky barrier between the semi-metal layer and the drain electrode.
The memory device of claim 12, further comprising: a plurality of grooves on a surface of the substrate, the plurality of grooves corresponding to the plurality of metal bumps; and an insulating material filling the plurality of grooves.
The memory device of claim 12, wherein the plurality of metal bumps have a size of about 1 nm to about 10 nm.
The memory device of claim 12, wherein the plurality of metal bumps are arranged at intervals of about 10 nm to about 30 nm.
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A memory device comprising: a graphene switching device having a source electrode, a drain electrode, and a gate electrode, and the graphene switching device including a Schott k y barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode, wherein the graphene switching device further includes a conductive semiconductor substrate, wherein Page 6 Application No. 13/943,006 Attorney Docket No. 2557SI- 00 1965-US the drain electrode is on a first region of the conductive semiconductor substrate, and an insulating layer is on a second region of the conductive semiconductor substrate, the first and second regions being spaced apart from each other; a semi-metal layer on the conductive semiconductor substrate between the drain electrode and the insulating layer, the semi-metal layer extending onto the insulating layer such that a first portion of the semi-metal layer is on a surface of the conductive semiconductor substrate and a second portion of the semimetal layer is on a surface of the insulating layer, the semi-metal layer being a conductive layer, and the semi-metal layer being configured to electrode is on the semi-metal layer; and a gate gate electrode is on the gate oxide layer, the Schottky barrier between the semi-metal layer and the second portion of the semi-metal layer on the surface of the first portion of the semi-metal layer substrate. Page 7 function as the channel, wherein the source oxide layer on the semi-metal layer, wherein the conductive semiconductor substrate forms the drain electrode, and a bottom surface of insulating layer is raised relative to a bottom on the surface of the conductive semiconductor
Layer stacks claimed or described, ordered top of device to substrate.
graphene switching device (memory device, claim 1 embodiment)
graphene switching device with metal bumps (claim 12 embodiment)
Materials described outside the worked examples.
graphene
conductive semiconductor substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic cross-sectional view of a graphene switching device according to an example embodiment; [0023]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–30 nm | — |
Thickness | 1–10 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,299,789Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic circuit diagram of a memory array including graphene switching devices according to an example embodiment; [0022]
FIG. 2 is a schematic cross-sectional view of a graphene switching device according to an example embodiment; [0023]
FIGS. 3A through 3D are energy band diagrams for explaining example functionality of the graphene switching device of
FIG. 4 is an example current-voltage (1 -V) characteristic curve for an n-type graphene switching device according to an example embodiment; [0025]
FIG. 5 is an example I -V characteristic curve for a p-type graphene switching device according to an example embodiment; [0026]
FIG. 6 is a graph showing example drain current characteristics for an example embodiment of the graphene switching device of
FIG. 7 is a graph showing example drain current characteristics depending on application of a programming voltage; [0028]
FIG. 8 is a circuit diagram illustrating an example read operation; [0029]
FIG. 9 is a schematic cross-sectional view of a graphene switching device according to another example embodiment; [0030]
FIG. 10 is a diagram for explaining example functionality of the graphene switching device of
FIG. 11 is a schematic cross-sectional view of another example embodiment of a graphene switching device; and [0032]
FIG. 12 is a schematic cross-sectional view of yet another example embodiment of a graphene switching device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A memory device comprising: a graphene switching device having a source electrode, a drain electrode, and a gate electrode, and the graphene switching device including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode, wherein the graphene switching device further includes a conductive semiconductor substrate, wherein the drain electrode is on a first region of the conductive semiconductor substrate, and an insulating layer is on a second region of the conductive semiconductor substrate, the first and second regions being spaced apart from each other; a semimetal layer on the conductive semiconductor substrate between the drain electrode and the insulating layer, the semi-metal layer extending onto the insulating layer, the semi-metal layer being a conductive layer, and the semi-metal layer being configured to function as the channel, wherein the source electrode is on the semi-metal layer; and a gate oxide layer on the semi-metal layer, wherein the gate electrode is on the gate oxide layer, and the conductive semiconductor substrate forms the Schottky barrier between the semi-metal layer and the drain electrode: Page 2 Application No. 13/943,006 Attorney Docket No. 2557 SI -001965-US the insulating layer is between the semi-metal layer and the conductive semiconductor substrate, and the insulating layer is entirely above the surface of the conductive semiconductor substrate.
The memory device of claim 1, further comprising: a plurality of graphene switching devices arranged in a plurality of rows and a plurality of columns, each of the plurality of graphene switching devices having a source electrode, a drain electrode, and a gate electrode, and each of the plurality of graphene switching devices including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode.
The memory device of claim 1, wherein the substrate includes at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), a Group I II -V semiconductor, a Group I I -VI semiconductor, semiconductor Page 3 Application No. 13/943,006 Attorney Docket No. 2557 SI -001965-US carbon nanotube (CNT), molybdenum sulfide (MoS₂), indium zinc oxide (IZO), and gallium indium zin c oxide (GIZO).
The memory device of claim 1, wherein the drain electrode is spaced apart from the semimetal layer.
The memory device of claim 1, wherein the semi- metal layer is a graphene layer or a metal carbon nanotube (CNT) mesh.
The memory device of claim 1, wherein the drain electrode and the source electrode are formed of a metal or polysilicon (poly-Si).
The memory device of claim 1, wherein a height of the Schottky barrier varies according to a voltage applied to the gate electrode.
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A memory device comprising: a graphene switching device having a source electrode, a drain electrode, and a gate electrode, and the graphene switching device including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode, the graphene switching device further including Page 4 Application No. 13/943,006 Attorney Docket No. 2557S I -001965-US a conductive semiconductor substrate, wherein the drain electrode is on a first region of the substrate, and an insulating layer is on a second region of the substrate; a plurality of metal bumps on the substrate between the first region and the second region; a semi-metal layer on the plurality of metal bumps and extending onto the insulating layer, wherein the source electrode is on the semi-metal layer in the second region; and a gate oxide layer on the semi-metal layer, wherein the gate electrode on the gate oxide layer, and the substrate forms the Schottky barrier between the semi-metal layer and the drain electrode.
The memory device of claim 12, further comprising: a plurality of grooves on a surface of the substrate, the plurality of grooves corresponding to the plurality of metal bumps; and an insulating material filling the plurality of grooves.
The memory device of claim 12, wherein the plurality of metal bumps have a size of about 1 nm to about 10 nm.
The memory device of claim 12, wherein the plurality of metal bumps are arranged at intervals of about 10 nm to about 30 nm.
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A memory device comprising: a graphene switching device having a source electrode, a drain electrode, and a gate electrode, and the graphene switching device including a Schott k y barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode, wherein the graphene switching device further includes a conductive semiconductor substrate, wherein Page 6 Application No. 13/943,006 Attorney Docket No. 2557SI- 00 1965-US the drain electrode is on a first region of the conductive semiconductor substrate, and an insulating layer is on a second region of the conductive semiconductor substrate, the first and second regions being spaced apart from each other; a semi-metal layer on the conductive semiconductor substrate between the drain electrode and the insulating layer, the semi-metal layer extending onto the insulating layer such that a first portion of the semi-metal layer is on a surface of the conductive semiconductor substrate and a second portion of the semimetal layer is on a surface of the insulating layer, the semi-metal layer being a conductive layer, and the semi-metal layer being configured to electrode is on the semi-metal layer; and a gate gate electrode is on the gate oxide layer, the Schottky barrier between the semi-metal layer and the second portion of the semi-metal layer on the surface of the first portion of the semi-metal layer substrate. Page 7 function as the channel, wherein the source oxide layer on the semi-metal layer, wherein the conductive semiconductor substrate forms the drain electrode, and a bottom surface of insulating layer is raised relative to a bottom on the surface of the conductive semiconductor
Layer stacks claimed or described, ordered top of device to substrate.
graphene switching device (memory device, claim 1 embodiment)
graphene switching device with metal bumps (claim 12 embodiment)
Materials described outside the worked examples.
graphene
conductive semiconductor substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic cross-sectional view of a graphene switching device according to an example embodiment; [0023]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–30 nm | — |
Thickness | 1–10 nm |
Related documents with shared materials, methods, properties, or citations.
graphene switching device (claim 31 embodiment, raised insulating layer)
insulating layer
gate oxide layer
silicon
Si
germanium
Ge
silicon-germanium
SiGe
Group III-V semiconductor
Group II-VI semiconductor
molybdenum sulfide
MoS₂
indium zinc oxide
IZO
metal carbon nanotube mesh
polysilicon
poly-Si
metal bumps
organic layer
FIG. 6 is a graph showing example drain current characteristics for an example embodiment of the graphene switching device of
FIG. 6 is a graph showing example drain current characteristics for an example embodiment of the graphene switching device of
FIG. 7 is a graph showing example drain current characteristics depending on application of a programming voltage; [0028]
FIG. 7 is a graph showing example drain current characteristics depending on application of a programming voltage; [0028]
| — |
Thickness | 10–30 nm | — |
Thickness | 1–3 nm | — |
graphene switching device (claim 31 embodiment, raised insulating layer)
insulating layer
gate oxide layer
silicon
Si
germanium
Ge
silicon-germanium
SiGe
Group III-V semiconductor
Group II-VI semiconductor
molybdenum sulfide
MoS₂
indium zinc oxide
IZO
metal carbon nanotube mesh
polysilicon
poly-Si
metal bumps
organic layer
FIG. 6 is a graph showing example drain current characteristics for an example embodiment of the graphene switching device of
FIG. 6 is a graph showing example drain current characteristics for an example embodiment of the graphene switching device of
FIG. 7 is a graph showing example drain current characteristics depending on application of a programming voltage; [0028]
FIG. 7 is a graph showing example drain current characteristics depending on application of a programming voltage; [0028]
| — |
Thickness | 10–30 nm | — |
Thickness | 1–3 nm | — |
graphene switching device (claim 31 embodiment, raised insulating layer)
insulating layer
gate oxide layer
silicon
Si
germanium
Ge
silicon-germanium
SiGe
Group III-V semiconductor
Group II-VI semiconductor
molybdenum sulfide
MoS₂
indium zinc oxide
IZO
metal carbon nanotube mesh
polysilicon
poly-Si
metal bumps
organic layer
FIG. 6 is a graph showing example drain current characteristics for an example embodiment of the graphene switching device of
FIG. 6 is a graph showing example drain current characteristics for an example embodiment of the graphene switching device of
FIG. 7 is a graph showing example drain current characteristics depending on application of a programming voltage; [0028]
FIG. 7 is a graph showing example drain current characteristics depending on application of a programming voltage; [0028]
| — |
Thickness | 10–30 nm | — |
Thickness | 1–3 nm | — |
graphene switching device (claim 31 embodiment, raised insulating layer)
insulating layer
gate oxide layer
silicon
Si
germanium
Ge
silicon-germanium
SiGe
Group III-V semiconductor
Group II-VI semiconductor
molybdenum sulfide
MoS₂
indium zinc oxide
IZO
metal carbon nanotube mesh
polysilicon
poly-Si
metal bumps
organic layer
FIG. 6 is a graph showing example drain current characteristics for an example embodiment of the graphene switching device of
FIG. 6 is a graph showing example drain current characteristics for an example embodiment of the graphene switching device of
FIG. 7 is a graph showing example drain current characteristics depending on application of a programming voltage; [0028]
FIG. 7 is a graph showing example drain current characteristics depending on application of a programming voltage; [0028]
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Thickness | 10–30 nm | — |
Thickness | 1–3 nm | — |