Patent
Atlas literature
Patent
US 12,261,134 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram depicting an example process to manufacture monolithic microwave integrated circuits used 40 in electronic devices.
FIG. 2 is a diagram depicting at least a portion of a cross-section of an example monolithic microwave inte- grated circuit with aluminum-based electrical …
FIG. 3 is a diagram depicting an example process to form 45 electrical features on a substrate having an aluminum (Al) gallium nitride (GaN)/GaN semiconductor …
FIG. 4 is a diagram an example process to produce through substrate vias in a substrate having an AlGaN/GaN semiconductor layer. 50
FIG. 5 is an example process to produce aluminum-based interconnect devices for MMICs having an AlGaN/GaN semiconductor layer.
FIG. 6 is an example process to produce a gate electrical contact using a reduced enhancement of lithography by 55 assist of chemical shrink (RELACS) technique.
FIG. 7 is a flow diagram depicting operations of an example process to produce electrical features of a mono- lithic microwave integrated circuit having an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A process to form an aluminum (Al) based gallium nitride (GaN) monolithic microwave integrated circuit com-prises: providing a substrate having: a barrier layer that includes an AlGaN material and includes a drain region, a source region, and a gate region; and a channel layer disposed between a surface of the substrate and the barrier layer, the channel layer including a GaN material; depositing a gate electrical contact layer on the gate region of the barrier layer, the gate electrical contact layer including a first metallic material that includes Al; forming a gate electrical contact with the first metallic material of the gate electrical contact layer; depositing a source and drain electrical contact layer on the drain region and the source region of the barrier layer, the source and drain electrical contact layer including a second complementary metal oxide semiconductor (CMOS)-compatible metallic material that includes Al; forming a source electrical contact and a drain electrical contact using the second CMOS-compatible metallic material of the source and drain electrical contact layer; depositing a first amount of an Al-based metal on at least a first portion of the barrier layer and on at least a portion of the source electrical contact; forming a first electrical feature from the first amount of the Al-based metal; depositing a second amount of the Al-based metal on at least a second portion of the barrier layer and on at least a portion of the drain electrical contact; and forming a second electrical feature from the second amount of the Al-based metal.
The process of claim 1, wherein at least one of the first electrical feature or the second electrical feature includes a connector or a plate.
The process of claim 1, comprises: applying a mask layer to the first amount of the Al-based metal; forming the mask layer into a pattern; and removing a portion of the first amount of the Al-based metal according to at least a portion of the pattern to form the first electrical feature.
The process of claim 1, wherein the substrate includes silicon carbide (SiC) and has a diameter from about 140 mm to about 210 mm.
The process of claim 1, wherein a surface of the substrate has no greater than 1×1010 gold atoms per cm2.
The process of claim 1, comprises: depositing an amount of a dielectric material over the first electrical feature and over the second electrical feature; depositing a third amount of the Al-based metal over a portion of the dielectric material that is aligned with the first electrical feature; and forming a third electrical feature from the third amount of the Al-based metal; wherein the first electrical feature is a first plate of a capacitor and the third electrical feature is a second plate of the capacitor with a portion of the dielectric material disposed between the first plate and the second plate.
The process of claim 1, comprises: depositing an amount of an impedance device metal onto at least one of a portion of the barrier layer or a portion of the channel layer; and forming an impedance device from the amount of the impedance device metal; wherein: the second amount of the Al-based metal is deposited over 40 at least a portion of the impedance device; and the second electrical feature is a connector between the impedance device and the drain electrical contact.
The process of claim 1, wherein the first metallic material includes at least one layer of Al and at least one layer of titanium nitride (TiN) and the second CMOS-compatible metallic material includes at least one layer of Al and at least one layer of titanium (Ti).
The process of claim 1, comprises: forming a mask layer including an Al-based metal on an additional surface of the substrate, the additional sur-face of the substrate being at least substantially parallel with respect to the surface of the substrate; forming the mask layer into a pattern; removing a portion of the mask layer, a portion of the substrate, a portion of the channel layer, and a portion of the barrier layer according to the pattern to form a via through the mask layer, the substrate, the channel layer, and the barrier layer; and B₂ depositing an amount of the Al-based metal to at least partially fill the via.
The process of claim 1, comprises forming an addi-tional gate electrical contact with the first metallic material of the gate electrical contact layer; wherein a first length of the gate electrical contact is different from a second length of the additional gate electrical contact.
The process of claim 1, comprises reducing an initial thickness of the substrate by removing an amount of the substrate to produce a modified substrate having a modified thickness.
The process of claim 1, comprises: depositing a first dielectric material layer over the gate electrical contact, the source electrical contact, the drain electrical contact, and over at least one of exposed portions of the barrier layer or exposed portions of the channel layer; forming a pattern of first Al-based metal regions on the first dielectric material layer; depositing a second dielectric material layer over the pattern of first Al-based metal regions and over the first dielectric material layer; removing a portion of the second dielectric material layer according to a second pattern to produce a cavity that exposes a portion of a first Al-based metal region; depositing an amount of an Al-based metal into the cavity such that the amount of the Al-based metal fills the cavity to produce a connecting portion of the Al-based metal in the cavity and an excess portion of the amount of the Al-based metal overflows onto the second dielec-tric material layer; and forming a second Al-based metal region on the second dielectric material layer using the excess portion of the amount of the Al-based metal, the second Al-based metal region being coupled to the first Al-based metal region by the connecting portion.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT for Al-based MMIC
Al-based metal-insulator-metal capacitor
Materials described outside the worked examples.
AlGaN
GaN
Al-containing first metallic material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a diagram depicting at least a portion of a cross-section of an example monolithic microwave inte- grated circuit with aluminum-based electrical …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 130–170 mm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 71
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,261,134 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram depicting an example process to manufacture monolithic microwave integrated circuits used 40 in electronic devices.
FIG. 2 is a diagram depicting at least a portion of a cross-section of an example monolithic microwave inte- grated circuit with aluminum-based electrical …
FIG. 3 is a diagram depicting an example process to form 45 electrical features on a substrate having an aluminum (Al) gallium nitride (GaN)/GaN semiconductor …
FIG. 4 is a diagram an example process to produce through substrate vias in a substrate having an AlGaN/GaN semiconductor layer. 50
FIG. 5 is an example process to produce aluminum-based interconnect devices for MMICs having an AlGaN/GaN semiconductor layer.
FIG. 6 is an example process to produce a gate electrical contact using a reduced enhancement of lithography by 55 assist of chemical shrink (RELACS) technique.
FIG. 7 is a flow diagram depicting operations of an example process to produce electrical features of a mono- lithic microwave integrated circuit having an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A process to form an aluminum (Al) based gallium nitride (GaN) monolithic microwave integrated circuit com-prises: providing a substrate having: a barrier layer that includes an AlGaN material and includes a drain region, a source region, and a gate region; and a channel layer disposed between a surface of the substrate and the barrier layer, the channel layer including a GaN material; depositing a gate electrical contact layer on the gate region of the barrier layer, the gate electrical contact layer including a first metallic material that includes Al; forming a gate electrical contact with the first metallic material of the gate electrical contact layer; depositing a source and drain electrical contact layer on the drain region and the source region of the barrier layer, the source and drain electrical contact layer including a second complementary metal oxide semiconductor (CMOS)-compatible metallic material that includes Al; forming a source electrical contact and a drain electrical contact using the second CMOS-compatible metallic material of the source and drain electrical contact layer; depositing a first amount of an Al-based metal on at least a first portion of the barrier layer and on at least a portion of the source electrical contact; forming a first electrical feature from the first amount of the Al-based metal; depositing a second amount of the Al-based metal on at least a second portion of the barrier layer and on at least a portion of the drain electrical contact; and forming a second electrical feature from the second amount of the Al-based metal.
The process of claim 1, wherein at least one of the first electrical feature or the second electrical feature includes a connector or a plate.
The process of claim 1, comprises: applying a mask layer to the first amount of the Al-based metal; forming the mask layer into a pattern; and removing a portion of the first amount of the Al-based metal according to at least a portion of the pattern to form the first electrical feature.
The process of claim 1, wherein the substrate includes silicon carbide (SiC) and has a diameter from about 140 mm to about 210 mm.
The process of claim 1, wherein a surface of the substrate has no greater than 1×1010 gold atoms per cm2.
The process of claim 1, comprises: depositing an amount of a dielectric material over the first electrical feature and over the second electrical feature; depositing a third amount of the Al-based metal over a portion of the dielectric material that is aligned with the first electrical feature; and forming a third electrical feature from the third amount of the Al-based metal; wherein the first electrical feature is a first plate of a capacitor and the third electrical feature is a second plate of the capacitor with a portion of the dielectric material disposed between the first plate and the second plate.
The process of claim 1, comprises: depositing an amount of an impedance device metal onto at least one of a portion of the barrier layer or a portion of the channel layer; and forming an impedance device from the amount of the impedance device metal; wherein: the second amount of the Al-based metal is deposited over 40 at least a portion of the impedance device; and the second electrical feature is a connector between the impedance device and the drain electrical contact.
The process of claim 1, wherein the first metallic material includes at least one layer of Al and at least one layer of titanium nitride (TiN) and the second CMOS-compatible metallic material includes at least one layer of Al and at least one layer of titanium (Ti).
The process of claim 1, comprises: forming a mask layer including an Al-based metal on an additional surface of the substrate, the additional sur-face of the substrate being at least substantially parallel with respect to the surface of the substrate; forming the mask layer into a pattern; removing a portion of the mask layer, a portion of the substrate, a portion of the channel layer, and a portion of the barrier layer according to the pattern to form a via through the mask layer, the substrate, the channel layer, and the barrier layer; and B₂ depositing an amount of the Al-based metal to at least partially fill the via.
The process of claim 1, comprises forming an addi-tional gate electrical contact with the first metallic material of the gate electrical contact layer; wherein a first length of the gate electrical contact is different from a second length of the additional gate electrical contact.
The process of claim 1, comprises reducing an initial thickness of the substrate by removing an amount of the substrate to produce a modified substrate having a modified thickness.
The process of claim 1, comprises: depositing a first dielectric material layer over the gate electrical contact, the source electrical contact, the drain electrical contact, and over at least one of exposed portions of the barrier layer or exposed portions of the channel layer; forming a pattern of first Al-based metal regions on the first dielectric material layer; depositing a second dielectric material layer over the pattern of first Al-based metal regions and over the first dielectric material layer; removing a portion of the second dielectric material layer according to a second pattern to produce a cavity that exposes a portion of a first Al-based metal region; depositing an amount of an Al-based metal into the cavity such that the amount of the Al-based metal fills the cavity to produce a connecting portion of the Al-based metal in the cavity and an excess portion of the amount of the Al-based metal overflows onto the second dielec-tric material layer; and forming a second Al-based metal region on the second dielectric material layer using the excess portion of the amount of the Al-based metal, the second Al-based metal region being coupled to the first Al-based metal region by the connecting portion.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT for Al-based MMIC
Al-based metal-insulator-metal capacitor
Materials described outside the worked examples.
AlGaN
GaN
Al-containing first metallic material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a diagram depicting at least a portion of a cross-section of an example monolithic microwave inte- grated circuit with aluminum-based electrical …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 130–170 mm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 71
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,261,134 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram depicting an example process to manufacture monolithic microwave integrated circuits used 40 in electronic devices.
FIG. 2 is a diagram depicting at least a portion of a cross-section of an example monolithic microwave inte- grated circuit with aluminum-based electrical …
FIG. 3 is a diagram depicting an example process to form 45 electrical features on a substrate having an aluminum (Al) gallium nitride (GaN)/GaN semiconductor …
FIG. 4 is a diagram an example process to produce through substrate vias in a substrate having an AlGaN/GaN semiconductor layer. 50
FIG. 5 is an example process to produce aluminum-based interconnect devices for MMICs having an AlGaN/GaN semiconductor layer.
FIG. 6 is an example process to produce a gate electrical contact using a reduced enhancement of lithography by 55 assist of chemical shrink (RELACS) technique.
FIG. 7 is a flow diagram depicting operations of an example process to produce electrical features of a mono- lithic microwave integrated circuit having an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A process to form an aluminum (Al) based gallium nitride (GaN) monolithic microwave integrated circuit com-prises: providing a substrate having: a barrier layer that includes an AlGaN material and includes a drain region, a source region, and a gate region; and a channel layer disposed between a surface of the substrate and the barrier layer, the channel layer including a GaN material; depositing a gate electrical contact layer on the gate region of the barrier layer, the gate electrical contact layer including a first metallic material that includes Al; forming a gate electrical contact with the first metallic material of the gate electrical contact layer; depositing a source and drain electrical contact layer on the drain region and the source region of the barrier layer, the source and drain electrical contact layer including a second complementary metal oxide semiconductor (CMOS)-compatible metallic material that includes Al; forming a source electrical contact and a drain electrical contact using the second CMOS-compatible metallic material of the source and drain electrical contact layer; depositing a first amount of an Al-based metal on at least a first portion of the barrier layer and on at least a portion of the source electrical contact; forming a first electrical feature from the first amount of the Al-based metal; depositing a second amount of the Al-based metal on at least a second portion of the barrier layer and on at least a portion of the drain electrical contact; and forming a second electrical feature from the second amount of the Al-based metal.
The process of claim 1, wherein at least one of the first electrical feature or the second electrical feature includes a connector or a plate.
The process of claim 1, comprises: applying a mask layer to the first amount of the Al-based metal; forming the mask layer into a pattern; and removing a portion of the first amount of the Al-based metal according to at least a portion of the pattern to form the first electrical feature.
The process of claim 1, wherein the substrate includes silicon carbide (SiC) and has a diameter from about 140 mm to about 210 mm.
The process of claim 1, wherein a surface of the substrate has no greater than 1×1010 gold atoms per cm2.
The process of claim 1, comprises: depositing an amount of a dielectric material over the first electrical feature and over the second electrical feature; depositing a third amount of the Al-based metal over a portion of the dielectric material that is aligned with the first electrical feature; and forming a third electrical feature from the third amount of the Al-based metal; wherein the first electrical feature is a first plate of a capacitor and the third electrical feature is a second plate of the capacitor with a portion of the dielectric material disposed between the first plate and the second plate.
The process of claim 1, comprises: depositing an amount of an impedance device metal onto at least one of a portion of the barrier layer or a portion of the channel layer; and forming an impedance device from the amount of the impedance device metal; wherein: the second amount of the Al-based metal is deposited over 40 at least a portion of the impedance device; and the second electrical feature is a connector between the impedance device and the drain electrical contact.
The process of claim 1, wherein the first metallic material includes at least one layer of Al and at least one layer of titanium nitride (TiN) and the second CMOS-compatible metallic material includes at least one layer of Al and at least one layer of titanium (Ti).
The process of claim 1, comprises: forming a mask layer including an Al-based metal on an additional surface of the substrate, the additional sur-face of the substrate being at least substantially parallel with respect to the surface of the substrate; forming the mask layer into a pattern; removing a portion of the mask layer, a portion of the substrate, a portion of the channel layer, and a portion of the barrier layer according to the pattern to form a via through the mask layer, the substrate, the channel layer, and the barrier layer; and B₂ depositing an amount of the Al-based metal to at least partially fill the via.
The process of claim 1, comprises forming an addi-tional gate electrical contact with the first metallic material of the gate electrical contact layer; wherein a first length of the gate electrical contact is different from a second length of the additional gate electrical contact.
The process of claim 1, comprises reducing an initial thickness of the substrate by removing an amount of the substrate to produce a modified substrate having a modified thickness.
The process of claim 1, comprises: depositing a first dielectric material layer over the gate electrical contact, the source electrical contact, the drain electrical contact, and over at least one of exposed portions of the barrier layer or exposed portions of the channel layer; forming a pattern of first Al-based metal regions on the first dielectric material layer; depositing a second dielectric material layer over the pattern of first Al-based metal regions and over the first dielectric material layer; removing a portion of the second dielectric material layer according to a second pattern to produce a cavity that exposes a portion of a first Al-based metal region; depositing an amount of an Al-based metal into the cavity such that the amount of the Al-based metal fills the cavity to produce a connecting portion of the Al-based metal in the cavity and an excess portion of the amount of the Al-based metal overflows onto the second dielec-tric material layer; and forming a second Al-based metal region on the second dielectric material layer using the excess portion of the amount of the Al-based metal, the second Al-based metal region being coupled to the first Al-based metal region by the connecting portion.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT for Al-based MMIC
Al-based metal-insulator-metal capacitor
Materials described outside the worked examples.
AlGaN
GaN
Al-containing first metallic material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a diagram depicting at least a portion of a cross-section of an example monolithic microwave inte- grated circuit with aluminum-based electrical …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 130–170 mm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 71
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,261,134 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram depicting an example process to manufacture monolithic microwave integrated circuits used 40 in electronic devices.
FIG. 2 is a diagram depicting at least a portion of a cross-section of an example monolithic microwave inte- grated circuit with aluminum-based electrical …
FIG. 3 is a diagram depicting an example process to form 45 electrical features on a substrate having an aluminum (Al) gallium nitride (GaN)/GaN semiconductor …
FIG. 4 is a diagram an example process to produce through substrate vias in a substrate having an AlGaN/GaN semiconductor layer. 50
FIG. 5 is an example process to produce aluminum-based interconnect devices for MMICs having an AlGaN/GaN semiconductor layer.
FIG. 6 is an example process to produce a gate electrical contact using a reduced enhancement of lithography by 55 assist of chemical shrink (RELACS) technique.
FIG. 7 is a flow diagram depicting operations of an example process to produce electrical features of a mono- lithic microwave integrated circuit having an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A process to form an aluminum (Al) based gallium nitride (GaN) monolithic microwave integrated circuit com-prises: providing a substrate having: a barrier layer that includes an AlGaN material and includes a drain region, a source region, and a gate region; and a channel layer disposed between a surface of the substrate and the barrier layer, the channel layer including a GaN material; depositing a gate electrical contact layer on the gate region of the barrier layer, the gate electrical contact layer including a first metallic material that includes Al; forming a gate electrical contact with the first metallic material of the gate electrical contact layer; depositing a source and drain electrical contact layer on the drain region and the source region of the barrier layer, the source and drain electrical contact layer including a second complementary metal oxide semiconductor (CMOS)-compatible metallic material that includes Al; forming a source electrical contact and a drain electrical contact using the second CMOS-compatible metallic material of the source and drain electrical contact layer; depositing a first amount of an Al-based metal on at least a first portion of the barrier layer and on at least a portion of the source electrical contact; forming a first electrical feature from the first amount of the Al-based metal; depositing a second amount of the Al-based metal on at least a second portion of the barrier layer and on at least a portion of the drain electrical contact; and forming a second electrical feature from the second amount of the Al-based metal.
The process of claim 1, wherein at least one of the first electrical feature or the second electrical feature includes a connector or a plate.
The process of claim 1, comprises: applying a mask layer to the first amount of the Al-based metal; forming the mask layer into a pattern; and removing a portion of the first amount of the Al-based metal according to at least a portion of the pattern to form the first electrical feature.
The process of claim 1, wherein the substrate includes silicon carbide (SiC) and has a diameter from about 140 mm to about 210 mm.
The process of claim 1, wherein a surface of the substrate has no greater than 1×1010 gold atoms per cm2.
The process of claim 1, comprises: depositing an amount of a dielectric material over the first electrical feature and over the second electrical feature; depositing a third amount of the Al-based metal over a portion of the dielectric material that is aligned with the first electrical feature; and forming a third electrical feature from the third amount of the Al-based metal; wherein the first electrical feature is a first plate of a capacitor and the third electrical feature is a second plate of the capacitor with a portion of the dielectric material disposed between the first plate and the second plate.
The process of claim 1, comprises: depositing an amount of an impedance device metal onto at least one of a portion of the barrier layer or a portion of the channel layer; and forming an impedance device from the amount of the impedance device metal; wherein: the second amount of the Al-based metal is deposited over 40 at least a portion of the impedance device; and the second electrical feature is a connector between the impedance device and the drain electrical contact.
The process of claim 1, wherein the first metallic material includes at least one layer of Al and at least one layer of titanium nitride (TiN) and the second CMOS-compatible metallic material includes at least one layer of Al and at least one layer of titanium (Ti).
The process of claim 1, comprises: forming a mask layer including an Al-based metal on an additional surface of the substrate, the additional sur-face of the substrate being at least substantially parallel with respect to the surface of the substrate; forming the mask layer into a pattern; removing a portion of the mask layer, a portion of the substrate, a portion of the channel layer, and a portion of the barrier layer according to the pattern to form a via through the mask layer, the substrate, the channel layer, and the barrier layer; and B₂ depositing an amount of the Al-based metal to at least partially fill the via.
The process of claim 1, comprises forming an addi-tional gate electrical contact with the first metallic material of the gate electrical contact layer; wherein a first length of the gate electrical contact is different from a second length of the additional gate electrical contact.
The process of claim 1, comprises reducing an initial thickness of the substrate by removing an amount of the substrate to produce a modified substrate having a modified thickness.
The process of claim 1, comprises: depositing a first dielectric material layer over the gate electrical contact, the source electrical contact, the drain electrical contact, and over at least one of exposed portions of the barrier layer or exposed portions of the channel layer; forming a pattern of first Al-based metal regions on the first dielectric material layer; depositing a second dielectric material layer over the pattern of first Al-based metal regions and over the first dielectric material layer; removing a portion of the second dielectric material layer according to a second pattern to produce a cavity that exposes a portion of a first Al-based metal region; depositing an amount of an Al-based metal into the cavity such that the amount of the Al-based metal fills the cavity to produce a connecting portion of the Al-based metal in the cavity and an excess portion of the amount of the Al-based metal overflows onto the second dielec-tric material layer; and forming a second Al-based metal region on the second dielectric material layer using the excess portion of the amount of the Al-based metal, the second Al-based metal region being coupled to the first Al-based metal region by the connecting portion.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT for Al-based MMIC
Al-based metal-insulator-metal capacitor
Materials described outside the worked examples.
AlGaN
GaN
Al-containing first metallic material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a diagram depicting at least a portion of a cross-section of an example monolithic microwave inte- grated circuit with aluminum-based electrical …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 130–170 mm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 71
Related documents with shared materials, methods, properties, or citations.
Al-based interconnect device
Al-based inductor
Al-based metal
silicon carbide
SiC
dielectric material
silicon dioxide
SiO₂
disilicon trinitride
Si₂N₃
titanium nitride
TiN
aluminum
Al
titanium
Ti
Al-containing second CMOS-compatible metallic material
FIG. 3 is a diagram depicting an example process to form 45 electrical features on a substrate having an aluminum (Al) gallium nitride (GaN)/GaN semiconductor …
FIG. 6 is an example process to produce a gate electrical contact using a reduced enhancement of lithography by 55 assist of chemical shrink (RELACS) technique.
FIG. 7 is a flow diagram depicting operations of an example process to produce electrical features of a mono- lithic microwave integrated circuit having an …
| — |
Thickness | 140–210 mm | — |
Thickness | 250–800 µm | — |
Thickness | 80–125 mm | — |
Thickness | 100–300 nm | — |
Thickness | 125–200 nm | — |
Thickness | 400–1500 nm | — |
Thickness | 500–1000 nm | — |
Thickness | 1–15 µm | — |
Thickness | 2–12 µm | — |
Thickness | 3–10 µm | — |
Thickness | 1–50 nm | — |
Thickness | 10–30 nm | — |
Thickness | 1–10 µm | — |
Thickness | 2–5 µm | — |
Thickness | 2.5–8 µm | — |
Thickness | 3–6 µm | — |
Thickness | 2–6 µm | — |
Thickness | 175–500 nm | — |
Thickness | 200–400 nm | — |
Thickness | 250–500 µm | — |
Thickness | 100–200 µm | — |
Thickness | 30–150 nm | — |
Voltage | ≥ 30 V | — |
Voltage | ≥ 50 V | — |
Voltage | ≥ 80 V | — |
Voltage | ≥ 1 V | — |
Thickness | ≥ 1 µm | — |
Thickness | ≥ 2 µm | — |
Thickness | ≥ 3 µm | — |
Thickness | ≥ 4 µm | — |
Thickness | ≥ 10 µm | — |
Thickness | ≥ 8 µm | — |
Thickness | ≥ 6 µm | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 0.3 µm | — |
Thickness | ≥ 0.1 µm | — |
Thickness | ≥ 0.25 µm | — |
Thickness | ≥ 200 µm | — |
Thickness | ≥ 3.5 µm | — |
Cited non-patent literature · 5
Al-based interconnect device
Al-based inductor
Al-based metal
silicon carbide
SiC
dielectric material
silicon dioxide
SiO₂
disilicon trinitride
Si₂N₃
titanium nitride
TiN
aluminum
Al
titanium
Ti
Al-containing second CMOS-compatible metallic material
FIG. 3 is a diagram depicting an example process to form 45 electrical features on a substrate having an aluminum (Al) gallium nitride (GaN)/GaN semiconductor …
FIG. 6 is an example process to produce a gate electrical contact using a reduced enhancement of lithography by 55 assist of chemical shrink (RELACS) technique.
FIG. 7 is a flow diagram depicting operations of an example process to produce electrical features of a mono- lithic microwave integrated circuit having an …
| — |
Thickness | 140–210 mm | — |
Thickness | 250–800 µm | — |
Thickness | 80–125 mm | — |
Thickness | 100–300 nm | — |
Thickness | 125–200 nm | — |
Thickness | 400–1500 nm | — |
Thickness | 500–1000 nm | — |
Thickness | 1–15 µm | — |
Thickness | 2–12 µm | — |
Thickness | 3–10 µm | — |
Thickness | 1–50 nm | — |
Thickness | 10–30 nm | — |
Thickness | 1–10 µm | — |
Thickness | 2–5 µm | — |
Thickness | 2.5–8 µm | — |
Thickness | 3–6 µm | — |
Thickness | 2–6 µm | — |
Thickness | 175–500 nm | — |
Thickness | 200–400 nm | — |
Thickness | 250–500 µm | — |
Thickness | 100–200 µm | — |
Thickness | 30–150 nm | — |
Voltage | ≥ 30 V | — |
Voltage | ≥ 50 V | — |
Voltage | ≥ 80 V | — |
Voltage | ≥ 1 V | — |
Thickness | ≥ 1 µm | — |
Thickness | ≥ 2 µm | — |
Thickness | ≥ 3 µm | — |
Thickness | ≥ 4 µm | — |
Thickness | ≥ 10 µm | — |
Thickness | ≥ 8 µm | — |
Thickness | ≥ 6 µm | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 0.3 µm | — |
Thickness | ≥ 0.1 µm | — |
Thickness | ≥ 0.25 µm | — |
Thickness | ≥ 200 µm | — |
Thickness | ≥ 3.5 µm | — |
Cited non-patent literature · 5
Al-based interconnect device
Al-based inductor
Al-based metal
silicon carbide
SiC
dielectric material
silicon dioxide
SiO₂
disilicon trinitride
Si₂N₃
titanium nitride
TiN
aluminum
Al
titanium
Ti
Al-containing second CMOS-compatible metallic material
FIG. 3 is a diagram depicting an example process to form 45 electrical features on a substrate having an aluminum (Al) gallium nitride (GaN)/GaN semiconductor …
FIG. 6 is an example process to produce a gate electrical contact using a reduced enhancement of lithography by 55 assist of chemical shrink (RELACS) technique.
FIG. 7 is a flow diagram depicting operations of an example process to produce electrical features of a mono- lithic microwave integrated circuit having an …
| — |
Thickness | 140–210 mm | — |
Thickness | 250–800 µm | — |
Thickness | 80–125 mm | — |
Thickness | 100–300 nm | — |
Thickness | 125–200 nm | — |
Thickness | 400–1500 nm | — |
Thickness | 500–1000 nm | — |
Thickness | 1–15 µm | — |
Thickness | 2–12 µm | — |
Thickness | 3–10 µm | — |
Thickness | 1–50 nm | — |
Thickness | 10–30 nm | — |
Thickness | 1–10 µm | — |
Thickness | 2–5 µm | — |
Thickness | 2.5–8 µm | — |
Thickness | 3–6 µm | — |
Thickness | 2–6 µm | — |
Thickness | 175–500 nm | — |
Thickness | 200–400 nm | — |
Thickness | 250–500 µm | — |
Thickness | 100–200 µm | — |
Thickness | 30–150 nm | — |
Voltage | ≥ 30 V | — |
Voltage | ≥ 50 V | — |
Voltage | ≥ 80 V | — |
Voltage | ≥ 1 V | — |
Thickness | ≥ 1 µm | — |
Thickness | ≥ 2 µm | — |
Thickness | ≥ 3 µm | — |
Thickness | ≥ 4 µm | — |
Thickness | ≥ 10 µm | — |
Thickness | ≥ 8 µm | — |
Thickness | ≥ 6 µm | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 0.3 µm | — |
Thickness | ≥ 0.1 µm | — |
Thickness | ≥ 0.25 µm | — |
Thickness | ≥ 200 µm | — |
Thickness | ≥ 3.5 µm | — |
Cited non-patent literature · 5
Al-based interconnect device
Al-based inductor
Al-based metal
silicon carbide
SiC
dielectric material
silicon dioxide
SiO₂
disilicon trinitride
Si₂N₃
titanium nitride
TiN
aluminum
Al
titanium
Ti
Al-containing second CMOS-compatible metallic material
FIG. 3 is a diagram depicting an example process to form 45 electrical features on a substrate having an aluminum (Al) gallium nitride (GaN)/GaN semiconductor …
FIG. 6 is an example process to produce a gate electrical contact using a reduced enhancement of lithography by 55 assist of chemical shrink (RELACS) technique.
FIG. 7 is a flow diagram depicting operations of an example process to produce electrical features of a mono- lithic microwave integrated circuit having an …
| — |
Thickness | 140–210 mm | — |
Thickness | 250–800 µm | — |
Thickness | 80–125 mm | — |
Thickness | 100–300 nm | — |
Thickness | 125–200 nm | — |
Thickness | 400–1500 nm | — |
Thickness | 500–1000 nm | — |
Thickness | 1–15 µm | — |
Thickness | 2–12 µm | — |
Thickness | 3–10 µm | — |
Thickness | 1–50 nm | — |
Thickness | 10–30 nm | — |
Thickness | 1–10 µm | — |
Thickness | 2–5 µm | — |
Thickness | 2.5–8 µm | — |
Thickness | 3–6 µm | — |
Thickness | 2–6 µm | — |
Thickness | 175–500 nm | — |
Thickness | 200–400 nm | — |
Thickness | 250–500 µm | — |
Thickness | 100–200 µm | — |
Thickness | 30–150 nm | — |
Voltage | ≥ 30 V | — |
Voltage | ≥ 50 V | — |
Voltage | ≥ 80 V | — |
Voltage | ≥ 1 V | — |
Thickness | ≥ 1 µm | — |
Thickness | ≥ 2 µm | — |
Thickness | ≥ 3 µm | — |
Thickness | ≥ 4 µm | — |
Thickness | ≥ 10 µm | — |
Thickness | ≥ 8 µm | — |
Thickness | ≥ 6 µm | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 0.3 µm | — |
Thickness | ≥ 0.1 µm | — |
Thickness | ≥ 0.25 µm | — |
Thickness | ≥ 200 µm | — |
Thickness | ≥ 3.5 µm | — |
Cited non-patent literature · 5
