Patent
US 10,861,943TRANSISTOR WITH MULTIPLE GAN-BASED ALLOY LAYERS
Dong Seup LEE
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,861,943Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(a) depicts a cross-section of an illustrative GaN-based high electron mobility transistor (HEMT), in accordance with various examples; [0007]
FIG. 2(a) depicts a cross-section of yet another illustrative GaN-based HEMT, in accordance with various examples; [0009]
FIG. 3 depicts an illustrative method 300 to fabricate an illustrative GaN-based HEMT, in accordance with various examples; and [0011] FIGs. 4(a)-4(d) depicts …
FIG. 4(a) also depicts another GaN-based alloy layer 440, which, in subsequent steps, will be used to cover one or more portions of the top side 403. The GaN …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor, comprising: a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer, wherein the drain contact structure disposed on the second GaN-based alloy la yer such that the drain contact structure is separated from the first GaN-based alloy layer by the second GaN-based alloy layer.
The transistor of claim 1 further comprising a third GaN- based alloy layer disposed on the first GaN based alloy layer, the third GaN- based alloy layer covers a second portion of the top side.
The transistor of claim 1, wherein the drain contact structure forms an ohmic contact with the second GaN-based alloy layer, the source contact structure forms an ohmic contact with the first GaN-based alloy layer.
The transistor of claim 1, wherein the second GaN-based alloy layer is at least partially positioned in a drain access region and contacts the drain contact structure.
A transistor, comprising: a g allium nitride (GaN) layer; a first GaN-based alloy layer havin g a top side and disposed on the GaN laver; a second GaN-based alloy la y er disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; a source contact structure, a drain contact structure, and a g ate contact structure, wherein the source, drain, and q ate contact structures are supported by the first GaN-based alloy layer; and SVG 16216874.04-21-2020.K₉AFYFEYRXEAPX2.CLM.1.svg 0.16 6.01 Black and white positioned on the top side, wherein the gate contact structure is positioned on the p-doped GaN layer.
Canceled
A transistor, comprising: a g allium nitride (GaN) layer; a first GaN-based alloy la y er positioned on the GaN la yer; a second GaN-based alloy la y er positioned on a first portion of the first GaN-based alloy layer, wherein a two-dimensional electron qas (2 DEG) forms with different electron densities at an interface of the GaN layer and the first GaN-based alloy layer; a source contact structure, a drain contact structure, and a q ate contact structure, wherein the source, drain, and g ate contact structures are supported by the first GaN-based alloy layer; and a p-doped GaN layer positioned on a second portion of the first GaN-based alloy layer, wherein the gate contact structure is positioned on the p-doped GaN layer.
The transistor of claim 10 further comprising a third GaN- based alloy layer positioned on a third portion of the first GaN-based alloy layer, wherein the source contact structure contacts the third GaN-based alloy layer and the drain contact structure contacts the second GaN-based alloy layer.
A method, comprising: providing a substrate including a gallium nitride (GaN) layer, a first GaN- based alloy layer disposed on the GaN layer and having a top side; forming a second GaN-based alloy layer disposed on a first portion of the first GaN-based alloy layer; and forming source, drain, and gate contact structures supported by the first GaN-based alloy layer, the drain contact structure bein q separated from the first GaN-based alloy la y er by the second GaN-based alloy layer.
The method of claim 13 further comprising forming a third GaN-based alloy layer disposed on a second portion of the first GaN-based alloy layer.
A method, comprisin g: providin g a substrate includin q a q allium nitride (GaN) la y er, a first GaN- based alloy layer disposed on the GaN layer and havin q a top side; formin q a second GaN-based alloy layer disposed on a first portion of the first GaN-based alloy layer; formin q source, drain, and q ate contact structures supported by the first GaN-based alloy layer; and SVG 16216874.04-21-2020.K₉AFYFEYRXEAPX2.CLM.2.svg 0.16 5.5 Black and white (pGaN) on the first GaN-based alloy layer, wherein the gate contact structure is positioned on the pGaN layer.
A method, comprising: providing a substrate including a gallium nitride (GaN) layer, a first GaN- based alloy layer disposed on the GaN layer and having a top side; forming a second GaN-based alloy layer disposed on a first portion and a second portion of the first GaN-based alloy layer but not on a third portion of the first GaN-based alloy layer; and forming source, drain, and gate contact structures supported by the first GaN-based alloy layer, the source and drain contact structures contacting the second GaN-based alloy layer on the first and second portions, respectively, and the gate contact structure over the third portion of the first GaN-based alloy layer not contacting the second GaN-based alloy layer.
A transistor comprising: a substrate including alloy layer disposed on the GaN layer and having disposed on a first portion and a second portion of third portion of the first GaN-based alloy layer; supported by the first GaN- based alloy layer, the second GaN-based alloy layer on the first and contact structure over the third portion of the first second GaN-based alloy layer. a gallium nitride (GaN) layer, a first GaN-based a top side; a second GaN-based alloy layer the first GaN-based alloy layer but not on a and source, drain, and gate contact structures source and drain contact structures contacting second portions, respectively, and the gate GaN-based alloy layer not contacting the
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT with selective drain-side cap layer
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
first GaN-based alloy layer
Al(X₁)In(Y₁)Ga(1-X₁-Y₁)N
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(a) depicts a cross-section of an illustrative GaN-based high electron mobility transistor (HEMT), in accordance with various examples; [0007]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–500 nm | — |
Thickness | 5–500 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,861,943Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(a) depicts a cross-section of an illustrative GaN-based high electron mobility transistor (HEMT), in accordance with various examples; [0007]
FIG. 2(a) depicts a cross-section of yet another illustrative GaN-based HEMT, in accordance with various examples; [0009]
FIG. 3 depicts an illustrative method 300 to fabricate an illustrative GaN-based HEMT, in accordance with various examples; and [0011] FIGs. 4(a)-4(d) depicts …
FIG. 4(a) also depicts another GaN-based alloy layer 440, which, in subsequent steps, will be used to cover one or more portions of the top side 403. The GaN …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor, comprising: a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer, wherein the drain contact structure disposed on the second GaN-based alloy la yer such that the drain contact structure is separated from the first GaN-based alloy layer by the second GaN-based alloy layer.
The transistor of claim 1 further comprising a third GaN- based alloy layer disposed on the first GaN based alloy layer, the third GaN- based alloy layer covers a second portion of the top side.
The transistor of claim 1, wherein the drain contact structure forms an ohmic contact with the second GaN-based alloy layer, the source contact structure forms an ohmic contact with the first GaN-based alloy layer.
The transistor of claim 1, wherein the second GaN-based alloy layer is at least partially positioned in a drain access region and contacts the drain contact structure.
A transistor, comprising: a g allium nitride (GaN) layer; a first GaN-based alloy layer havin g a top side and disposed on the GaN laver; a second GaN-based alloy la y er disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; a source contact structure, a drain contact structure, and a g ate contact structure, wherein the source, drain, and q ate contact structures are supported by the first GaN-based alloy layer; and SVG 16216874.04-21-2020.K₉AFYFEYRXEAPX2.CLM.1.svg 0.16 6.01 Black and white positioned on the top side, wherein the gate contact structure is positioned on the p-doped GaN layer.
Canceled
A transistor, comprising: a g allium nitride (GaN) layer; a first GaN-based alloy la y er positioned on the GaN la yer; a second GaN-based alloy la y er positioned on a first portion of the first GaN-based alloy layer, wherein a two-dimensional electron qas (2 DEG) forms with different electron densities at an interface of the GaN layer and the first GaN-based alloy layer; a source contact structure, a drain contact structure, and a q ate contact structure, wherein the source, drain, and g ate contact structures are supported by the first GaN-based alloy layer; and a p-doped GaN layer positioned on a second portion of the first GaN-based alloy layer, wherein the gate contact structure is positioned on the p-doped GaN layer.
The transistor of claim 10 further comprising a third GaN- based alloy layer positioned on a third portion of the first GaN-based alloy layer, wherein the source contact structure contacts the third GaN-based alloy layer and the drain contact structure contacts the second GaN-based alloy layer.
A method, comprising: providing a substrate including a gallium nitride (GaN) layer, a first GaN- based alloy layer disposed on the GaN layer and having a top side; forming a second GaN-based alloy layer disposed on a first portion of the first GaN-based alloy layer; and forming source, drain, and gate contact structures supported by the first GaN-based alloy layer, the drain contact structure bein q separated from the first GaN-based alloy la y er by the second GaN-based alloy layer.
The method of claim 13 further comprising forming a third GaN-based alloy layer disposed on a second portion of the first GaN-based alloy layer.
A method, comprisin g: providin g a substrate includin q a q allium nitride (GaN) la y er, a first GaN- based alloy layer disposed on the GaN layer and havin q a top side; formin q a second GaN-based alloy layer disposed on a first portion of the first GaN-based alloy layer; formin q source, drain, and q ate contact structures supported by the first GaN-based alloy layer; and SVG 16216874.04-21-2020.K₉AFYFEYRXEAPX2.CLM.2.svg 0.16 5.5 Black and white (pGaN) on the first GaN-based alloy layer, wherein the gate contact structure is positioned on the pGaN layer.
A method, comprising: providing a substrate including a gallium nitride (GaN) layer, a first GaN- based alloy layer disposed on the GaN layer and having a top side; forming a second GaN-based alloy layer disposed on a first portion and a second portion of the first GaN-based alloy layer but not on a third portion of the first GaN-based alloy layer; and forming source, drain, and gate contact structures supported by the first GaN-based alloy layer, the source and drain contact structures contacting the second GaN-based alloy layer on the first and second portions, respectively, and the gate contact structure over the third portion of the first GaN-based alloy layer not contacting the second GaN-based alloy layer.
A transistor comprising: a substrate including alloy layer disposed on the GaN layer and having disposed on a first portion and a second portion of third portion of the first GaN-based alloy layer; supported by the first GaN- based alloy layer, the second GaN-based alloy layer on the first and contact structure over the third portion of the first second GaN-based alloy layer. a gallium nitride (GaN) layer, a first GaN-based a top side; a second GaN-based alloy layer the first GaN-based alloy layer but not on a and source, drain, and gate contact structures source and drain contact structures contacting second portions, respectively, and the gate GaN-based alloy layer not contacting the
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT with selective drain-side cap layer
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
first GaN-based alloy layer
Al(X₁)In(Y₁)Ga(1-X₁-Y₁)N
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(a) depicts a cross-section of an illustrative GaN-based high electron mobility transistor (HEMT), in accordance with various examples; [0007]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–500 nm | — |
Thickness | 5–500 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,861,943Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(a) depicts a cross-section of an illustrative GaN-based high electron mobility transistor (HEMT), in accordance with various examples; [0007]
FIG. 2(a) depicts a cross-section of yet another illustrative GaN-based HEMT, in accordance with various examples; [0009]
FIG. 3 depicts an illustrative method 300 to fabricate an illustrative GaN-based HEMT, in accordance with various examples; and [0011] FIGs. 4(a)-4(d) depicts …
FIG. 4(a) also depicts another GaN-based alloy layer 440, which, in subsequent steps, will be used to cover one or more portions of the top side 403. The GaN …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor, comprising: a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer, wherein the drain contact structure disposed on the second GaN-based alloy la yer such that the drain contact structure is separated from the first GaN-based alloy layer by the second GaN-based alloy layer.
The transistor of claim 1 further comprising a third GaN- based alloy layer disposed on the first GaN based alloy layer, the third GaN- based alloy layer covers a second portion of the top side.
The transistor of claim 1, wherein the drain contact structure forms an ohmic contact with the second GaN-based alloy layer, the source contact structure forms an ohmic contact with the first GaN-based alloy layer.
The transistor of claim 1, wherein the second GaN-based alloy layer is at least partially positioned in a drain access region and contacts the drain contact structure.
A transistor, comprising: a g allium nitride (GaN) layer; a first GaN-based alloy layer havin g a top side and disposed on the GaN laver; a second GaN-based alloy la y er disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; a source contact structure, a drain contact structure, and a g ate contact structure, wherein the source, drain, and q ate contact structures are supported by the first GaN-based alloy layer; and SVG 16216874.04-21-2020.K₉AFYFEYRXEAPX2.CLM.1.svg 0.16 6.01 Black and white positioned on the top side, wherein the gate contact structure is positioned on the p-doped GaN layer.
Canceled
A transistor, comprising: a g allium nitride (GaN) layer; a first GaN-based alloy la y er positioned on the GaN la yer; a second GaN-based alloy la y er positioned on a first portion of the first GaN-based alloy layer, wherein a two-dimensional electron qas (2 DEG) forms with different electron densities at an interface of the GaN layer and the first GaN-based alloy layer; a source contact structure, a drain contact structure, and a q ate contact structure, wherein the source, drain, and g ate contact structures are supported by the first GaN-based alloy layer; and a p-doped GaN layer positioned on a second portion of the first GaN-based alloy layer, wherein the gate contact structure is positioned on the p-doped GaN layer.
The transistor of claim 10 further comprising a third GaN- based alloy layer positioned on a third portion of the first GaN-based alloy layer, wherein the source contact structure contacts the third GaN-based alloy layer and the drain contact structure contacts the second GaN-based alloy layer.
A method, comprising: providing a substrate including a gallium nitride (GaN) layer, a first GaN- based alloy layer disposed on the GaN layer and having a top side; forming a second GaN-based alloy layer disposed on a first portion of the first GaN-based alloy layer; and forming source, drain, and gate contact structures supported by the first GaN-based alloy layer, the drain contact structure bein q separated from the first GaN-based alloy la y er by the second GaN-based alloy layer.
The method of claim 13 further comprising forming a third GaN-based alloy layer disposed on a second portion of the first GaN-based alloy layer.
A method, comprisin g: providin g a substrate includin q a q allium nitride (GaN) la y er, a first GaN- based alloy layer disposed on the GaN layer and havin q a top side; formin q a second GaN-based alloy layer disposed on a first portion of the first GaN-based alloy layer; formin q source, drain, and q ate contact structures supported by the first GaN-based alloy layer; and SVG 16216874.04-21-2020.K₉AFYFEYRXEAPX2.CLM.2.svg 0.16 5.5 Black and white (pGaN) on the first GaN-based alloy layer, wherein the gate contact structure is positioned on the pGaN layer.
A method, comprising: providing a substrate including a gallium nitride (GaN) layer, a first GaN- based alloy layer disposed on the GaN layer and having a top side; forming a second GaN-based alloy layer disposed on a first portion and a second portion of the first GaN-based alloy layer but not on a third portion of the first GaN-based alloy layer; and forming source, drain, and gate contact structures supported by the first GaN-based alloy layer, the source and drain contact structures contacting the second GaN-based alloy layer on the first and second portions, respectively, and the gate contact structure over the third portion of the first GaN-based alloy layer not contacting the second GaN-based alloy layer.
A transistor comprising: a substrate including alloy layer disposed on the GaN layer and having disposed on a first portion and a second portion of third portion of the first GaN-based alloy layer; supported by the first GaN- based alloy layer, the second GaN-based alloy layer on the first and contact structure over the third portion of the first second GaN-based alloy layer. a gallium nitride (GaN) layer, a first GaN-based a top side; a second GaN-based alloy layer the first GaN-based alloy layer but not on a and source, drain, and gate contact structures source and drain contact structures contacting second portions, respectively, and the gate GaN-based alloy layer not contacting the
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT with selective drain-side cap layer
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
first GaN-based alloy layer
Al(X₁)In(Y₁)Ga(1-X₁-Y₁)N
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(a) depicts a cross-section of an illustrative GaN-based high electron mobility transistor (HEMT), in accordance with various examples; [0007]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–500 nm | — |
Thickness | 5–500 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,861,943Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(a) depicts a cross-section of an illustrative GaN-based high electron mobility transistor (HEMT), in accordance with various examples; [0007]
FIG. 2(a) depicts a cross-section of yet another illustrative GaN-based HEMT, in accordance with various examples; [0009]
FIG. 3 depicts an illustrative method 300 to fabricate an illustrative GaN-based HEMT, in accordance with various examples; and [0011] FIGs. 4(a)-4(d) depicts …
FIG. 4(a) also depicts another GaN-based alloy layer 440, which, in subsequent steps, will be used to cover one or more portions of the top side 403. The GaN …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor, comprising: a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer, wherein the drain contact structure disposed on the second GaN-based alloy la yer such that the drain contact structure is separated from the first GaN-based alloy layer by the second GaN-based alloy layer.
The transistor of claim 1 further comprising a third GaN- based alloy layer disposed on the first GaN based alloy layer, the third GaN- based alloy layer covers a second portion of the top side.
The transistor of claim 1, wherein the drain contact structure forms an ohmic contact with the second GaN-based alloy layer, the source contact structure forms an ohmic contact with the first GaN-based alloy layer.
The transistor of claim 1, wherein the second GaN-based alloy layer is at least partially positioned in a drain access region and contacts the drain contact structure.
A transistor, comprising: a g allium nitride (GaN) layer; a first GaN-based alloy layer havin g a top side and disposed on the GaN laver; a second GaN-based alloy la y er disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; a source contact structure, a drain contact structure, and a g ate contact structure, wherein the source, drain, and q ate contact structures are supported by the first GaN-based alloy layer; and SVG 16216874.04-21-2020.K₉AFYFEYRXEAPX2.CLM.1.svg 0.16 6.01 Black and white positioned on the top side, wherein the gate contact structure is positioned on the p-doped GaN layer.
Canceled
A transistor, comprising: a g allium nitride (GaN) layer; a first GaN-based alloy la y er positioned on the GaN la yer; a second GaN-based alloy la y er positioned on a first portion of the first GaN-based alloy layer, wherein a two-dimensional electron qas (2 DEG) forms with different electron densities at an interface of the GaN layer and the first GaN-based alloy layer; a source contact structure, a drain contact structure, and a q ate contact structure, wherein the source, drain, and g ate contact structures are supported by the first GaN-based alloy layer; and a p-doped GaN layer positioned on a second portion of the first GaN-based alloy layer, wherein the gate contact structure is positioned on the p-doped GaN layer.
The transistor of claim 10 further comprising a third GaN- based alloy layer positioned on a third portion of the first GaN-based alloy layer, wherein the source contact structure contacts the third GaN-based alloy layer and the drain contact structure contacts the second GaN-based alloy layer.
A method, comprising: providing a substrate including a gallium nitride (GaN) layer, a first GaN- based alloy layer disposed on the GaN layer and having a top side; forming a second GaN-based alloy layer disposed on a first portion of the first GaN-based alloy layer; and forming source, drain, and gate contact structures supported by the first GaN-based alloy layer, the drain contact structure bein q separated from the first GaN-based alloy la y er by the second GaN-based alloy layer.
The method of claim 13 further comprising forming a third GaN-based alloy layer disposed on a second portion of the first GaN-based alloy layer.
A method, comprisin g: providin g a substrate includin q a q allium nitride (GaN) la y er, a first GaN- based alloy layer disposed on the GaN layer and havin q a top side; formin q a second GaN-based alloy layer disposed on a first portion of the first GaN-based alloy layer; formin q source, drain, and q ate contact structures supported by the first GaN-based alloy layer; and SVG 16216874.04-21-2020.K₉AFYFEYRXEAPX2.CLM.2.svg 0.16 5.5 Black and white (pGaN) on the first GaN-based alloy layer, wherein the gate contact structure is positioned on the pGaN layer.
A method, comprising: providing a substrate including a gallium nitride (GaN) layer, a first GaN- based alloy layer disposed on the GaN layer and having a top side; forming a second GaN-based alloy layer disposed on a first portion and a second portion of the first GaN-based alloy layer but not on a third portion of the first GaN-based alloy layer; and forming source, drain, and gate contact structures supported by the first GaN-based alloy layer, the source and drain contact structures contacting the second GaN-based alloy layer on the first and second portions, respectively, and the gate contact structure over the third portion of the first GaN-based alloy layer not contacting the second GaN-based alloy layer.
A transistor comprising: a substrate including alloy layer disposed on the GaN layer and having disposed on a first portion and a second portion of third portion of the first GaN-based alloy layer; supported by the first GaN- based alloy layer, the second GaN-based alloy layer on the first and contact structure over the third portion of the first second GaN-based alloy layer. a gallium nitride (GaN) layer, a first GaN-based a top side; a second GaN-based alloy layer the first GaN-based alloy layer but not on a and source, drain, and gate contact structures source and drain contact structures contacting second portions, respectively, and the gate GaN-based alloy layer not contacting the
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT with selective drain-side cap layer
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
first GaN-based alloy layer
Al(X₁)In(Y₁)Ga(1-X₁-Y₁)N
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(a) depicts a cross-section of an illustrative GaN-based high electron mobility transistor (HEMT), in accordance with various examples; [0007]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–500 nm | — |
Thickness | 5–500 nm |
Related documents with shared materials, methods, properties, or citations.
Enhancement-mode GaN HEMT with p-doped GaN gate and selective cap layer
GaN HEMT with second GaN-based alloy layer on source and drain regions but not gate region
second GaN-based alloy layer
Al(X₂)In(Y₂)Ga(1-X₂-Y₂)N
third GaN-based alloy layer
Al(X₃)In(Y₃)Ga(1-X₃-Y₃)N
p-doped GaN layer
GaN:p
AlGaN layer
AlGaN
aluminum nitride seed layer
AlN
Al(0.3)Ga(0.7)N
Al0.3Ga0.7N
| — |
Thickness | 0.1–0.5 µm | — |
Enhancement-mode GaN HEMT with p-doped GaN gate and selective cap layer
GaN HEMT with second GaN-based alloy layer on source and drain regions but not gate region
second GaN-based alloy layer
Al(X₂)In(Y₂)Ga(1-X₂-Y₂)N
third GaN-based alloy layer
Al(X₃)In(Y₃)Ga(1-X₃-Y₃)N
p-doped GaN layer
GaN:p
AlGaN layer
AlGaN
aluminum nitride seed layer
AlN
Al(0.3)Ga(0.7)N
Al0.3Ga0.7N
| — |
Thickness | 0.1–0.5 µm | — |
Enhancement-mode GaN HEMT with p-doped GaN gate and selective cap layer
GaN HEMT with second GaN-based alloy layer on source and drain regions but not gate region
second GaN-based alloy layer
Al(X₂)In(Y₂)Ga(1-X₂-Y₂)N
third GaN-based alloy layer
Al(X₃)In(Y₃)Ga(1-X₃-Y₃)N
p-doped GaN layer
GaN:p
AlGaN layer
AlGaN
aluminum nitride seed layer
AlN
Al(0.3)Ga(0.7)N
Al0.3Ga0.7N
| — |
Thickness | 0.1–0.5 µm | — |
Enhancement-mode GaN HEMT with p-doped GaN gate and selective cap layer
GaN HEMT with second GaN-based alloy layer on source and drain regions but not gate region
second GaN-based alloy layer
Al(X₂)In(Y₂)Ga(1-X₂-Y₂)N
third GaN-based alloy layer
Al(X₃)In(Y₃)Ga(1-X₃-Y₃)N
p-doped GaN layer
GaN:p
AlGaN layer
AlGaN
aluminum nitride seed layer
AlN
Al(0.3)Ga(0.7)N
Al0.3Ga0.7N
| — |
Thickness | 0.1–0.5 µm | — |