Patent
US 9,064,748Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof
Wilfried Ernst-August Haensch
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the transparent substrate is obscured by the channel material and thus is not visible. However, the transparent substrate is shown in illustrated in …
FIG. 2. As highlighted above, the illustration of graphene as the channel material in
FIG. 3. According to an exemplary embodiment, source and drain electrodes 302 are formed by first depositing a suitable metal over the transparent substrate and …
FIG. 4 is a cross-sectional diagram illustrating a dielectric layer having been deposited onto exposed top surfaces of the channel material, the transparent …
FIG. 5 is a cross-sectional diagram illustrating a positive photoresist having been deposited over the dielectric layer and development of the photoresist …
FIG. 6 is a cross-sectional diagram illustrating portions of the photoresist that remain over the source and drain electrodes once the developed portions of …
FIG. 7 is a cross-sectional diagram illustrating a gate metal(s) having been blanket deposited onto exposed portions of the dielectric layer and on the …
FIG. 8. According to an exemplary embodiment, the lift-off process involves leaving the wafer in a hot acetone at about 80 * C for a duration of from about 30 …
FIG. 9. For instance, the removal of the outer portion of the metal (portions 804) and the underlying dielectric is fully dependent on the specific application …
FIG. 10. Photoresist 1002 may be deposited in this manner using a spin-on deposition process. Any conventional photoresist material may be employed. Next, as …
FIG. 11, once the developed portions of the photoresist are removed (as described above), i.e., the photoresist is patterned, the remaining portions 1102 of …
FIG. 12 is a cross-sectional diagram illustrating a dielectric layer having been deposited onto exposed surfaces of the channel material, the remaining …
FIG. 13, a gate metal(s) 1302 is blanket deposited onto the dielectric layer 1202. Suitable gate metals, configurations (e.g., a multi-layer stack) and …
FIG. 14. Exemplary lift-off parameters were provided above. The result is gate 1402 (labeled "G"). Advantageously, since the photoresist portions 1102 (now …
FIG. 15. For instance, the removal of the outer portion of the metal (portions 1404) and the underlying dielectric is fully dependent on the specific …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a transparent substrate; a channel material on the substrate; source and drain electrodes over, and in contact with, the channel material; a dielectric layer on the channel material and on the source and drain electrodes; and a gate on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes, wherein the gate is present between the source and drain electrodes, a nd wherein portions of gate metal remain present on outer sides of the source and drain electrodes and are separated from the source and drain electrodes by the dielectric layer, such that top surfaces of the source and drain electrodes are accessible, and wherein the gate and the portions of the gate metal on the outer sides of the source and drain electrodes are separated by a gap present over the top surfaces of the source and drain electrodes.
The device of claim 1, wherein the transparent substrate comprises a glass substrate, or a flexible plastic substrate.
The device of claim 1, wherein the transparent substrate comprises a silicon carbide wafer.
The device of claim 1, wherein the channel material comprises a carbon-based material.
The device of claim 1, wherein the channel material comprises a nanostructured material selected from the group consisting of nanowires, nanorods, nanocolumns and quantum dots.
The device of claim 1, wherein the source and drain electrodes are present over, and in direct contact with, both the channel material and the transparent substrate, such that the source and drain electrodes cover opposite ends of the channel material and contact a surface of the transparent substrate beneath the channel material.
The device of claim 1, wherein the dielectric layer is present on, and in direct contact with, each of the channel material, the source and drain electrodes, and the transparent substrate.
The device of claim 1, wherein the dielectric layer has a thickness that permits UV light to pass therethrough.
1 1. The device of claim 1, wherein only the dielectric layer is present on, and in direct contact with, the top surfaces of the source and drain electrodes.
The device of claim 1, wherein the dielectric layer comprises one or more of hafnium oxide, aluminum oxide and silicon oxide.
The device of claim 1, wherein the dielectric layer has a thickness of from about 1 nanometer to about 50 nanometers.
The device of claim 1, wherein the source and drain electrodes each comprise one or more of gold, platinum or nickel.
The device of claim 1, wherein the gate metal comprises one or more of gold copper and aluminum.
The device of claim 1, wherein the dielectric layer is present on, and completely covers, both sides of the gate adjacent to the source and drain electrodes, and wherein the dielectric layer is absent from the top surfaces of the source and drain electrodes.
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
self-aligned gate transistor on transparent substrate
Materials described outside the worked examples.
channel material
carbon-based material
dielectric layer
glass substrate
flexible plastic substrate
silicon carbide wafer
SiC
graphene
carbon nanotubes
nanostructured material (nanowires, nanorods, nanocolumns, quantum dots)
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
silicon oxide
SiO₂
gold
Au
platinum
Pt
nickel
Ni
copper
Cu
aluminum
Al
graphene (CVD on Cu foil)
graphene (epitaxial on SiC)
PMMA
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the transparent substrate is obscured by the channel material and thus is not visible. However, the transparent substrate is shown in illustrated in …
FIG. 8. According to an exemplary embodiment, the lift-off process involves leaving the wafer in a hot acetone at about 80 * C for a duration of from about 30 …
FIG. 14. Exemplary lift-off parameters were provided above. The result is gate 1402 (labeled "G"). Advantageously, since the photoresist portions 1102 (now …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 500–800 °C | — |
Thickness | 1–50 nm | — |
Duration | 5–60 seconds | — |
Duration | 1800–3600 s | — |
Thickness | 1–100 nm | — |
Related documents with shared materials, methods, properties, or citations.
VERTICAL STACKING OF GRAPHENE IN A FIELD-EFFECT TRANSISTOR
Graphene-Based Solid State Devices Capable of Emitting Electromagnetic Radiation and Improvements Thereof
METHODS FOR INTEGRATING LEAD AND GRAPHENE GROWTH AND DEVICES FORMED THEREFROM
METHODS FOR N-TYPE DOPING OF GRAPHENE, AND N-TYPE-DOPED GRAPHENE COMPOSITIONS
METAL-FREE INTEGRATED CIRCUITS COMPRISING GRAPHENE AND CARBON NANOTUBES
METHOD FOR MANUFACTURING FLEXIBLE GRAPHENE ELECTRICALLY CONDUCTIVE FILM
METHOD FOR MANUFACTURING A GRAPHENE THIN-FILM TRANSISTOR
TRANSFER-FREE BATCH FABRICATION OF SINGLE LAYER GRAPHENE DEVICES
GRAPHENE FIELD EFFECT TRANSISTOR
SEMICONDUCTOR DEVICE WITH GRAPHENE LAYER AS CHANNEL
SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGEMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the transparent substrate is obscured by the channel material and thus is not visible. However, the transparent substrate is shown in illustrated in …
FIG. 2. As highlighted above, the illustration of graphene as the channel material in
FIG. 3. According to an exemplary embodiment, source and drain electrodes 302 are formed by first depositing a suitable metal over the transparent substrate and …
FIG. 4 is a cross-sectional diagram illustrating a dielectric layer having been deposited onto exposed top surfaces of the channel material, the transparent …
FIG. 5 is a cross-sectional diagram illustrating a positive photoresist having been deposited over the dielectric layer and development of the photoresist …
FIG. 6 is a cross-sectional diagram illustrating portions of the photoresist that remain over the source and drain electrodes once the developed portions of …
FIG. 7 is a cross-sectional diagram illustrating a gate metal(s) having been blanket deposited onto exposed portions of the dielectric layer and on the …
FIG. 8. According to an exemplary embodiment, the lift-off process involves leaving the wafer in a hot acetone at about 80 * C for a duration of from about 30 …
FIG. 9. For instance, the removal of the outer portion of the metal (portions 804) and the underlying dielectric is fully dependent on the specific application …
FIG. 10. Photoresist 1002 may be deposited in this manner using a spin-on deposition process. Any conventional photoresist material may be employed. Next, as …
FIG. 11, once the developed portions of the photoresist are removed (as described above), i.e., the photoresist is patterned, the remaining portions 1102 of …
FIG. 12 is a cross-sectional diagram illustrating a dielectric layer having been deposited onto exposed surfaces of the channel material, the remaining …
FIG. 13, a gate metal(s) 1302 is blanket deposited onto the dielectric layer 1202. Suitable gate metals, configurations (e.g., a multi-layer stack) and …
FIG. 14. Exemplary lift-off parameters were provided above. The result is gate 1402 (labeled "G"). Advantageously, since the photoresist portions 1102 (now …
FIG. 15. For instance, the removal of the outer portion of the metal (portions 1404) and the underlying dielectric is fully dependent on the specific …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a transparent substrate; a channel material on the substrate; source and drain electrodes over, and in contact with, the channel material; a dielectric layer on the channel material and on the source and drain electrodes; and a gate on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes, wherein the gate is present between the source and drain electrodes, a nd wherein portions of gate metal remain present on outer sides of the source and drain electrodes and are separated from the source and drain electrodes by the dielectric layer, such that top surfaces of the source and drain electrodes are accessible, and wherein the gate and the portions of the gate metal on the outer sides of the source and drain electrodes are separated by a gap present over the top surfaces of the source and drain electrodes.
The device of claim 1, wherein the transparent substrate comprises a glass substrate, or a flexible plastic substrate.
The device of claim 1, wherein the transparent substrate comprises a silicon carbide wafer.
The device of claim 1, wherein the channel material comprises a carbon-based material.
The device of claim 1, wherein the channel material comprises a nanostructured material selected from the group consisting of nanowires, nanorods, nanocolumns and quantum dots.
The device of claim 1, wherein the source and drain electrodes are present over, and in direct contact with, both the channel material and the transparent substrate, such that the source and drain electrodes cover opposite ends of the channel material and contact a surface of the transparent substrate beneath the channel material.
The device of claim 1, wherein the dielectric layer is present on, and in direct contact with, each of the channel material, the source and drain electrodes, and the transparent substrate.
The device of claim 1, wherein the dielectric layer has a thickness that permits UV light to pass therethrough.
1 1. The device of claim 1, wherein only the dielectric layer is present on, and in direct contact with, the top surfaces of the source and drain electrodes.
The device of claim 1, wherein the dielectric layer comprises one or more of hafnium oxide, aluminum oxide and silicon oxide.
The device of claim 1, wherein the dielectric layer has a thickness of from about 1 nanometer to about 50 nanometers.
The device of claim 1, wherein the source and drain electrodes each comprise one or more of gold, platinum or nickel.
The device of claim 1, wherein the gate metal comprises one or more of gold copper and aluminum.
The device of claim 1, wherein the dielectric layer is present on, and completely covers, both sides of the gate adjacent to the source and drain electrodes, and wherein the dielectric layer is absent from the top surfaces of the source and drain electrodes.
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
self-aligned gate transistor on transparent substrate
Materials described outside the worked examples.
channel material
carbon-based material
dielectric layer
glass substrate
flexible plastic substrate
silicon carbide wafer
SiC
graphene
carbon nanotubes
nanostructured material (nanowires, nanorods, nanocolumns, quantum dots)
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
silicon oxide
SiO₂
gold
Au
platinum
Pt
nickel
Ni
copper
Cu
aluminum
Al
graphene (CVD on Cu foil)
graphene (epitaxial on SiC)
PMMA
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the transparent substrate is obscured by the channel material and thus is not visible. However, the transparent substrate is shown in illustrated in …
FIG. 8. According to an exemplary embodiment, the lift-off process involves leaving the wafer in a hot acetone at about 80 * C for a duration of from about 30 …
FIG. 14. Exemplary lift-off parameters were provided above. The result is gate 1402 (labeled "G"). Advantageously, since the photoresist portions 1102 (now …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 500–800 °C | — |
Thickness | 1–50 nm | — |
Duration | 5–60 seconds | — |
Duration | 1800–3600 s | — |
Thickness | 1–100 nm | — |
Related documents with shared materials, methods, properties, or citations.
VERTICAL STACKING OF GRAPHENE IN A FIELD-EFFECT TRANSISTOR
Graphene-Based Solid State Devices Capable of Emitting Electromagnetic Radiation and Improvements Thereof
METHODS FOR INTEGRATING LEAD AND GRAPHENE GROWTH AND DEVICES FORMED THEREFROM
METHODS FOR N-TYPE DOPING OF GRAPHENE, AND N-TYPE-DOPED GRAPHENE COMPOSITIONS
METAL-FREE INTEGRATED CIRCUITS COMPRISING GRAPHENE AND CARBON NANOTUBES
METHOD FOR MANUFACTURING FLEXIBLE GRAPHENE ELECTRICALLY CONDUCTIVE FILM
METHOD FOR MANUFACTURING A GRAPHENE THIN-FILM TRANSISTOR
TRANSFER-FREE BATCH FABRICATION OF SINGLE LAYER GRAPHENE DEVICES
GRAPHENE FIELD EFFECT TRANSISTOR
SEMICONDUCTOR DEVICE WITH GRAPHENE LAYER AS CHANNEL
SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGEMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the transparent substrate is obscured by the channel material and thus is not visible. However, the transparent substrate is shown in illustrated in …
FIG. 2. As highlighted above, the illustration of graphene as the channel material in
FIG. 3. According to an exemplary embodiment, source and drain electrodes 302 are formed by first depositing a suitable metal over the transparent substrate and …
FIG. 4 is a cross-sectional diagram illustrating a dielectric layer having been deposited onto exposed top surfaces of the channel material, the transparent …
FIG. 5 is a cross-sectional diagram illustrating a positive photoresist having been deposited over the dielectric layer and development of the photoresist …
FIG. 6 is a cross-sectional diagram illustrating portions of the photoresist that remain over the source and drain electrodes once the developed portions of …
FIG. 7 is a cross-sectional diagram illustrating a gate metal(s) having been blanket deposited onto exposed portions of the dielectric layer and on the …
FIG. 8. According to an exemplary embodiment, the lift-off process involves leaving the wafer in a hot acetone at about 80 * C for a duration of from about 30 …
FIG. 9. For instance, the removal of the outer portion of the metal (portions 804) and the underlying dielectric is fully dependent on the specific application …
FIG. 10. Photoresist 1002 may be deposited in this manner using a spin-on deposition process. Any conventional photoresist material may be employed. Next, as …
FIG. 11, once the developed portions of the photoresist are removed (as described above), i.e., the photoresist is patterned, the remaining portions 1102 of …
FIG. 12 is a cross-sectional diagram illustrating a dielectric layer having been deposited onto exposed surfaces of the channel material, the remaining …
FIG. 13, a gate metal(s) 1302 is blanket deposited onto the dielectric layer 1202. Suitable gate metals, configurations (e.g., a multi-layer stack) and …
FIG. 14. Exemplary lift-off parameters were provided above. The result is gate 1402 (labeled "G"). Advantageously, since the photoresist portions 1102 (now …
FIG. 15. For instance, the removal of the outer portion of the metal (portions 1404) and the underlying dielectric is fully dependent on the specific …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a transparent substrate; a channel material on the substrate; source and drain electrodes over, and in contact with, the channel material; a dielectric layer on the channel material and on the source and drain electrodes; and a gate on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes, wherein the gate is present between the source and drain electrodes, a nd wherein portions of gate metal remain present on outer sides of the source and drain electrodes and are separated from the source and drain electrodes by the dielectric layer, such that top surfaces of the source and drain electrodes are accessible, and wherein the gate and the portions of the gate metal on the outer sides of the source and drain electrodes are separated by a gap present over the top surfaces of the source and drain electrodes.
The device of claim 1, wherein the transparent substrate comprises a glass substrate, or a flexible plastic substrate.
The device of claim 1, wherein the transparent substrate comprises a silicon carbide wafer.
The device of claim 1, wherein the channel material comprises a carbon-based material.
The device of claim 1, wherein the channel material comprises a nanostructured material selected from the group consisting of nanowires, nanorods, nanocolumns and quantum dots.
The device of claim 1, wherein the source and drain electrodes are present over, and in direct contact with, both the channel material and the transparent substrate, such that the source and drain electrodes cover opposite ends of the channel material and contact a surface of the transparent substrate beneath the channel material.
The device of claim 1, wherein the dielectric layer is present on, and in direct contact with, each of the channel material, the source and drain electrodes, and the transparent substrate.
The device of claim 1, wherein the dielectric layer has a thickness that permits UV light to pass therethrough.
1 1. The device of claim 1, wherein only the dielectric layer is present on, and in direct contact with, the top surfaces of the source and drain electrodes.
The device of claim 1, wherein the dielectric layer comprises one or more of hafnium oxide, aluminum oxide and silicon oxide.
The device of claim 1, wherein the dielectric layer has a thickness of from about 1 nanometer to about 50 nanometers.
The device of claim 1, wherein the source and drain electrodes each comprise one or more of gold, platinum or nickel.
The device of claim 1, wherein the gate metal comprises one or more of gold copper and aluminum.
The device of claim 1, wherein the dielectric layer is present on, and completely covers, both sides of the gate adjacent to the source and drain electrodes, and wherein the dielectric layer is absent from the top surfaces of the source and drain electrodes.
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
self-aligned gate transistor on transparent substrate
Materials described outside the worked examples.
channel material
carbon-based material
dielectric layer
glass substrate
flexible plastic substrate
silicon carbide wafer
SiC
graphene
carbon nanotubes
nanostructured material (nanowires, nanorods, nanocolumns, quantum dots)
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
silicon oxide
SiO₂
gold
Au
platinum
Pt
nickel
Ni
copper
Cu
aluminum
Al
graphene (CVD on Cu foil)
graphene (epitaxial on SiC)
PMMA
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the transparent substrate is obscured by the channel material and thus is not visible. However, the transparent substrate is shown in illustrated in …
FIG. 8. According to an exemplary embodiment, the lift-off process involves leaving the wafer in a hot acetone at about 80 * C for a duration of from about 30 …
FIG. 14. Exemplary lift-off parameters were provided above. The result is gate 1402 (labeled "G"). Advantageously, since the photoresist portions 1102 (now …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 500–800 °C | — |
Thickness | 1–50 nm | — |
Duration | 5–60 seconds | — |
Duration | 1800–3600 s | — |
Thickness | 1–100 nm | — |
Related documents with shared materials, methods, properties, or citations.
VERTICAL STACKING OF GRAPHENE IN A FIELD-EFFECT TRANSISTOR
Graphene-Based Solid State Devices Capable of Emitting Electromagnetic Radiation and Improvements Thereof
METHODS FOR INTEGRATING LEAD AND GRAPHENE GROWTH AND DEVICES FORMED THEREFROM
METHODS FOR N-TYPE DOPING OF GRAPHENE, AND N-TYPE-DOPED GRAPHENE COMPOSITIONS
METAL-FREE INTEGRATED CIRCUITS COMPRISING GRAPHENE AND CARBON NANOTUBES
METHOD FOR MANUFACTURING FLEXIBLE GRAPHENE ELECTRICALLY CONDUCTIVE FILM
METHOD FOR MANUFACTURING A GRAPHENE THIN-FILM TRANSISTOR
TRANSFER-FREE BATCH FABRICATION OF SINGLE LAYER GRAPHENE DEVICES
GRAPHENE FIELD EFFECT TRANSISTOR
SEMICONDUCTOR DEVICE WITH GRAPHENE LAYER AS CHANNEL
SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGEMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the transparent substrate is obscured by the channel material and thus is not visible. However, the transparent substrate is shown in illustrated in …
FIG. 2. As highlighted above, the illustration of graphene as the channel material in
FIG. 3. According to an exemplary embodiment, source and drain electrodes 302 are formed by first depositing a suitable metal over the transparent substrate and …
FIG. 4 is a cross-sectional diagram illustrating a dielectric layer having been deposited onto exposed top surfaces of the channel material, the transparent …
FIG. 5 is a cross-sectional diagram illustrating a positive photoresist having been deposited over the dielectric layer and development of the photoresist …
FIG. 6 is a cross-sectional diagram illustrating portions of the photoresist that remain over the source and drain electrodes once the developed portions of …
FIG. 7 is a cross-sectional diagram illustrating a gate metal(s) having been blanket deposited onto exposed portions of the dielectric layer and on the …
FIG. 8. According to an exemplary embodiment, the lift-off process involves leaving the wafer in a hot acetone at about 80 * C for a duration of from about 30 …
FIG. 9. For instance, the removal of the outer portion of the metal (portions 804) and the underlying dielectric is fully dependent on the specific application …
FIG. 10. Photoresist 1002 may be deposited in this manner using a spin-on deposition process. Any conventional photoresist material may be employed. Next, as …
FIG. 11, once the developed portions of the photoresist are removed (as described above), i.e., the photoresist is patterned, the remaining portions 1102 of …
FIG. 12 is a cross-sectional diagram illustrating a dielectric layer having been deposited onto exposed surfaces of the channel material, the remaining …
FIG. 13, a gate metal(s) 1302 is blanket deposited onto the dielectric layer 1202. Suitable gate metals, configurations (e.g., a multi-layer stack) and …
FIG. 14. Exemplary lift-off parameters were provided above. The result is gate 1402 (labeled "G"). Advantageously, since the photoresist portions 1102 (now …
FIG. 15. For instance, the removal of the outer portion of the metal (portions 1404) and the underlying dielectric is fully dependent on the specific …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a transparent substrate; a channel material on the substrate; source and drain electrodes over, and in contact with, the channel material; a dielectric layer on the channel material and on the source and drain electrodes; and a gate on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes, wherein the gate is present between the source and drain electrodes, a nd wherein portions of gate metal remain present on outer sides of the source and drain electrodes and are separated from the source and drain electrodes by the dielectric layer, such that top surfaces of the source and drain electrodes are accessible, and wherein the gate and the portions of the gate metal on the outer sides of the source and drain electrodes are separated by a gap present over the top surfaces of the source and drain electrodes.
The device of claim 1, wherein the transparent substrate comprises a glass substrate, or a flexible plastic substrate.
The device of claim 1, wherein the transparent substrate comprises a silicon carbide wafer.
The device of claim 1, wherein the channel material comprises a carbon-based material.
The device of claim 1, wherein the channel material comprises a nanostructured material selected from the group consisting of nanowires, nanorods, nanocolumns and quantum dots.
The device of claim 1, wherein the source and drain electrodes are present over, and in direct contact with, both the channel material and the transparent substrate, such that the source and drain electrodes cover opposite ends of the channel material and contact a surface of the transparent substrate beneath the channel material.
The device of claim 1, wherein the dielectric layer is present on, and in direct contact with, each of the channel material, the source and drain electrodes, and the transparent substrate.
The device of claim 1, wherein the dielectric layer has a thickness that permits UV light to pass therethrough.
1 1. The device of claim 1, wherein only the dielectric layer is present on, and in direct contact with, the top surfaces of the source and drain electrodes.
The device of claim 1, wherein the dielectric layer comprises one or more of hafnium oxide, aluminum oxide and silicon oxide.
The device of claim 1, wherein the dielectric layer has a thickness of from about 1 nanometer to about 50 nanometers.
The device of claim 1, wherein the source and drain electrodes each comprise one or more of gold, platinum or nickel.
The device of claim 1, wherein the gate metal comprises one or more of gold copper and aluminum.
The device of claim 1, wherein the dielectric layer is present on, and completely covers, both sides of the gate adjacent to the source and drain electrodes, and wherein the dielectric layer is absent from the top surfaces of the source and drain electrodes.
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
self-aligned gate transistor on transparent substrate
Materials described outside the worked examples.
channel material
carbon-based material
dielectric layer
glass substrate
flexible plastic substrate
silicon carbide wafer
SiC
graphene
carbon nanotubes
nanostructured material (nanowires, nanorods, nanocolumns, quantum dots)
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
silicon oxide
SiO₂
gold
Au
platinum
Pt
nickel
Ni
copper
Cu
aluminum
Al
graphene (CVD on Cu foil)
graphene (epitaxial on SiC)
PMMA
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the transparent substrate is obscured by the channel material and thus is not visible. However, the transparent substrate is shown in illustrated in …
FIG. 8. According to an exemplary embodiment, the lift-off process involves leaving the wafer in a hot acetone at about 80 * C for a duration of from about 30 …
FIG. 14. Exemplary lift-off parameters were provided above. The result is gate 1402 (labeled "G"). Advantageously, since the photoresist portions 1102 (now …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 500–800 °C | — |
Thickness | 1–50 nm | — |
Duration | 5–60 seconds | — |
Duration | 1800–3600 s | — |
Thickness | 1–100 nm | — |
Related documents with shared materials, methods, properties, or citations.
VERTICAL STACKING OF GRAPHENE IN A FIELD-EFFECT TRANSISTOR
Graphene-Based Solid State Devices Capable of Emitting Electromagnetic Radiation and Improvements Thereof
METHODS FOR INTEGRATING LEAD AND GRAPHENE GROWTH AND DEVICES FORMED THEREFROM
METHODS FOR N-TYPE DOPING OF GRAPHENE, AND N-TYPE-DOPED GRAPHENE COMPOSITIONS
METAL-FREE INTEGRATED CIRCUITS COMPRISING GRAPHENE AND CARBON NANOTUBES
METHOD FOR MANUFACTURING FLEXIBLE GRAPHENE ELECTRICALLY CONDUCTIVE FILM
METHOD FOR MANUFACTURING A GRAPHENE THIN-FILM TRANSISTOR
TRANSFER-FREE BATCH FABRICATION OF SINGLE LAYER GRAPHENE DEVICES
GRAPHENE FIELD EFFECT TRANSISTOR
SEMICONDUCTOR DEVICE WITH GRAPHENE LAYER AS CHANNEL
SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGEMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME