Patent
US 9,362,364single layer graphene transistor
Si
silicon dioxide
SiO₂
copper
Cu
nickel adhesion layer
Ni
transition metal growth substrate (nickel, cobalt, ruthenium, iridium, or transition metal)
acetic acid
CH₃COOH
FIG. 6B is a graph of median resistance (R m e dian) f or a va r iety of SLG devices produced using an embodiment of the manufacturing method discussed with …
FIG. 7 schematically illustrates a cross-section of an embodiment of a transistor comprising a single layer graphene channel grown partially on and coupling a …
FIG. 8 schematically illustrates a cross-section of another embodiment of a transistor comprising a single layer graphene channel grown partially on and …
FIG. 9B shows saturation current observed for negative drain- source bias (V D S) f o r an embodiment of the transistor illustrated in
| 3–6 mm |
| — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 0.5 mm | — |
single layer graphene transistor
Si
silicon dioxide
SiO₂
copper
Cu
nickel adhesion layer
Ni
transition metal growth substrate (nickel, cobalt, ruthenium, iridium, or transition metal)
acetic acid
CH₃COOH
FIG. 6B is a graph of median resistance (R m e dian) f or a va r iety of SLG devices produced using an embodiment of the manufacturing method discussed with …
FIG. 7 schematically illustrates a cross-section of an embodiment of a transistor comprising a single layer graphene channel grown partially on and coupling a …
FIG. 8 schematically illustrates a cross-section of another embodiment of a transistor comprising a single layer graphene channel grown partially on and …
FIG. 9B shows saturation current observed for negative drain- source bias (V D S) f o r an embodiment of the transistor illustrated in
| 3–6 mm |
| — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 0.5 mm | — |
single layer graphene transistor
Si
silicon dioxide
SiO₂
copper
Cu
nickel adhesion layer
Ni
transition metal growth substrate (nickel, cobalt, ruthenium, iridium, or transition metal)
acetic acid
CH₃COOH
FIG. 6B is a graph of median resistance (R m e dian) f or a va r iety of SLG devices produced using an embodiment of the manufacturing method discussed with …
FIG. 7 schematically illustrates a cross-section of an embodiment of a transistor comprising a single layer graphene channel grown partially on and coupling a …
FIG. 8 schematically illustrates a cross-section of another embodiment of a transistor comprising a single layer graphene channel grown partially on and …
FIG. 9B shows saturation current observed for negative drain- source bias (V D S) f o r an embodiment of the transistor illustrated in
| 3–6 mm |
| — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 0.5 mm | — |
single layer graphene transistor
Si
silicon dioxide
SiO₂
copper
Cu
nickel adhesion layer
Ni
transition metal growth substrate (nickel, cobalt, ruthenium, iridium, or transition metal)
acetic acid
CH₃COOH
FIG. 6B is a graph of median resistance (R m e dian) f or a va r iety of SLG devices produced using an embodiment of the manufacturing method discussed with …
FIG. 7 schematically illustrates a cross-section of an embodiment of a transistor comprising a single layer graphene channel grown partially on and coupling a …
FIG. 8 schematically illustrates a cross-section of another embodiment of a transistor comprising a single layer graphene channel grown partially on and …
FIG. 9B shows saturation current observed for negative drain- source bias (V D S) f o r an embodiment of the transistor illustrated in
| 3–6 mm |
| — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 0.5 mm | — |