Patent
US 8,932,919VERTICAL STACKING OF GRAPHENE IN A FIELD-EFFECT TRANSISTOR
Damon B. Farmer
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,932,919Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an exemplary single layer of a gate region of an exemplary graphene field-effect transistor disclosed herein;
Figure 2 shows an exemplary graphene field-effect transistor that includes multiple stacked graphene sheets;
Figure 3 shows a first manufacturing stage of an exemplary graphene field-effect transistor in which a sheet of graphene is disposed on a substrate;
Figure 4 shows a second stage of the manufacturing process in which source and drain contacts are formed;
Figure 5 shows a third stage of the manufacturing process in which a dielectric layer is formed on the graphene sheet of
Figure 6 shows a fourth stage of the manufacturing process in which a gate contact metal is formed on the dielectric layer of
Figure 7 shows a f ift h stage of the manufacturing process in which a second dielectric layer is deposited on the gate contact metal of
Figure 8 shows a sixth stage of the manufacturing process in which a second graphene sheet of the graphene field-effect transistor is formed;
Figure 9 shows a flowchart illustrating an exemplary method of forming the graphene field-effect transistor of the present invention; and
Figure 10 shows an exemplary graph illustrating the effect of multiple graphene sheets on various parameters of the exemplary graphene field-effect transistor of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A method of forming a graphene field-effect transistor, comprising: forming a first graphene sheet on a substrate; coupling d epositing a first gate layer on [[toll a top surface of the first graphene sheet, wherein the first gate layer influences to influence an electric field of the first graphene sheet; coupling d epositing at least one of a source contact and a drain contact on l[tol the top surface of the first graphene sheet; and coupling d epositing a second graphene sheet on top surfaces of [[toEl the first gate layer and the at least one of the source contact and the drain contact, wherein the first gate layer influences an electric field of the second graphene sheet.
(Cu rr ently Amended) The method of claim 1, further comprising forming depositing a second gate layer on a top surface of r toll the second graphene sheet and electrically coupling the first gate layer and the second gate layer.
The method of claim 1, wherein the first gate layer further comprises a gate contact metal sandwiched between dielectric layers.
The method of claim 1, wherein a thickness of the gate layer is substantially the same as the thickness of the at least one of the source contact and the drain contact.
The method of claim 1, further comprising stacking alternating layers of graphene sheets and gate layers to obtain a selected state of a parameter of the transistor.
canceled
(Cu rr ently Amended) A method of forming a gate region of a transistor, comprising: depositing a first gate layer and at least one of a source contact and a drain contact on the top surface of the first graphene sheet; depositing a second graphene sheet on top surfaces of the first gate layer and the at least one of the source contact and the drain contact; forming a second gate layer on a top surface of the second graphene sheet; and stacking a plurality of alternating layers of gate layers and graphene sheets, wherein at least one of a source contact and a drain contact corresponding to a selected gate layer is between graphene sheets surrounding the selected gate layer; and electrically coupling the first and second gate layers to each other to form the gate region of the transistor.
(Cu rr ently Amended) The method of claim 8 wherein stacking the plurality of alternating layers of gate contact metal and graphene further comprises further comprising forming [ail the first layer of graphene sheet on a substrate and vertically stacking the plurality of alternating layers of gate contact metal and graphene on top of the first layer of graphene.
(Cu rr ently Amended) The method of claim 8, further comprising stacking a l[the il plurality of alternating layers of gate layers and graphene sheets so that an electric field in a selected graphene sheet is affected by gate layers on opposite sides of the selected graphene sheet.
(Cu rr ently Amended) The method of claim 8, further comprising coupling the layers of graphene to the at least one of the source contact and the drain contact to the first graphene sheet and the second graphene sheet.
The method of claim 8 wherein a selected gate layer includes a gate contact metal sandwiched between dielectric layers.
(Cu rr ently Amended) A method of forming a transistor, comprising: depositing a first gate layer and at least one of a source contact and a drain contact on the top surface of the first graphene sheet; depositing a second graphene sheet on top surfaces of the first gate layer and the at least one of the source contact and the drain contact; forming a second gate layer on a top surface of the second graphene sheet; and stacking a plurality of alternating layers of gate layers and graphene sheets by forming a selected gate layer on a first one of the plurality of graphene sheets, forming at least one of a source contact and a drain contact on the first one of the plurality of graphene sheets, and forming a second one of the plurality of graphene sheets on the gate layer and the at least one of the source contact and the drain contact; and electrically coupling the first and second gate layers to each other.
(Cu rr ently Amended) The method of claim 15 wherein stacking the plurality SVG 13683148.07-28-2014.HY₈I₉SHTPXXIFW1.CLM.1.svg 0.17 5.84 Black and white forming l[all the first layer of graphene sheet on a substrate and vertically stacking the plurality of alternating layers of gate layer and graphene on top of the first layer of graphene.
The method of claim 15 wherein a selected sandwiched between insulator material.
The method of claim 15, wherein a thickness thickness of the at least one of the source contact
The method of claim 15 further comprising a selected state of a transistor parameter. YO 15, further comp ri sing stacking a l[the ll selected graphene sheet is affected by gate layers on gate layer includes a gate contact metal of the gate layer is substantially the same as the and the drain contact selecting a number of alternating layers to obtain R₉₂₀₁₂₀₇₇₁US₁
(Cu rr ently Amended) The method of claim plurality of layers so that an electric field in a opposite sides of the selected graphene sheet.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (single gate layer)
vertically stacked multi-layer graphene field-effect transistor
Materials described outside the worked examples.
graphene
graphene sheet (first)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 shows an exemplary single layer of a gate region of an exemplary graphene field-effect transistor disclosed herein;
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,932,919Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an exemplary single layer of a gate region of an exemplary graphene field-effect transistor disclosed herein;
Figure 2 shows an exemplary graphene field-effect transistor that includes multiple stacked graphene sheets;
Figure 3 shows a first manufacturing stage of an exemplary graphene field-effect transistor in which a sheet of graphene is disposed on a substrate;
Figure 4 shows a second stage of the manufacturing process in which source and drain contacts are formed;
Figure 5 shows a third stage of the manufacturing process in which a dielectric layer is formed on the graphene sheet of
Figure 6 shows a fourth stage of the manufacturing process in which a gate contact metal is formed on the dielectric layer of
Figure 7 shows a f ift h stage of the manufacturing process in which a second dielectric layer is deposited on the gate contact metal of
Figure 8 shows a sixth stage of the manufacturing process in which a second graphene sheet of the graphene field-effect transistor is formed;
Figure 9 shows a flowchart illustrating an exemplary method of forming the graphene field-effect transistor of the present invention; and
Figure 10 shows an exemplary graph illustrating the effect of multiple graphene sheets on various parameters of the exemplary graphene field-effect transistor of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A method of forming a graphene field-effect transistor, comprising: forming a first graphene sheet on a substrate; coupling d epositing a first gate layer on [[toll a top surface of the first graphene sheet, wherein the first gate layer influences to influence an electric field of the first graphene sheet; coupling d epositing at least one of a source contact and a drain contact on l[tol the top surface of the first graphene sheet; and coupling d epositing a second graphene sheet on top surfaces of [[toEl the first gate layer and the at least one of the source contact and the drain contact, wherein the first gate layer influences an electric field of the second graphene sheet.
(Cu rr ently Amended) The method of claim 1, further comprising forming depositing a second gate layer on a top surface of r toll the second graphene sheet and electrically coupling the first gate layer and the second gate layer.
The method of claim 1, wherein the first gate layer further comprises a gate contact metal sandwiched between dielectric layers.
The method of claim 1, wherein a thickness of the gate layer is substantially the same as the thickness of the at least one of the source contact and the drain contact.
The method of claim 1, further comprising stacking alternating layers of graphene sheets and gate layers to obtain a selected state of a parameter of the transistor.
canceled
(Cu rr ently Amended) A method of forming a gate region of a transistor, comprising: depositing a first gate layer and at least one of a source contact and a drain contact on the top surface of the first graphene sheet; depositing a second graphene sheet on top surfaces of the first gate layer and the at least one of the source contact and the drain contact; forming a second gate layer on a top surface of the second graphene sheet; and stacking a plurality of alternating layers of gate layers and graphene sheets, wherein at least one of a source contact and a drain contact corresponding to a selected gate layer is between graphene sheets surrounding the selected gate layer; and electrically coupling the first and second gate layers to each other to form the gate region of the transistor.
(Cu rr ently Amended) The method of claim 8 wherein stacking the plurality of alternating layers of gate contact metal and graphene further comprises further comprising forming [ail the first layer of graphene sheet on a substrate and vertically stacking the plurality of alternating layers of gate contact metal and graphene on top of the first layer of graphene.
(Cu rr ently Amended) The method of claim 8, further comprising stacking a l[the il plurality of alternating layers of gate layers and graphene sheets so that an electric field in a selected graphene sheet is affected by gate layers on opposite sides of the selected graphene sheet.
(Cu rr ently Amended) The method of claim 8, further comprising coupling the layers of graphene to the at least one of the source contact and the drain contact to the first graphene sheet and the second graphene sheet.
The method of claim 8 wherein a selected gate layer includes a gate contact metal sandwiched between dielectric layers.
(Cu rr ently Amended) A method of forming a transistor, comprising: depositing a first gate layer and at least one of a source contact and a drain contact on the top surface of the first graphene sheet; depositing a second graphene sheet on top surfaces of the first gate layer and the at least one of the source contact and the drain contact; forming a second gate layer on a top surface of the second graphene sheet; and stacking a plurality of alternating layers of gate layers and graphene sheets by forming a selected gate layer on a first one of the plurality of graphene sheets, forming at least one of a source contact and a drain contact on the first one of the plurality of graphene sheets, and forming a second one of the plurality of graphene sheets on the gate layer and the at least one of the source contact and the drain contact; and electrically coupling the first and second gate layers to each other.
(Cu rr ently Amended) The method of claim 15 wherein stacking the plurality SVG 13683148.07-28-2014.HY₈I₉SHTPXXIFW1.CLM.1.svg 0.17 5.84 Black and white forming l[all the first layer of graphene sheet on a substrate and vertically stacking the plurality of alternating layers of gate layer and graphene on top of the first layer of graphene.
The method of claim 15 wherein a selected sandwiched between insulator material.
The method of claim 15, wherein a thickness thickness of the at least one of the source contact
The method of claim 15 further comprising a selected state of a transistor parameter. YO 15, further comp ri sing stacking a l[the ll selected graphene sheet is affected by gate layers on gate layer includes a gate contact metal of the gate layer is substantially the same as the and the drain contact selecting a number of alternating layers to obtain R₉₂₀₁₂₀₇₇₁US₁
(Cu rr ently Amended) The method of claim plurality of layers so that an electric field in a opposite sides of the selected graphene sheet.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (single gate layer)
vertically stacked multi-layer graphene field-effect transistor
Materials described outside the worked examples.
graphene
graphene sheet (first)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 shows an exemplary single layer of a gate region of an exemplary graphene field-effect transistor disclosed herein;
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,932,919Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an exemplary single layer of a gate region of an exemplary graphene field-effect transistor disclosed herein;
Figure 2 shows an exemplary graphene field-effect transistor that includes multiple stacked graphene sheets;
Figure 3 shows a first manufacturing stage of an exemplary graphene field-effect transistor in which a sheet of graphene is disposed on a substrate;
Figure 4 shows a second stage of the manufacturing process in which source and drain contacts are formed;
Figure 5 shows a third stage of the manufacturing process in which a dielectric layer is formed on the graphene sheet of
Figure 6 shows a fourth stage of the manufacturing process in which a gate contact metal is formed on the dielectric layer of
Figure 7 shows a f ift h stage of the manufacturing process in which a second dielectric layer is deposited on the gate contact metal of
Figure 8 shows a sixth stage of the manufacturing process in which a second graphene sheet of the graphene field-effect transistor is formed;
Figure 9 shows a flowchart illustrating an exemplary method of forming the graphene field-effect transistor of the present invention; and
Figure 10 shows an exemplary graph illustrating the effect of multiple graphene sheets on various parameters of the exemplary graphene field-effect transistor of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A method of forming a graphene field-effect transistor, comprising: forming a first graphene sheet on a substrate; coupling d epositing a first gate layer on [[toll a top surface of the first graphene sheet, wherein the first gate layer influences to influence an electric field of the first graphene sheet; coupling d epositing at least one of a source contact and a drain contact on l[tol the top surface of the first graphene sheet; and coupling d epositing a second graphene sheet on top surfaces of [[toEl the first gate layer and the at least one of the source contact and the drain contact, wherein the first gate layer influences an electric field of the second graphene sheet.
(Cu rr ently Amended) The method of claim 1, further comprising forming depositing a second gate layer on a top surface of r toll the second graphene sheet and electrically coupling the first gate layer and the second gate layer.
The method of claim 1, wherein the first gate layer further comprises a gate contact metal sandwiched between dielectric layers.
The method of claim 1, wherein a thickness of the gate layer is substantially the same as the thickness of the at least one of the source contact and the drain contact.
The method of claim 1, further comprising stacking alternating layers of graphene sheets and gate layers to obtain a selected state of a parameter of the transistor.
canceled
(Cu rr ently Amended) A method of forming a gate region of a transistor, comprising: depositing a first gate layer and at least one of a source contact and a drain contact on the top surface of the first graphene sheet; depositing a second graphene sheet on top surfaces of the first gate layer and the at least one of the source contact and the drain contact; forming a second gate layer on a top surface of the second graphene sheet; and stacking a plurality of alternating layers of gate layers and graphene sheets, wherein at least one of a source contact and a drain contact corresponding to a selected gate layer is between graphene sheets surrounding the selected gate layer; and electrically coupling the first and second gate layers to each other to form the gate region of the transistor.
(Cu rr ently Amended) The method of claim 8 wherein stacking the plurality of alternating layers of gate contact metal and graphene further comprises further comprising forming [ail the first layer of graphene sheet on a substrate and vertically stacking the plurality of alternating layers of gate contact metal and graphene on top of the first layer of graphene.
(Cu rr ently Amended) The method of claim 8, further comprising stacking a l[the il plurality of alternating layers of gate layers and graphene sheets so that an electric field in a selected graphene sheet is affected by gate layers on opposite sides of the selected graphene sheet.
(Cu rr ently Amended) The method of claim 8, further comprising coupling the layers of graphene to the at least one of the source contact and the drain contact to the first graphene sheet and the second graphene sheet.
The method of claim 8 wherein a selected gate layer includes a gate contact metal sandwiched between dielectric layers.
(Cu rr ently Amended) A method of forming a transistor, comprising: depositing a first gate layer and at least one of a source contact and a drain contact on the top surface of the first graphene sheet; depositing a second graphene sheet on top surfaces of the first gate layer and the at least one of the source contact and the drain contact; forming a second gate layer on a top surface of the second graphene sheet; and stacking a plurality of alternating layers of gate layers and graphene sheets by forming a selected gate layer on a first one of the plurality of graphene sheets, forming at least one of a source contact and a drain contact on the first one of the plurality of graphene sheets, and forming a second one of the plurality of graphene sheets on the gate layer and the at least one of the source contact and the drain contact; and electrically coupling the first and second gate layers to each other.
(Cu rr ently Amended) The method of claim 15 wherein stacking the plurality SVG 13683148.07-28-2014.HY₈I₉SHTPXXIFW1.CLM.1.svg 0.17 5.84 Black and white forming l[all the first layer of graphene sheet on a substrate and vertically stacking the plurality of alternating layers of gate layer and graphene on top of the first layer of graphene.
The method of claim 15 wherein a selected sandwiched between insulator material.
The method of claim 15, wherein a thickness thickness of the at least one of the source contact
The method of claim 15 further comprising a selected state of a transistor parameter. YO 15, further comp ri sing stacking a l[the ll selected graphene sheet is affected by gate layers on gate layer includes a gate contact metal of the gate layer is substantially the same as the and the drain contact selecting a number of alternating layers to obtain R₉₂₀₁₂₀₇₇₁US₁
(Cu rr ently Amended) The method of claim plurality of layers so that an electric field in a opposite sides of the selected graphene sheet.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (single gate layer)
vertically stacked multi-layer graphene field-effect transistor
Materials described outside the worked examples.
graphene
graphene sheet (first)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 shows an exemplary single layer of a gate region of an exemplary graphene field-effect transistor disclosed herein;
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,932,919Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an exemplary single layer of a gate region of an exemplary graphene field-effect transistor disclosed herein;
Figure 2 shows an exemplary graphene field-effect transistor that includes multiple stacked graphene sheets;
Figure 3 shows a first manufacturing stage of an exemplary graphene field-effect transistor in which a sheet of graphene is disposed on a substrate;
Figure 4 shows a second stage of the manufacturing process in which source and drain contacts are formed;
Figure 5 shows a third stage of the manufacturing process in which a dielectric layer is formed on the graphene sheet of
Figure 6 shows a fourth stage of the manufacturing process in which a gate contact metal is formed on the dielectric layer of
Figure 7 shows a f ift h stage of the manufacturing process in which a second dielectric layer is deposited on the gate contact metal of
Figure 8 shows a sixth stage of the manufacturing process in which a second graphene sheet of the graphene field-effect transistor is formed;
Figure 9 shows a flowchart illustrating an exemplary method of forming the graphene field-effect transistor of the present invention; and
Figure 10 shows an exemplary graph illustrating the effect of multiple graphene sheets on various parameters of the exemplary graphene field-effect transistor of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A method of forming a graphene field-effect transistor, comprising: forming a first graphene sheet on a substrate; coupling d epositing a first gate layer on [[toll a top surface of the first graphene sheet, wherein the first gate layer influences to influence an electric field of the first graphene sheet; coupling d epositing at least one of a source contact and a drain contact on l[tol the top surface of the first graphene sheet; and coupling d epositing a second graphene sheet on top surfaces of [[toEl the first gate layer and the at least one of the source contact and the drain contact, wherein the first gate layer influences an electric field of the second graphene sheet.
(Cu rr ently Amended) The method of claim 1, further comprising forming depositing a second gate layer on a top surface of r toll the second graphene sheet and electrically coupling the first gate layer and the second gate layer.
The method of claim 1, wherein the first gate layer further comprises a gate contact metal sandwiched between dielectric layers.
The method of claim 1, wherein a thickness of the gate layer is substantially the same as the thickness of the at least one of the source contact and the drain contact.
The method of claim 1, further comprising stacking alternating layers of graphene sheets and gate layers to obtain a selected state of a parameter of the transistor.
canceled
(Cu rr ently Amended) A method of forming a gate region of a transistor, comprising: depositing a first gate layer and at least one of a source contact and a drain contact on the top surface of the first graphene sheet; depositing a second graphene sheet on top surfaces of the first gate layer and the at least one of the source contact and the drain contact; forming a second gate layer on a top surface of the second graphene sheet; and stacking a plurality of alternating layers of gate layers and graphene sheets, wherein at least one of a source contact and a drain contact corresponding to a selected gate layer is between graphene sheets surrounding the selected gate layer; and electrically coupling the first and second gate layers to each other to form the gate region of the transistor.
(Cu rr ently Amended) The method of claim 8 wherein stacking the plurality of alternating layers of gate contact metal and graphene further comprises further comprising forming [ail the first layer of graphene sheet on a substrate and vertically stacking the plurality of alternating layers of gate contact metal and graphene on top of the first layer of graphene.
(Cu rr ently Amended) The method of claim 8, further comprising stacking a l[the il plurality of alternating layers of gate layers and graphene sheets so that an electric field in a selected graphene sheet is affected by gate layers on opposite sides of the selected graphene sheet.
(Cu rr ently Amended) The method of claim 8, further comprising coupling the layers of graphene to the at least one of the source contact and the drain contact to the first graphene sheet and the second graphene sheet.
The method of claim 8 wherein a selected gate layer includes a gate contact metal sandwiched between dielectric layers.
(Cu rr ently Amended) A method of forming a transistor, comprising: depositing a first gate layer and at least one of a source contact and a drain contact on the top surface of the first graphene sheet; depositing a second graphene sheet on top surfaces of the first gate layer and the at least one of the source contact and the drain contact; forming a second gate layer on a top surface of the second graphene sheet; and stacking a plurality of alternating layers of gate layers and graphene sheets by forming a selected gate layer on a first one of the plurality of graphene sheets, forming at least one of a source contact and a drain contact on the first one of the plurality of graphene sheets, and forming a second one of the plurality of graphene sheets on the gate layer and the at least one of the source contact and the drain contact; and electrically coupling the first and second gate layers to each other.
(Cu rr ently Amended) The method of claim 15 wherein stacking the plurality SVG 13683148.07-28-2014.HY₈I₉SHTPXXIFW1.CLM.1.svg 0.17 5.84 Black and white forming l[all the first layer of graphene sheet on a substrate and vertically stacking the plurality of alternating layers of gate layer and graphene on top of the first layer of graphene.
The method of claim 15 wherein a selected sandwiched between insulator material.
The method of claim 15, wherein a thickness thickness of the at least one of the source contact
The method of claim 15 further comprising a selected state of a transistor parameter. YO 15, further comp ri sing stacking a l[the ll selected graphene sheet is affected by gate layers on gate layer includes a gate contact metal of the gate layer is substantially the same as the and the drain contact selecting a number of alternating layers to obtain R₉₂₀₁₂₀₇₇₁US₁
(Cu rr ently Amended) The method of claim plurality of layers so that an electric field in a opposite sides of the selected graphene sheet.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (single gate layer)
vertically stacked multi-layer graphene field-effect transistor
Materials described outside the worked examples.
graphene
graphene sheet (first)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 shows an exemplary single layer of a gate region of an exemplary graphene field-effect transistor disclosed herein;
Related documents with shared materials, methods, properties, or citations.
dielectric layer
silicon
Si
palladium
Pd
hafnium oxide
HfO₂
alumina
Al₂O₃
PMMA
hydrogen silsesquioxane (HSQ)
trimethylaluminum (TMA)
copper foil
Figure 2 shows an exemplary graphene field-effect transistor that includes multiple stacked graphene sheets;
Figure 3 shows a first manufacturing stage of an exemplary graphene field-effect transistor in which a sheet of graphene is disposed on a substrate;
Figure 8 shows a sixth stage of the manufacturing process in which a second graphene sheet of the graphene field-effect transistor is formed;
Figure 9 shows a flowchart illustrating an exemplary method of forming the graphene field-effect transistor of the present invention; and
Figure 10 shows an exemplary graph illustrating the effect of multiple graphene sheets on various parameters of the exemplary graphene field-effect transistor of the present invention.
Figure 10 shows an exemplary graph illustrating the effect of multiple graphene sheets on various parameters of the exemplary graphene field-effect transistor of the present invention.
dielectric layer
silicon
Si
palladium
Pd
hafnium oxide
HfO₂
alumina
Al₂O₃
PMMA
hydrogen silsesquioxane (HSQ)
trimethylaluminum (TMA)
copper foil
Figure 2 shows an exemplary graphene field-effect transistor that includes multiple stacked graphene sheets;
Figure 3 shows a first manufacturing stage of an exemplary graphene field-effect transistor in which a sheet of graphene is disposed on a substrate;
Figure 8 shows a sixth stage of the manufacturing process in which a second graphene sheet of the graphene field-effect transistor is formed;
Figure 9 shows a flowchart illustrating an exemplary method of forming the graphene field-effect transistor of the present invention; and
Figure 10 shows an exemplary graph illustrating the effect of multiple graphene sheets on various parameters of the exemplary graphene field-effect transistor of the present invention.
Figure 10 shows an exemplary graph illustrating the effect of multiple graphene sheets on various parameters of the exemplary graphene field-effect transistor of the present invention.
dielectric layer
silicon
Si
palladium
Pd
hafnium oxide
HfO₂
alumina
Al₂O₃
PMMA
hydrogen silsesquioxane (HSQ)
trimethylaluminum (TMA)
copper foil
Figure 2 shows an exemplary graphene field-effect transistor that includes multiple stacked graphene sheets;
Figure 3 shows a first manufacturing stage of an exemplary graphene field-effect transistor in which a sheet of graphene is disposed on a substrate;
Figure 8 shows a sixth stage of the manufacturing process in which a second graphene sheet of the graphene field-effect transistor is formed;
Figure 9 shows a flowchart illustrating an exemplary method of forming the graphene field-effect transistor of the present invention; and
Figure 10 shows an exemplary graph illustrating the effect of multiple graphene sheets on various parameters of the exemplary graphene field-effect transistor of the present invention.
Figure 10 shows an exemplary graph illustrating the effect of multiple graphene sheets on various parameters of the exemplary graphene field-effect transistor of the present invention.
dielectric layer
silicon
Si
palladium
Pd
hafnium oxide
HfO₂
alumina
Al₂O₃
PMMA
hydrogen silsesquioxane (HSQ)
trimethylaluminum (TMA)
copper foil
Figure 2 shows an exemplary graphene field-effect transistor that includes multiple stacked graphene sheets;
Figure 3 shows a first manufacturing stage of an exemplary graphene field-effect transistor in which a sheet of graphene is disposed on a substrate;
Figure 8 shows a sixth stage of the manufacturing process in which a second graphene sheet of the graphene field-effect transistor is formed;
Figure 9 shows a flowchart illustrating an exemplary method of forming the graphene field-effect transistor of the present invention; and
Figure 10 shows an exemplary graph illustrating the effect of multiple graphene sheets on various parameters of the exemplary graphene field-effect transistor of the present invention.
Figure 10 shows an exemplary graph illustrating the effect of multiple graphene sheets on various parameters of the exemplary graphene field-effect transistor of the present invention.