SCALABLE GRAPHENE NANORIBBON ARRAYS FOR DIGITAL TRANSISTORS

Mitchell B. Lerner

Patent

Atlas literature

Patent

US 10,490,401

SCALABLE GRAPHENE NANORIBBON ARRAYS FOR DIGITAL TRANSISTORS

Mitchell B. Lerner

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 2

FIG. 3

FIG. 4

FIG. 5

FIG. 6

FIG. 7

FIG. 8

FIG. 9

FIG. 10

FIG. 11

FIG. 12

FIG. 13

FIG. 14

FIG. 15

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

5 independent · 12 dependent

1
IndependentgraphenePMMAinsulatorgraphene nanotransistor
A method for fabricating a graphene nanoribbon array, comprising the steps of: A) selectively seeding the growth of graphene ﬂakes on a substrate, including; Al) depositing PMMA dots on said substrate in an m x n grid, wherein a periodicity of the grid is controlled by an initial spacing of said PMMA dots on said substrate; A₂) depositing said graphene on said PMMA dots and said substrate, wherein a size of said graphene ﬂakes is controlled by controlling a growth time of said graphene ﬂakes on said PMMA dots; B) masking said graphene ﬂake edges with a layer of insulator; C) etching said graphene ﬂakes; D) removing said insulator to expose an m x n array of said graphene nanoribbons, said nanoribbons having a plurality of facets when viewed in top plan; E) etching at least one electrode in each of said facets; and, F) providing a back plane to establish a graphene nanotransistor in each said facet of each said graphene nanoribbon. Previously presented
1. 3
  Dependent← claim 1graphene
  The method of claim 1, wherein said step A₂) is accomplished using a gas selected from the group consisting of Ar, H 2 or CH₄ at about 1050 °C. Previously presented
2. 4
  Dependent← claim 1graphene
  The method of claim 1, wherein said step A₂) is accomplished using a process selected from the group consisting of CVD growth, epitaxial growth or R F inductive growth. Previously presented
3. 5
  Dependent← claim 1Al₂O₃HfO₂
  The method of claim 1, wherein said insulator is selected from the group consisting of A 1 203 or Hf O2. Original
4. 6
  Dependent← claim 1Cu
  The method of claim 1, wherein said substrate is a copper catalyst foil. Original
5. 7
  Dependent← claim 1
  The method of claim 1, where said step C) is accomplished using an oxygen plasma etch at 30 W for 30 seconds. Original
6. 8
  Dependent← claim 1KOH
  The method of claim 1, wherein said step D) is accomplished using KOH. Original
2
Independent
Canceled
9
IndependentgraphenePMMAinsulatorgraphene nanotransistor
A method for manufacturing a graphene nanotransistor grid, said method comprising the steps of: A) seeding the growth of graphene ﬂakes on a substrate in an m x n array, including; Al) depositing PMMA dots on said substrate in an m x n grid, wherein a periodicity of said grid is controlled by an initial spacing of said PMMA dots on said substrate; A₂) depositing said graphene on said PMMA dots and said substrate, wherein a size of said graphene ﬂakes is controlled by controlling a growth time of said graphene ﬂakes on said PMMA dots; B) masking said graphene ﬂake edges with a layer of insulator; C) etching said graphene ﬂakes; D) removing said insulator to expose an m x n array of said graphene nanoribbons, said nanoribbons having a plurality of facets when viewed in top plan; E) etching at least one electrode in each of said facets; and, F) providing a back plane to establish a graphene nanotransistor in each said facet of each said graphene nanoribbon. Previously presented
1. 11
  Dependent← claim 9graphene
  The method of claim 9, wherein said step A₂) is accomplished using a gas selected from the group consisting of Ar, H 2 or CH₄ at about 1050 °C. Previously presented
2. 12
  Dependent← claim 9graphene
  The method of claim 9, wherein said step A₂) is accomplished using a process selected from the group consisting of CVD growth, epitaxial growth or R F inductive growth. Previously presented
3. 13
  Dependent← claim 9Al₂O₃HfO₂
  The method of claim 9, wherein said insulator is selected from the group consisting of A 1 203 or Hf O2. Original
4. 14
  Dependent← claim 9Cu
  The method of claim 9, wherein said substrate is a copper catalyst foil. Original
5. 15
  Dependent← claim 9
  The method of claim 9, where said step C) is accomplished using an oxygen plasma etch at 30 W for 30 seconds. Original
6. 16
  Dependent← claim 9KOH
  The method of claim 9, wherein said step D) is accomplished using KOH. Previously presented
10
Independent
Canceled
17
Independent
Canceled

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

graphene nanotransistor

back_gateback gate

insulatorgate dielectric

graphene nanoribbonchannel

Materials

Materials described outside the worked examples.

graphene

Channel Material

PMMA

Seeding Dot Material

Process steps

Additional fabrication and treatment steps described in the patent.

Cvd Growth

Step 1

Temperature

1050°C

Ambient

Ar/H2/CH4

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
Thickness	2–3 nm	—

Why these are connected

Related documents with shared materials, methods, properties, or citations.

SCALABLE GRAPHENE NANORIBBON ARRAYS FOR DIGITAL TRANSISTORS | Matter42 Literature