Patent
US 12,652,836 B2SCALABLE CIRCUIT-UNDER-PAD DEVICE TOPOLOGIES FOR LATERAL GaN POWER TRANSISTORS
Ahmad Mizan, Hossein Mousavian, Xiaodong Cui
GAN SYSTEMS INC., Ottawa (CA)·Jun. 9, 2026·US
Copyright © 2026 Matter42. All rights reserved.
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US 12,652,836 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 (Prior art) shows an example of a known CUP device topology for one section or cell of a multi-section power transistor, comprising a two-piece pad …
FIG. 2, comprising a plan view of layers of one section of a multi-section power transistor and cross-sectional side views to illustrate source and drain 55 …
FIG. 3 shows a plan view of CUP device topology for one section or cell of a multi-section lateral GaN power transis- tor, comprising a two-piece pad structure …
FIG. 4 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN transistor according to a first embodiment
FIG. 5 shows a plan view of two cells or sections (i, i+1) 65 of a multi-section lateral GaN power transistor based on the topology shown in
FIG. 6A shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a second …
FIG. 7 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fourth …
FIG. 8 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fifth …
FIG. 18 of U.S. Ser. No. 15/704,458). In the embodiments shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device structure comprising: a lateral GaN transistor structure comprising active regions for a plurality of transistor sections of a multisection transistor; each transistor section comprising source, drain and gate electrodes defined on an active region; a level of on-chip metallization defining for each section a contact structure comprising a drain contact area and first and second source contact areas; the drain contact area comprising a drain pad extending over a central part of the active region located between the first and second source contact areas; the drain pad being interconnected by conductive microvias to underlying parts of the drain electrodes and the first and second source contact areas being intercon-nected to the source electrodes; and the first and second source contact areas being first and second parts of a source bus, the first and second parts of the source bus being located each side of the drain pad and the source bus being routed over inactive regions adjacent the active region.
The semiconductor device structure of claim 1, further comprising a gate bus interconnecting gate electrodes of each section, the gate bus being routed over said inactive regions, and the source bus being routed over or under the gate bus. 15 16
A semiconductor device structure comprising: 10 a lateral GaN transistor structure comprising active regions for a plurality of transistor sections of a multisection transistor; each transistor section comprising source, drain and gate electrodes defined on an active region; on-chip metallization defining for each section a contact structure comprising a drain pad a source bus, and a gate bus; the drain pad extending over a central part of the active region, the drain pad being interconnected by conduc-tive micro-vias to underlying parts of the drain elec-trodes; the source bus being routed over inactive regions adjacent the active region, without extending over the active region; the source bus comprising first and second parts each side of the drain pad, the source electrodes being connected to the first and second parts of the source bus; and the gate bus being routed over said inactive regions and interconnecting the gate electrodes; and the source bus overlapping the gate bus, running over or under the gate bus. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN multisection transistor with CUP topology (source bus over inactive regions)
lateral GaN multisection transistor with CUP topology (source bus over inactive regions, overlapping gate bus)
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
GaN/AlGaN heterostructure
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 (Prior art) shows an example of a known CUP device topology for one section or cell of a multi-section power transistor, comprising a two-piece pad …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 38
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,652,836 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 (Prior art) shows an example of a known CUP device topology for one section or cell of a multi-section power transistor, comprising a two-piece pad …
FIG. 2, comprising a plan view of layers of one section of a multi-section power transistor and cross-sectional side views to illustrate source and drain 55 …
FIG. 3 shows a plan view of CUP device topology for one section or cell of a multi-section lateral GaN power transis- tor, comprising a two-piece pad structure …
FIG. 4 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN transistor according to a first embodiment
FIG. 5 shows a plan view of two cells or sections (i, i+1) 65 of a multi-section lateral GaN power transistor based on the topology shown in
FIG. 6A shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a second …
FIG. 7 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fourth …
FIG. 8 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fifth …
FIG. 18 of U.S. Ser. No. 15/704,458). In the embodiments shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device structure comprising: a lateral GaN transistor structure comprising active regions for a plurality of transistor sections of a multisection transistor; each transistor section comprising source, drain and gate electrodes defined on an active region; a level of on-chip metallization defining for each section a contact structure comprising a drain contact area and first and second source contact areas; the drain contact area comprising a drain pad extending over a central part of the active region located between the first and second source contact areas; the drain pad being interconnected by conductive microvias to underlying parts of the drain electrodes and the first and second source contact areas being intercon-nected to the source electrodes; and the first and second source contact areas being first and second parts of a source bus, the first and second parts of the source bus being located each side of the drain pad and the source bus being routed over inactive regions adjacent the active region.
The semiconductor device structure of claim 1, further comprising a gate bus interconnecting gate electrodes of each section, the gate bus being routed over said inactive regions, and the source bus being routed over or under the gate bus. 15 16
A semiconductor device structure comprising: 10 a lateral GaN transistor structure comprising active regions for a plurality of transistor sections of a multisection transistor; each transistor section comprising source, drain and gate electrodes defined on an active region; on-chip metallization defining for each section a contact structure comprising a drain pad a source bus, and a gate bus; the drain pad extending over a central part of the active region, the drain pad being interconnected by conduc-tive micro-vias to underlying parts of the drain elec-trodes; the source bus being routed over inactive regions adjacent the active region, without extending over the active region; the source bus comprising first and second parts each side of the drain pad, the source electrodes being connected to the first and second parts of the source bus; and the gate bus being routed over said inactive regions and interconnecting the gate electrodes; and the source bus overlapping the gate bus, running over or under the gate bus. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN multisection transistor with CUP topology (source bus over inactive regions)
lateral GaN multisection transistor with CUP topology (source bus over inactive regions, overlapping gate bus)
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
GaN/AlGaN heterostructure
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 (Prior art) shows an example of a known CUP device topology for one section or cell of a multi-section power transistor, comprising a two-piece pad …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 38
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,652,836 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 (Prior art) shows an example of a known CUP device topology for one section or cell of a multi-section power transistor, comprising a two-piece pad …
FIG. 2, comprising a plan view of layers of one section of a multi-section power transistor and cross-sectional side views to illustrate source and drain 55 …
FIG. 3 shows a plan view of CUP device topology for one section or cell of a multi-section lateral GaN power transis- tor, comprising a two-piece pad structure …
FIG. 4 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN transistor according to a first embodiment
FIG. 5 shows a plan view of two cells or sections (i, i+1) 65 of a multi-section lateral GaN power transistor based on the topology shown in
FIG. 6A shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a second …
FIG. 7 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fourth …
FIG. 8 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fifth …
FIG. 18 of U.S. Ser. No. 15/704,458). In the embodiments shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device structure comprising: a lateral GaN transistor structure comprising active regions for a plurality of transistor sections of a multisection transistor; each transistor section comprising source, drain and gate electrodes defined on an active region; a level of on-chip metallization defining for each section a contact structure comprising a drain contact area and first and second source contact areas; the drain contact area comprising a drain pad extending over a central part of the active region located between the first and second source contact areas; the drain pad being interconnected by conductive microvias to underlying parts of the drain electrodes and the first and second source contact areas being intercon-nected to the source electrodes; and the first and second source contact areas being first and second parts of a source bus, the first and second parts of the source bus being located each side of the drain pad and the source bus being routed over inactive regions adjacent the active region.
The semiconductor device structure of claim 1, further comprising a gate bus interconnecting gate electrodes of each section, the gate bus being routed over said inactive regions, and the source bus being routed over or under the gate bus. 15 16
A semiconductor device structure comprising: 10 a lateral GaN transistor structure comprising active regions for a plurality of transistor sections of a multisection transistor; each transistor section comprising source, drain and gate electrodes defined on an active region; on-chip metallization defining for each section a contact structure comprising a drain pad a source bus, and a gate bus; the drain pad extending over a central part of the active region, the drain pad being interconnected by conduc-tive micro-vias to underlying parts of the drain elec-trodes; the source bus being routed over inactive regions adjacent the active region, without extending over the active region; the source bus comprising first and second parts each side of the drain pad, the source electrodes being connected to the first and second parts of the source bus; and the gate bus being routed over said inactive regions and interconnecting the gate electrodes; and the source bus overlapping the gate bus, running over or under the gate bus. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN multisection transistor with CUP topology (source bus over inactive regions)
lateral GaN multisection transistor with CUP topology (source bus over inactive regions, overlapping gate bus)
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
GaN/AlGaN heterostructure
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 (Prior art) shows an example of a known CUP device topology for one section or cell of a multi-section power transistor, comprising a two-piece pad …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 38
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,652,836 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 (Prior art) shows an example of a known CUP device topology for one section or cell of a multi-section power transistor, comprising a two-piece pad …
FIG. 2, comprising a plan view of layers of one section of a multi-section power transistor and cross-sectional side views to illustrate source and drain 55 …
FIG. 3 shows a plan view of CUP device topology for one section or cell of a multi-section lateral GaN power transis- tor, comprising a two-piece pad structure …
FIG. 4 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN transistor according to a first embodiment
FIG. 5 shows a plan view of two cells or sections (i, i+1) 65 of a multi-section lateral GaN power transistor based on the topology shown in
FIG. 6A shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a second …
FIG. 7 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fourth …
FIG. 8 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fifth …
FIG. 18 of U.S. Ser. No. 15/704,458). In the embodiments shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device structure comprising: a lateral GaN transistor structure comprising active regions for a plurality of transistor sections of a multisection transistor; each transistor section comprising source, drain and gate electrodes defined on an active region; a level of on-chip metallization defining for each section a contact structure comprising a drain contact area and first and second source contact areas; the drain contact area comprising a drain pad extending over a central part of the active region located between the first and second source contact areas; the drain pad being interconnected by conductive microvias to underlying parts of the drain electrodes and the first and second source contact areas being intercon-nected to the source electrodes; and the first and second source contact areas being first and second parts of a source bus, the first and second parts of the source bus being located each side of the drain pad and the source bus being routed over inactive regions adjacent the active region.
The semiconductor device structure of claim 1, further comprising a gate bus interconnecting gate electrodes of each section, the gate bus being routed over said inactive regions, and the source bus being routed over or under the gate bus. 15 16
A semiconductor device structure comprising: 10 a lateral GaN transistor structure comprising active regions for a plurality of transistor sections of a multisection transistor; each transistor section comprising source, drain and gate electrodes defined on an active region; on-chip metallization defining for each section a contact structure comprising a drain pad a source bus, and a gate bus; the drain pad extending over a central part of the active region, the drain pad being interconnected by conduc-tive micro-vias to underlying parts of the drain elec-trodes; the source bus being routed over inactive regions adjacent the active region, without extending over the active region; the source bus comprising first and second parts each side of the drain pad, the source electrodes being connected to the first and second parts of the source bus; and the gate bus being routed over said inactive regions and interconnecting the gate electrodes; and the source bus overlapping the gate bus, running over or under the gate bus. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN multisection transistor with CUP topology (source bus over inactive regions)
lateral GaN multisection transistor with CUP topology (source bus over inactive regions, overlapping gate bus)
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
GaN/AlGaN heterostructure
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 (Prior art) shows an example of a known CUP device topology for one section or cell of a multi-section power transistor, comprising a two-piece pad …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 38
Related documents with shared materials, methods, properties, or citations.
lateral GaN E-HEMT multisection transistor with CUP topology (described embodiment with GaN/AlGaN heterostructure)
FIG. 2, comprising a plan view of layers of one section of a multi-section power transistor and cross-sectional side views to illustrate source and drain 55 …
FIG. 4 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN transistor according to a first embodiment
FIG. 5 shows a plan view of two cells or sections (i, i+1) 65 of a multi-section lateral GaN power transistor based on the topology shown in
FIG. 6A shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a second …
FIG. 7 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fourth …
FIG. 8 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fifth …
lateral GaN E-HEMT multisection transistor with CUP topology (described embodiment with GaN/AlGaN heterostructure)
FIG. 2, comprising a plan view of layers of one section of a multi-section power transistor and cross-sectional side views to illustrate source and drain 55 …
FIG. 4 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN transistor according to a first embodiment
FIG. 5 shows a plan view of two cells or sections (i, i+1) 65 of a multi-section lateral GaN power transistor based on the topology shown in
FIG. 6A shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a second …
FIG. 7 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fourth …
FIG. 8 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fifth …
lateral GaN E-HEMT multisection transistor with CUP topology (described embodiment with GaN/AlGaN heterostructure)
FIG. 2, comprising a plan view of layers of one section of a multi-section power transistor and cross-sectional side views to illustrate source and drain 55 …
FIG. 4 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN transistor according to a first embodiment
FIG. 5 shows a plan view of two cells or sections (i, i+1) 65 of a multi-section lateral GaN power transistor based on the topology shown in
FIG. 6A shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a second …
FIG. 7 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fourth …
FIG. 8 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fifth …
lateral GaN E-HEMT multisection transistor with CUP topology (described embodiment with GaN/AlGaN heterostructure)
FIG. 2, comprising a plan view of layers of one section of a multi-section power transistor and cross-sectional side views to illustrate source and drain 55 …
FIG. 4 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN transistor according to a first embodiment
FIG. 5 shows a plan view of two cells or sections (i, i+1) 65 of a multi-section lateral GaN power transistor based on the topology shown in
FIG. 6A shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a second …
FIG. 7 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fourth …
FIG. 8 shows a plan view of a GaN-on-silicon device structure comprising one section of a multi-section lateral GaN power transistor according to a fifth …