Patent
US 8,593,211SYSTEM AND APPARATUS FOR DRIVER CIRCUIT FOR PROTECTION OF GATES OF GAN FETS
Hassan Pooya Forghani-Zadeh
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,593,211Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a prior art half bridge power stage that employs both a low side MOSFET and a high side GaN FET; [0013]
FIG. 2 illustrates a prior art GaN FET driver system that employs transformers; [0014]
FIG. 3 illustrates an example of a half bridge power stage that employs both low side and high side GaN FETs with driver circuitry constructed according to …
FIG. 4 is an example of a bootstrap capacitor clamp (BCC) controller for a GaN FET, such as employable with the half bridge power amplifier of
FIG. 5 is an illustration of a transient input voltage, and various resulting voltages across at different nodes of the half- bridge power stage that employs …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. An apparatus, comprising: a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of [[the]] a driver and a source of the first GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode; and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor (Boot); and d) a signal representative of a Voltage at the source of the first GaN FET, wherein the BCC controller is configured to compare: a) a difference of: i) the VDRV and the GND, to generate a first comparison signal, to b) a difference of ii) the Boot and the source of the GaN FET, to generate a second comparison signal; 2 ATTORNEY DOCKET NO. PATENT APPLICATION TI-71442 SERIAL NO. 13/422,132 wherein the BCC controller is further configured to maintain a relationship between the first comparison signal and the second comparison signal base on the comparison, and wherein the BCC controller is further configured to drive a gate output signal to the first GaN FET to maintain this relationship.
The apparatus of Claim 1, wherein the drain of the FET is coupled to the anode of the diode.
The apparatus of Claim 1, wherein the GaN FET, further comprising a drain of a second GaN FET coupled to a source of the first GaN FET, and the first GaN FET is a high side GaN FET, and the second GaN FET is a low side GaN FET.
The apparatus of Claim 1, wherein the relationship is a substantially equal voltage drop comparison between: i) the VDRV and the GND, and ii) ii) the Boot and the source of the GaN FET.
The apparatus of Claim 1, wherein the driver is a first driver, and a deadtime control is coupled to an input of the first driver and a second driver, wherein the second driver is also coupled to a gate of a second GaN FET, the second GaN FET coupled to the source of the first GaN FET.
The apparatus of Claim 1, further comprising an upper driver rail of the first driver coupled to a cathode of the capacitor; and a lower rail of the first driver coupled to the source of the GaN FET.
A system, comprising: a) a GaN FET; b) a bootstrap capacitor clamp (BCC) controller coupled to a gate of the GaN FET, the BCC controller comprising: a comparator; a FET, a gate of which is coupled to an output of the comparator; a first isolation switch coupled to a positive input of the comparator, a drain of the first isolation switch coupled between a first resistor and a second resistor, wherein the first resistor is also coupled to an anode of a capacitor, and wherein the second resistor is coupled to a ground; a second isolation switch coupled to a negative input of the comparator, a drain of the second isolation switch coupled between a third resistor and a fourth resistor, wherein the third resistor is also coupled to a signal representative of a signal voltage (VDRV) and wherein the fourth resistor is also coupled to a source of the GaN FET.
The system of Claim 9, further comprising a diode coupled between the BCC controller and a gate of the GaN FET.
The system of Claim 9, wherein driving the FET off by the comparator allows a voltage across [[a]] th boot capacitor to float, thereby not overdriving a difference between a gate and a source of the GaN FET.
The system of Claim 9, wherein the BCC controller is configured to keep a voltage difference between a first input voltage of the amplifier and a second input of [[the]] a n amplifier substantially constant.
The system of Claim [[11]] 9, wherein the first isolation switch and [[a]] t he second isolation switch are enabled when receiving a low side GaN FET on (LSON) signal.
The system of Claim 10, wherein the comparator turns on the FET [[if]] when a difference between the Boot and GND voltage is greater than that of a difference between a VDRV and SW voltage.
A system, comprising: a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of [[the]] a driver and a source of the GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode; and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the source of the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor; and d) a signal representative of a voltage at the source of the first GaN FET, wherein the bootstrap capacitor clamp is configured to compare: a) a difference of:i) the VDRV and the GND to generate a first comparison signal; to b) a difference of ii) the Boot and the SW to generate a second comparison signal; wherein the BCC controller is configured to maintain a relationship between the first comparison signal and the second comparison signal base on the comparison, and wherein the BCC controller is further configured to drive a gate output signal to the a drain of a second GaN FET coupled to a source of the first GaN FET; an inductor coupled to a source of the first GaN FET; and 7 ATTORNEY DOCKET NO. PATENT APPLICATION TI-71442 SERIAL NO. 13/422,132 a drain of a second GaN FET coupled to a source of the first GaN FET.
The system of Claim 17, wherein the BCC controller further comp ri ses: SVG 13422132.07-02-2013.HINLP₉₄NPXXIFW3.CLM.1.svg 0.14 0.93 Black and white a FET, a gate of which is coupled to an output of the comparator; a first isolation switch coupled to a positive input of the comparator, a drain of the first isolation switch coupled between a first resistor and a second resistor, wherein the first resistor is also coupled to an anode of [[a]] t he capacitor, and wherein the second resistor is coupled to a ground; a second isolation switch coupled to a negative input of the comparator, a drain of the second isolation switch coupled between a third resistor and a fourth resistor, wherein the third resistor is also coupled to a signal representative of a signal voltage (VDRV) and wherein the fourth resistor is also coupled to a source of the GaN FET.
The system of Claim 23, wherein said system is embodied upon an integrated circuit. 9
Layer stacks claimed or described, ordered top of device to substrate.
Half-bridge apparatus with GaN FETs and BCC controller
GaN FET system with BCC controller (resistor-divider comparator topology)
Half-bridge system with dual GaN FETs and BCC controller
Materials described outside the worked examples.
Gallium Nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a prior art half bridge power stage that employs both a low side MOSFET and a high side GaN FET; [0013]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 50–600 V | — |
Voltage | 60–100 V |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,593,211Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a prior art half bridge power stage that employs both a low side MOSFET and a high side GaN FET; [0013]
FIG. 2 illustrates a prior art GaN FET driver system that employs transformers; [0014]
FIG. 3 illustrates an example of a half bridge power stage that employs both low side and high side GaN FETs with driver circuitry constructed according to …
FIG. 4 is an example of a bootstrap capacitor clamp (BCC) controller for a GaN FET, such as employable with the half bridge power amplifier of
FIG. 5 is an illustration of a transient input voltage, and various resulting voltages across at different nodes of the half- bridge power stage that employs …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. An apparatus, comprising: a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of [[the]] a driver and a source of the first GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode; and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor (Boot); and d) a signal representative of a Voltage at the source of the first GaN FET, wherein the BCC controller is configured to compare: a) a difference of: i) the VDRV and the GND, to generate a first comparison signal, to b) a difference of ii) the Boot and the source of the GaN FET, to generate a second comparison signal; 2 ATTORNEY DOCKET NO. PATENT APPLICATION TI-71442 SERIAL NO. 13/422,132 wherein the BCC controller is further configured to maintain a relationship between the first comparison signal and the second comparison signal base on the comparison, and wherein the BCC controller is further configured to drive a gate output signal to the first GaN FET to maintain this relationship.
The apparatus of Claim 1, wherein the drain of the FET is coupled to the anode of the diode.
The apparatus of Claim 1, wherein the GaN FET, further comprising a drain of a second GaN FET coupled to a source of the first GaN FET, and the first GaN FET is a high side GaN FET, and the second GaN FET is a low side GaN FET.
The apparatus of Claim 1, wherein the relationship is a substantially equal voltage drop comparison between: i) the VDRV and the GND, and ii) ii) the Boot and the source of the GaN FET.
The apparatus of Claim 1, wherein the driver is a first driver, and a deadtime control is coupled to an input of the first driver and a second driver, wherein the second driver is also coupled to a gate of a second GaN FET, the second GaN FET coupled to the source of the first GaN FET.
The apparatus of Claim 1, further comprising an upper driver rail of the first driver coupled to a cathode of the capacitor; and a lower rail of the first driver coupled to the source of the GaN FET.
A system, comprising: a) a GaN FET; b) a bootstrap capacitor clamp (BCC) controller coupled to a gate of the GaN FET, the BCC controller comprising: a comparator; a FET, a gate of which is coupled to an output of the comparator; a first isolation switch coupled to a positive input of the comparator, a drain of the first isolation switch coupled between a first resistor and a second resistor, wherein the first resistor is also coupled to an anode of a capacitor, and wherein the second resistor is coupled to a ground; a second isolation switch coupled to a negative input of the comparator, a drain of the second isolation switch coupled between a third resistor and a fourth resistor, wherein the third resistor is also coupled to a signal representative of a signal voltage (VDRV) and wherein the fourth resistor is also coupled to a source of the GaN FET.
The system of Claim 9, further comprising a diode coupled between the BCC controller and a gate of the GaN FET.
The system of Claim 9, wherein driving the FET off by the comparator allows a voltage across [[a]] th boot capacitor to float, thereby not overdriving a difference between a gate and a source of the GaN FET.
The system of Claim 9, wherein the BCC controller is configured to keep a voltage difference between a first input voltage of the amplifier and a second input of [[the]] a n amplifier substantially constant.
The system of Claim [[11]] 9, wherein the first isolation switch and [[a]] t he second isolation switch are enabled when receiving a low side GaN FET on (LSON) signal.
The system of Claim 10, wherein the comparator turns on the FET [[if]] when a difference between the Boot and GND voltage is greater than that of a difference between a VDRV and SW voltage.
A system, comprising: a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of [[the]] a driver and a source of the GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode; and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the source of the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor; and d) a signal representative of a voltage at the source of the first GaN FET, wherein the bootstrap capacitor clamp is configured to compare: a) a difference of:i) the VDRV and the GND to generate a first comparison signal; to b) a difference of ii) the Boot and the SW to generate a second comparison signal; wherein the BCC controller is configured to maintain a relationship between the first comparison signal and the second comparison signal base on the comparison, and wherein the BCC controller is further configured to drive a gate output signal to the a drain of a second GaN FET coupled to a source of the first GaN FET; an inductor coupled to a source of the first GaN FET; and 7 ATTORNEY DOCKET NO. PATENT APPLICATION TI-71442 SERIAL NO. 13/422,132 a drain of a second GaN FET coupled to a source of the first GaN FET.
The system of Claim 17, wherein the BCC controller further comp ri ses: SVG 13422132.07-02-2013.HINLP₉₄NPXXIFW3.CLM.1.svg 0.14 0.93 Black and white a FET, a gate of which is coupled to an output of the comparator; a first isolation switch coupled to a positive input of the comparator, a drain of the first isolation switch coupled between a first resistor and a second resistor, wherein the first resistor is also coupled to an anode of [[a]] t he capacitor, and wherein the second resistor is coupled to a ground; a second isolation switch coupled to a negative input of the comparator, a drain of the second isolation switch coupled between a third resistor and a fourth resistor, wherein the third resistor is also coupled to a signal representative of a signal voltage (VDRV) and wherein the fourth resistor is also coupled to a source of the GaN FET.
The system of Claim 23, wherein said system is embodied upon an integrated circuit. 9
Layer stacks claimed or described, ordered top of device to substrate.
Half-bridge apparatus with GaN FETs and BCC controller
GaN FET system with BCC controller (resistor-divider comparator topology)
Half-bridge system with dual GaN FETs and BCC controller
Materials described outside the worked examples.
Gallium Nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a prior art half bridge power stage that employs both a low side MOSFET and a high side GaN FET; [0013]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 50–600 V | — |
Voltage | 60–100 V |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,593,211Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a prior art half bridge power stage that employs both a low side MOSFET and a high side GaN FET; [0013]
FIG. 2 illustrates a prior art GaN FET driver system that employs transformers; [0014]
FIG. 3 illustrates an example of a half bridge power stage that employs both low side and high side GaN FETs with driver circuitry constructed according to …
FIG. 4 is an example of a bootstrap capacitor clamp (BCC) controller for a GaN FET, such as employable with the half bridge power amplifier of
FIG. 5 is an illustration of a transient input voltage, and various resulting voltages across at different nodes of the half- bridge power stage that employs …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. An apparatus, comprising: a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of [[the]] a driver and a source of the first GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode; and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor (Boot); and d) a signal representative of a Voltage at the source of the first GaN FET, wherein the BCC controller is configured to compare: a) a difference of: i) the VDRV and the GND, to generate a first comparison signal, to b) a difference of ii) the Boot and the source of the GaN FET, to generate a second comparison signal; 2 ATTORNEY DOCKET NO. PATENT APPLICATION TI-71442 SERIAL NO. 13/422,132 wherein the BCC controller is further configured to maintain a relationship between the first comparison signal and the second comparison signal base on the comparison, and wherein the BCC controller is further configured to drive a gate output signal to the first GaN FET to maintain this relationship.
The apparatus of Claim 1, wherein the drain of the FET is coupled to the anode of the diode.
The apparatus of Claim 1, wherein the GaN FET, further comprising a drain of a second GaN FET coupled to a source of the first GaN FET, and the first GaN FET is a high side GaN FET, and the second GaN FET is a low side GaN FET.
The apparatus of Claim 1, wherein the relationship is a substantially equal voltage drop comparison between: i) the VDRV and the GND, and ii) ii) the Boot and the source of the GaN FET.
The apparatus of Claim 1, wherein the driver is a first driver, and a deadtime control is coupled to an input of the first driver and a second driver, wherein the second driver is also coupled to a gate of a second GaN FET, the second GaN FET coupled to the source of the first GaN FET.
The apparatus of Claim 1, further comprising an upper driver rail of the first driver coupled to a cathode of the capacitor; and a lower rail of the first driver coupled to the source of the GaN FET.
A system, comprising: a) a GaN FET; b) a bootstrap capacitor clamp (BCC) controller coupled to a gate of the GaN FET, the BCC controller comprising: a comparator; a FET, a gate of which is coupled to an output of the comparator; a first isolation switch coupled to a positive input of the comparator, a drain of the first isolation switch coupled between a first resistor and a second resistor, wherein the first resistor is also coupled to an anode of a capacitor, and wherein the second resistor is coupled to a ground; a second isolation switch coupled to a negative input of the comparator, a drain of the second isolation switch coupled between a third resistor and a fourth resistor, wherein the third resistor is also coupled to a signal representative of a signal voltage (VDRV) and wherein the fourth resistor is also coupled to a source of the GaN FET.
The system of Claim 9, further comprising a diode coupled between the BCC controller and a gate of the GaN FET.
The system of Claim 9, wherein driving the FET off by the comparator allows a voltage across [[a]] th boot capacitor to float, thereby not overdriving a difference between a gate and a source of the GaN FET.
The system of Claim 9, wherein the BCC controller is configured to keep a voltage difference between a first input voltage of the amplifier and a second input of [[the]] a n amplifier substantially constant.
The system of Claim [[11]] 9, wherein the first isolation switch and [[a]] t he second isolation switch are enabled when receiving a low side GaN FET on (LSON) signal.
The system of Claim 10, wherein the comparator turns on the FET [[if]] when a difference between the Boot and GND voltage is greater than that of a difference between a VDRV and SW voltage.
A system, comprising: a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of [[the]] a driver and a source of the GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode; and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the source of the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor; and d) a signal representative of a voltage at the source of the first GaN FET, wherein the bootstrap capacitor clamp is configured to compare: a) a difference of:i) the VDRV and the GND to generate a first comparison signal; to b) a difference of ii) the Boot and the SW to generate a second comparison signal; wherein the BCC controller is configured to maintain a relationship between the first comparison signal and the second comparison signal base on the comparison, and wherein the BCC controller is further configured to drive a gate output signal to the a drain of a second GaN FET coupled to a source of the first GaN FET; an inductor coupled to a source of the first GaN FET; and 7 ATTORNEY DOCKET NO. PATENT APPLICATION TI-71442 SERIAL NO. 13/422,132 a drain of a second GaN FET coupled to a source of the first GaN FET.
The system of Claim 17, wherein the BCC controller further comp ri ses: SVG 13422132.07-02-2013.HINLP₉₄NPXXIFW3.CLM.1.svg 0.14 0.93 Black and white a FET, a gate of which is coupled to an output of the comparator; a first isolation switch coupled to a positive input of the comparator, a drain of the first isolation switch coupled between a first resistor and a second resistor, wherein the first resistor is also coupled to an anode of [[a]] t he capacitor, and wherein the second resistor is coupled to a ground; a second isolation switch coupled to a negative input of the comparator, a drain of the second isolation switch coupled between a third resistor and a fourth resistor, wherein the third resistor is also coupled to a signal representative of a signal voltage (VDRV) and wherein the fourth resistor is also coupled to a source of the GaN FET.
The system of Claim 23, wherein said system is embodied upon an integrated circuit. 9
Layer stacks claimed or described, ordered top of device to substrate.
Half-bridge apparatus with GaN FETs and BCC controller
GaN FET system with BCC controller (resistor-divider comparator topology)
Half-bridge system with dual GaN FETs and BCC controller
Materials described outside the worked examples.
Gallium Nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a prior art half bridge power stage that employs both a low side MOSFET and a high side GaN FET; [0013]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 50–600 V | — |
Voltage | 60–100 V |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,593,211Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a prior art half bridge power stage that employs both a low side MOSFET and a high side GaN FET; [0013]
FIG. 2 illustrates a prior art GaN FET driver system that employs transformers; [0014]
FIG. 3 illustrates an example of a half bridge power stage that employs both low side and high side GaN FETs with driver circuitry constructed according to …
FIG. 4 is an example of a bootstrap capacitor clamp (BCC) controller for a GaN FET, such as employable with the half bridge power amplifier of
FIG. 5 is an illustration of a transient input voltage, and various resulting voltages across at different nodes of the half- bridge power stage that employs …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. An apparatus, comprising: a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of [[the]] a driver and a source of the first GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode; and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor (Boot); and d) a signal representative of a Voltage at the source of the first GaN FET, wherein the BCC controller is configured to compare: a) a difference of: i) the VDRV and the GND, to generate a first comparison signal, to b) a difference of ii) the Boot and the source of the GaN FET, to generate a second comparison signal; 2 ATTORNEY DOCKET NO. PATENT APPLICATION TI-71442 SERIAL NO. 13/422,132 wherein the BCC controller is further configured to maintain a relationship between the first comparison signal and the second comparison signal base on the comparison, and wherein the BCC controller is further configured to drive a gate output signal to the first GaN FET to maintain this relationship.
The apparatus of Claim 1, wherein the drain of the FET is coupled to the anode of the diode.
The apparatus of Claim 1, wherein the GaN FET, further comprising a drain of a second GaN FET coupled to a source of the first GaN FET, and the first GaN FET is a high side GaN FET, and the second GaN FET is a low side GaN FET.
The apparatus of Claim 1, wherein the relationship is a substantially equal voltage drop comparison between: i) the VDRV and the GND, and ii) ii) the Boot and the source of the GaN FET.
The apparatus of Claim 1, wherein the driver is a first driver, and a deadtime control is coupled to an input of the first driver and a second driver, wherein the second driver is also coupled to a gate of a second GaN FET, the second GaN FET coupled to the source of the first GaN FET.
The apparatus of Claim 1, further comprising an upper driver rail of the first driver coupled to a cathode of the capacitor; and a lower rail of the first driver coupled to the source of the GaN FET.
A system, comprising: a) a GaN FET; b) a bootstrap capacitor clamp (BCC) controller coupled to a gate of the GaN FET, the BCC controller comprising: a comparator; a FET, a gate of which is coupled to an output of the comparator; a first isolation switch coupled to a positive input of the comparator, a drain of the first isolation switch coupled between a first resistor and a second resistor, wherein the first resistor is also coupled to an anode of a capacitor, and wherein the second resistor is coupled to a ground; a second isolation switch coupled to a negative input of the comparator, a drain of the second isolation switch coupled between a third resistor and a fourth resistor, wherein the third resistor is also coupled to a signal representative of a signal voltage (VDRV) and wherein the fourth resistor is also coupled to a source of the GaN FET.
The system of Claim 9, further comprising a diode coupled between the BCC controller and a gate of the GaN FET.
The system of Claim 9, wherein driving the FET off by the comparator allows a voltage across [[a]] th boot capacitor to float, thereby not overdriving a difference between a gate and a source of the GaN FET.
The system of Claim 9, wherein the BCC controller is configured to keep a voltage difference between a first input voltage of the amplifier and a second input of [[the]] a n amplifier substantially constant.
The system of Claim [[11]] 9, wherein the first isolation switch and [[a]] t he second isolation switch are enabled when receiving a low side GaN FET on (LSON) signal.
The system of Claim 10, wherein the comparator turns on the FET [[if]] when a difference between the Boot and GND voltage is greater than that of a difference between a VDRV and SW voltage.
A system, comprising: a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of [[the]] a driver and a source of the GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode; and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the source of the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor; and d) a signal representative of a voltage at the source of the first GaN FET, wherein the bootstrap capacitor clamp is configured to compare: a) a difference of:i) the VDRV and the GND to generate a first comparison signal; to b) a difference of ii) the Boot and the SW to generate a second comparison signal; wherein the BCC controller is configured to maintain a relationship between the first comparison signal and the second comparison signal base on the comparison, and wherein the BCC controller is further configured to drive a gate output signal to the a drain of a second GaN FET coupled to a source of the first GaN FET; an inductor coupled to a source of the first GaN FET; and 7 ATTORNEY DOCKET NO. PATENT APPLICATION TI-71442 SERIAL NO. 13/422,132 a drain of a second GaN FET coupled to a source of the first GaN FET.
The system of Claim 17, wherein the BCC controller further comp ri ses: SVG 13422132.07-02-2013.HINLP₉₄NPXXIFW3.CLM.1.svg 0.14 0.93 Black and white a FET, a gate of which is coupled to an output of the comparator; a first isolation switch coupled to a positive input of the comparator, a drain of the first isolation switch coupled between a first resistor and a second resistor, wherein the first resistor is also coupled to an anode of [[a]] t he capacitor, and wherein the second resistor is coupled to a ground; a second isolation switch coupled to a negative input of the comparator, a drain of the second isolation switch coupled between a third resistor and a fourth resistor, wherein the third resistor is also coupled to a signal representative of a signal voltage (VDRV) and wherein the fourth resistor is also coupled to a source of the GaN FET.
The system of Claim 23, wherein said system is embodied upon an integrated circuit. 9
Layer stacks claimed or described, ordered top of device to substrate.
Half-bridge apparatus with GaN FETs and BCC controller
GaN FET system with BCC controller (resistor-divider comparator topology)
Half-bridge system with dual GaN FETs and BCC controller
Materials described outside the worked examples.
Gallium Nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a prior art half bridge power stage that employs both a low side MOSFET and a high side GaN FET; [0013]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 50–600 V | — |
Voltage | 60–100 V |
Related documents with shared materials, methods, properties, or citations.
FIG. 2 illustrates a prior art GaN FET driver system that employs transformers; [0014]
FIG. 3 illustrates an example of a half bridge power stage that employs both low side and high side GaN FETs with driver circuitry constructed according to …
FIG. 4 is an example of a bootstrap capacitor clamp (BCC) controller for a GaN FET, such as employable with the half bridge power amplifier of
FIG. 5 is an illustration of a transient input voltage, and various resulting voltages across at different nodes of the half- bridge power stage that employs …
| — |
Voltage | 5–10 V | — |
FIG. 2 illustrates a prior art GaN FET driver system that employs transformers; [0014]
FIG. 3 illustrates an example of a half bridge power stage that employs both low side and high side GaN FETs with driver circuitry constructed according to …
FIG. 4 is an example of a bootstrap capacitor clamp (BCC) controller for a GaN FET, such as employable with the half bridge power amplifier of
FIG. 5 is an illustration of a transient input voltage, and various resulting voltages across at different nodes of the half- bridge power stage that employs …
| — |
Voltage | 5–10 V | — |
FIG. 2 illustrates a prior art GaN FET driver system that employs transformers; [0014]
FIG. 3 illustrates an example of a half bridge power stage that employs both low side and high side GaN FETs with driver circuitry constructed according to …
FIG. 4 is an example of a bootstrap capacitor clamp (BCC) controller for a GaN FET, such as employable with the half bridge power amplifier of
FIG. 5 is an illustration of a transient input voltage, and various resulting voltages across at different nodes of the half- bridge power stage that employs …
| — |
Voltage | 5–10 V | — |
FIG. 2 illustrates a prior art GaN FET driver system that employs transformers; [0014]
FIG. 3 illustrates an example of a half bridge power stage that employs both low side and high side GaN FETs with driver circuitry constructed according to …
FIG. 4 is an example of a bootstrap capacitor clamp (BCC) controller for a GaN FET, such as employable with the half bridge power amplifier of
FIG. 5 is an illustration of a transient input voltage, and various resulting voltages across at different nodes of the half- bridge power stage that employs …
| — |
Voltage | 5–10 V | — |