Patent
US 10,784,794G aN FET GATE DRIVER FOR SELF-OSCILLATING CONVERTERS Inventor:
Michael A. de Rooij
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
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US 10,784,794Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Power converter circuit 100 includes power converter 10, which supplies a rectified voltage V rec t to the load. Power converter 10 is a full bridge …
FIG. 2 is that it is unsuitable for full implementation of the circuit with GaN FETs because of the potential for an over-voltage condition on the voltage …
FIG. 3 shows the gate-to-source voltage of voltage sense FETs 26, 27 in waveforms 260, 270, respectively. As can be seen in these wavefor m s, the …
FIG. 4) for implementing the synchronous modulation. Current mirror circuit 324 is identical to current mirror circuit 325, but is a mirror image. Current …
FIG. 5 shows an exemplary current mirror, according to one embodiment. [0014]
FIG. 6 shows wave fo rms associated with a power converter circuit according to embodiments disclosed herein. [0015]
FIG. 7 in that it includes inductors 546, 547 coupled in series between the AC voltage source 502 and power F ETs 502, 503, and, shunt capacitors 503, 504 …
FIG. 8 shows a power converter circuit according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION [0017]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power converter circuit comprising: a power convert e r comprising first and second power FETs having respective gates receiving respective alternating and opposite voltage waveforms such that the first and second power FETs conduct oppositely to each other; first and second turn-off FETs having: (i) respective drains connected to the gates of the first and second power FETs; (ii) respective sources connected to ground; and (iii) respective gates connected to the gates of opposite ones of the first and power FETs, to prevent spurious turn on of the first and second power FETs during periods in which the opposite first and second power FETs is turned on; and first and second voltage sense FETs having respective sources connected to the respective drains of the first and second turn-off FETs and to the respective gates of the first and second power FETs to limit the voltage applied to the respective gates of the first and second power FETs, the first and second voltage sense FETs having respective gates synchronously modulated with the first and second power FETs to SVG 16114718.08-28-2018.JLE₃MB₅WRXEAPX3.CLM.1.svg 0.16 5.42 Black and white turn-off FET is on and the corresponding power FET is off.
The power converter circuit of claim 1, wherein the first and second power FETs are GaN F ETs.
The power converter circuit of claim 1, wherein the first and second turn-off FETs are GaN FETs.
The power converter circuit of claim 1, wherein the first and second voltage sense FETs are GaN FETs.
The power converter circuit of claim 1, wherein the power converter is implemented in a cu rr ent-mode class D configuration.
The pow e r converter circuit of claim 1, wherein the power converter is implemented in a class E configuration.
The power converter circuit of claim 1, further comprising first and second current mirror circuits connected to the gates of the first and second current sense FETs for synchronously modulating each of th e f irst and second voltage sense FETs with the corresponding power FET to limit the gate to source voltage of the voltage sense FET when the corresponding turn-off F ET is on and the corresponding power FET is off.
The power converter circuit of claim 1, further comprising first and second voltage clamps coupled to the gates o f the first and second power FETs, respectively.
The power converter circuit of claim 1, further comprising f irst and second gate resistors coupled to the gates of the first and second power FETs, respectively, to maintain the respective first and second power FETs at zero volts in an off state.
Layer stacks claimed or described, ordered top of device to substrate.
GaN FET gate driver power converter circuit
No layer stack recorded.
Current-mode class D power converter circuit
No layer stack recorded.
Class E power converter circuit
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. Power converter circuit 100 includes power converter 10, which supplies a rectified voltage V rec t to the load. Power converter 10 is a full bridge …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≤ 5 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,784,794Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Power converter circuit 100 includes power converter 10, which supplies a rectified voltage V rec t to the load. Power converter 10 is a full bridge …
FIG. 2 is that it is unsuitable for full implementation of the circuit with GaN FETs because of the potential for an over-voltage condition on the voltage …
FIG. 3 shows the gate-to-source voltage of voltage sense FETs 26, 27 in waveforms 260, 270, respectively. As can be seen in these wavefor m s, the …
FIG. 4) for implementing the synchronous modulation. Current mirror circuit 324 is identical to current mirror circuit 325, but is a mirror image. Current …
FIG. 5 shows an exemplary current mirror, according to one embodiment. [0014]
FIG. 6 shows wave fo rms associated with a power converter circuit according to embodiments disclosed herein. [0015]
FIG. 7 in that it includes inductors 546, 547 coupled in series between the AC voltage source 502 and power F ETs 502, 503, and, shunt capacitors 503, 504 …
FIG. 8 shows a power converter circuit according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION [0017]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power converter circuit comprising: a power convert e r comprising first and second power FETs having respective gates receiving respective alternating and opposite voltage waveforms such that the first and second power FETs conduct oppositely to each other; first and second turn-off FETs having: (i) respective drains connected to the gates of the first and second power FETs; (ii) respective sources connected to ground; and (iii) respective gates connected to the gates of opposite ones of the first and power FETs, to prevent spurious turn on of the first and second power FETs during periods in which the opposite first and second power FETs is turned on; and first and second voltage sense FETs having respective sources connected to the respective drains of the first and second turn-off FETs and to the respective gates of the first and second power FETs to limit the voltage applied to the respective gates of the first and second power FETs, the first and second voltage sense FETs having respective gates synchronously modulated with the first and second power FETs to SVG 16114718.08-28-2018.JLE₃MB₅WRXEAPX3.CLM.1.svg 0.16 5.42 Black and white turn-off FET is on and the corresponding power FET is off.
The power converter circuit of claim 1, wherein the first and second power FETs are GaN F ETs.
The power converter circuit of claim 1, wherein the first and second turn-off FETs are GaN FETs.
The power converter circuit of claim 1, wherein the first and second voltage sense FETs are GaN FETs.
The power converter circuit of claim 1, wherein the power converter is implemented in a cu rr ent-mode class D configuration.
The pow e r converter circuit of claim 1, wherein the power converter is implemented in a class E configuration.
The power converter circuit of claim 1, further comprising first and second current mirror circuits connected to the gates of the first and second current sense FETs for synchronously modulating each of th e f irst and second voltage sense FETs with the corresponding power FET to limit the gate to source voltage of the voltage sense FET when the corresponding turn-off F ET is on and the corresponding power FET is off.
The power converter circuit of claim 1, further comprising first and second voltage clamps coupled to the gates o f the first and second power FETs, respectively.
The power converter circuit of claim 1, further comprising f irst and second gate resistors coupled to the gates of the first and second power FETs, respectively, to maintain the respective first and second power FETs at zero volts in an off state.
Layer stacks claimed or described, ordered top of device to substrate.
GaN FET gate driver power converter circuit
No layer stack recorded.
Current-mode class D power converter circuit
No layer stack recorded.
Class E power converter circuit
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. Power converter circuit 100 includes power converter 10, which supplies a rectified voltage V rec t to the load. Power converter 10 is a full bridge …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≤ 5 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,784,794Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Power converter circuit 100 includes power converter 10, which supplies a rectified voltage V rec t to the load. Power converter 10 is a full bridge …
FIG. 2 is that it is unsuitable for full implementation of the circuit with GaN FETs because of the potential for an over-voltage condition on the voltage …
FIG. 3 shows the gate-to-source voltage of voltage sense FETs 26, 27 in waveforms 260, 270, respectively. As can be seen in these wavefor m s, the …
FIG. 4) for implementing the synchronous modulation. Current mirror circuit 324 is identical to current mirror circuit 325, but is a mirror image. Current …
FIG. 5 shows an exemplary current mirror, according to one embodiment. [0014]
FIG. 6 shows wave fo rms associated with a power converter circuit according to embodiments disclosed herein. [0015]
FIG. 7 in that it includes inductors 546, 547 coupled in series between the AC voltage source 502 and power F ETs 502, 503, and, shunt capacitors 503, 504 …
FIG. 8 shows a power converter circuit according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION [0017]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power converter circuit comprising: a power convert e r comprising first and second power FETs having respective gates receiving respective alternating and opposite voltage waveforms such that the first and second power FETs conduct oppositely to each other; first and second turn-off FETs having: (i) respective drains connected to the gates of the first and second power FETs; (ii) respective sources connected to ground; and (iii) respective gates connected to the gates of opposite ones of the first and power FETs, to prevent spurious turn on of the first and second power FETs during periods in which the opposite first and second power FETs is turned on; and first and second voltage sense FETs having respective sources connected to the respective drains of the first and second turn-off FETs and to the respective gates of the first and second power FETs to limit the voltage applied to the respective gates of the first and second power FETs, the first and second voltage sense FETs having respective gates synchronously modulated with the first and second power FETs to SVG 16114718.08-28-2018.JLE₃MB₅WRXEAPX3.CLM.1.svg 0.16 5.42 Black and white turn-off FET is on and the corresponding power FET is off.
The power converter circuit of claim 1, wherein the first and second power FETs are GaN F ETs.
The power converter circuit of claim 1, wherein the first and second turn-off FETs are GaN FETs.
The power converter circuit of claim 1, wherein the first and second voltage sense FETs are GaN FETs.
The power converter circuit of claim 1, wherein the power converter is implemented in a cu rr ent-mode class D configuration.
The pow e r converter circuit of claim 1, wherein the power converter is implemented in a class E configuration.
The power converter circuit of claim 1, further comprising first and second current mirror circuits connected to the gates of the first and second current sense FETs for synchronously modulating each of th e f irst and second voltage sense FETs with the corresponding power FET to limit the gate to source voltage of the voltage sense FET when the corresponding turn-off F ET is on and the corresponding power FET is off.
The power converter circuit of claim 1, further comprising first and second voltage clamps coupled to the gates o f the first and second power FETs, respectively.
The power converter circuit of claim 1, further comprising f irst and second gate resistors coupled to the gates of the first and second power FETs, respectively, to maintain the respective first and second power FETs at zero volts in an off state.
Layer stacks claimed or described, ordered top of device to substrate.
GaN FET gate driver power converter circuit
No layer stack recorded.
Current-mode class D power converter circuit
No layer stack recorded.
Class E power converter circuit
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. Power converter circuit 100 includes power converter 10, which supplies a rectified voltage V rec t to the load. Power converter 10 is a full bridge …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≤ 5 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,784,794Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Power converter circuit 100 includes power converter 10, which supplies a rectified voltage V rec t to the load. Power converter 10 is a full bridge …
FIG. 2 is that it is unsuitable for full implementation of the circuit with GaN FETs because of the potential for an over-voltage condition on the voltage …
FIG. 3 shows the gate-to-source voltage of voltage sense FETs 26, 27 in waveforms 260, 270, respectively. As can be seen in these wavefor m s, the …
FIG. 4) for implementing the synchronous modulation. Current mirror circuit 324 is identical to current mirror circuit 325, but is a mirror image. Current …
FIG. 5 shows an exemplary current mirror, according to one embodiment. [0014]
FIG. 6 shows wave fo rms associated with a power converter circuit according to embodiments disclosed herein. [0015]
FIG. 7 in that it includes inductors 546, 547 coupled in series between the AC voltage source 502 and power F ETs 502, 503, and, shunt capacitors 503, 504 …
FIG. 8 shows a power converter circuit according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION [0017]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power converter circuit comprising: a power convert e r comprising first and second power FETs having respective gates receiving respective alternating and opposite voltage waveforms such that the first and second power FETs conduct oppositely to each other; first and second turn-off FETs having: (i) respective drains connected to the gates of the first and second power FETs; (ii) respective sources connected to ground; and (iii) respective gates connected to the gates of opposite ones of the first and power FETs, to prevent spurious turn on of the first and second power FETs during periods in which the opposite first and second power FETs is turned on; and first and second voltage sense FETs having respective sources connected to the respective drains of the first and second turn-off FETs and to the respective gates of the first and second power FETs to limit the voltage applied to the respective gates of the first and second power FETs, the first and second voltage sense FETs having respective gates synchronously modulated with the first and second power FETs to SVG 16114718.08-28-2018.JLE₃MB₅WRXEAPX3.CLM.1.svg 0.16 5.42 Black and white turn-off FET is on and the corresponding power FET is off.
The power converter circuit of claim 1, wherein the first and second power FETs are GaN F ETs.
The power converter circuit of claim 1, wherein the first and second turn-off FETs are GaN FETs.
The power converter circuit of claim 1, wherein the first and second voltage sense FETs are GaN FETs.
The power converter circuit of claim 1, wherein the power converter is implemented in a cu rr ent-mode class D configuration.
The pow e r converter circuit of claim 1, wherein the power converter is implemented in a class E configuration.
The power converter circuit of claim 1, further comprising first and second current mirror circuits connected to the gates of the first and second current sense FETs for synchronously modulating each of th e f irst and second voltage sense FETs with the corresponding power FET to limit the gate to source voltage of the voltage sense FET when the corresponding turn-off F ET is on and the corresponding power FET is off.
The power converter circuit of claim 1, further comprising first and second voltage clamps coupled to the gates o f the first and second power FETs, respectively.
The power converter circuit of claim 1, further comprising f irst and second gate resistors coupled to the gates of the first and second power FETs, respectively, to maintain the respective first and second power FETs at zero volts in an off state.
Layer stacks claimed or described, ordered top of device to substrate.
GaN FET gate driver power converter circuit
No layer stack recorded.
Current-mode class D power converter circuit
No layer stack recorded.
Class E power converter circuit
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. Power converter circuit 100 includes power converter 10, which supplies a rectified voltage V rec t to the load. Power converter 10 is a full bridge …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≤ 5 V | — |
Related documents with shared materials, methods, properties, or citations.
FIG. 2 is that it is unsuitable for full implementation of the circuit with GaN FETs because of the potential for an over-voltage condition on the voltage …
FIG. 3 shows the gate-to-source voltage of voltage sense FETs 26, 27 in waveforms 260, 270, respectively. As can be seen in these wavefor m s, the …
FIG. 4) for implementing the synchronous modulation. Current mirror circuit 324 is identical to current mirror circuit 325, but is a mirror image. Current …
FIG. 7 in that it includes inductors 546, 547 coupled in series between the AC voltage source 502 and power F ETs 502, 503, and, shunt capacitors 503, 504 …
FIG. 2 is that it is unsuitable for full implementation of the circuit with GaN FETs because of the potential for an over-voltage condition on the voltage …
FIG. 3 shows the gate-to-source voltage of voltage sense FETs 26, 27 in waveforms 260, 270, respectively. As can be seen in these wavefor m s, the …
FIG. 4) for implementing the synchronous modulation. Current mirror circuit 324 is identical to current mirror circuit 325, but is a mirror image. Current …
FIG. 7 in that it includes inductors 546, 547 coupled in series between the AC voltage source 502 and power F ETs 502, 503, and, shunt capacitors 503, 504 …
FIG. 2 is that it is unsuitable for full implementation of the circuit with GaN FETs because of the potential for an over-voltage condition on the voltage …
FIG. 3 shows the gate-to-source voltage of voltage sense FETs 26, 27 in waveforms 260, 270, respectively. As can be seen in these wavefor m s, the …
FIG. 4) for implementing the synchronous modulation. Current mirror circuit 324 is identical to current mirror circuit 325, but is a mirror image. Current …
FIG. 7 in that it includes inductors 546, 547 coupled in series between the AC voltage source 502 and power F ETs 502, 503, and, shunt capacitors 503, 504 …
FIG. 2 is that it is unsuitable for full implementation of the circuit with GaN FETs because of the potential for an over-voltage condition on the voltage …
FIG. 3 shows the gate-to-source voltage of voltage sense FETs 26, 27 in waveforms 260, 270, respectively. As can be seen in these wavefor m s, the …
FIG. 4) for implementing the synchronous modulation. Current mirror circuit 324 is identical to current mirror circuit 325, but is a mirror image. Current …
FIG. 7 in that it includes inductors 546, 547 coupled in series between the AC voltage source 502 and power F ETs 502, 503, and, shunt capacitors 503, 504 …