Patent
Atlas literature
Patent
US 12,046,666 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(a) depicts top-down views of an illustrative gal- lium nitride (GaN)-based transistor that implements a block- 65 based hybrid drain contact structure, …
FIG. 2(b) depicts top-down views of yet another illustra- tive gallium nitride-based transistor that implements the block-based hybrid drain contact structure, …
FIGS. 3(a)-3(d) are illustrative flow diagrams depicting cross-sectional side views of an illustrative gallium nitride- based transistor, in accordance with …
FIGS. 4(a)-4(d) are illustrative flow diagrams depicting cross-sectional side views of an illustrative gallium nitride- based transistor, in accordance with …
FIG. 5 depicts an illustrative method to fabricate a gallium nitride-based transistor that implements the block-based hybrid drain contact structure, in …
FIGS. 25 4(a)-4(d). The method 500 begins with obtaining a substrate 302 including a heterostructure 301 (step 510;
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: depositing a p-type gallium nitride (GaN) layer on a heterostructure over a substrate; selectively etching the p-type gallium nitride (GaN) layer to form a p-type GaN structure in a gate area of a GaN transistor and multiple p-type GaN blocks in a drain area of the GaN transistor, wherein the p-type GaN structure and the multiple p-type GaN blocks have a same thickness; and forming a first drain contact structure supported by the heterostructure, wherein the multiple p-type GaN blocks are located between the p-type GaN structure and the first drain contact structure.
The method of claim 1, further comprising: forming a gate contact structure supported by the p-type GaN structure; forming a source contact structure supported by the heterostructure; and forming blocks of a second drain contact structure sup-ported by the multiple p-type GaN blocks.
The method of claim 1, wherein the heterostructure comprises a GaN layer and an AlGaN layer disposed on the GaN layer.
The method of claim 1, wherein a first contour of a two-dimensional electron gas (2DEG) of the GaN transistor has a first depletion region, wherein a second contour of the 2DEG has second and third depletion regions.
A method of forming a gallium nitride (GaN)-based transistor, comprising: forming a GaN layer over a substrate; forming an aluminum nitride gallium (AlGaN) layer over the GaN layer; forming a p-doped GaN structure over the AlGaN layer; forming a source contact structure over the AlGaN layer; forming a first drain contact structure over the AlGaN layer; and B₂ forming multiple p-doped GaN blocks over the AlGaN layer and located between the p-doped GaN structure and the first drain contact structure, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein: first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers; and the p-doped GaN structure and the multiple p-doped GaN blocks have a same thickness.
The method of claim 6 further comprising: forming multiple second drain contact structures located between the p-doped GaN structure and the first drain contact structure, each of the multiple second drain contact structures physically separated from the remaining second drain contact structures, and each of the multiple second drain contact structures disposed on a different one of the multiple p-doped GaN blocks, wherein each of the multiple second drain contact structures electrically couples to the first drain contact structure; and forming a gate contact structure on the p-doped GaN structure.
The method of claim 6, wherein the second contour of the 2DEG has first and second depletion regions, wherein the first depletion region is positioned below the p-doped GaN structure, and wherein the second depletion region is positioned below one of the multiple p-doped GaN blocks.
The method of claim 6, wherein the AlGaN layer has a uniform thickness.
The method of claim 6, wherein the p-doped GaN structure and the multiple p-doped GaN blocks are concur-rently formed.
A method of forming a transistor, comprising: forming a GaN layer supported over a substrate; forming an aluminum nitride gallium (AlGaN) layer over the GaN layer; forming a p-doped GaN structure and multiple p-doped GaN blocks over the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein the p-doped GaN structure and the multiple p-doped GaN blocks have a same thickness; forming a source contact structure over the AlGaN layer; forming a drain contact structure over the multiple p-doped GaN blocks, wherein a linear portion of the drain contact structure overlies the multiple p-doped GaN blocks; and forming a gate contact structure over the p-doped GaN structure, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.
The method of claim 11, wherein the second contour of the 2DEG has a first depletion region below the drain contact structure and a second depletion region below the gate contact structure.
The method of claim 11, wherein the first contour of the 2DEG has a single depletion region, wherein the second contour of 2DEG has two depletion regions.
The method of claim 11, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a first distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a second distance from each other.
The method of claim 11, wherein the AlGaN layer has a uniform thickness.
The method of claim 11, wherein the p-doped GaN structure and the multiple p-doped GaN blocks are concur-rently formed.
A method, comprising: forming a GaN layer over a substrate; forming an aluminum nitride gallium (AlGaN) layer over the GaN layer; forming a p-doped GaN layer over the AlGaN layer; forming a gate contact structure on the p-doped GaN layer; forming a first drain contact structure on the AlGaN layer; forming multiple p-doped GaN blocks over the AlGaN layer, wherein the multiple p-doped GaN blocks are located between the p-doped GaN layer and the first drain contact structure, and wherein the p-doped GaN layer and the multiple p-doped GaN blocks have a same thickness; forming multiple second drain contact structures, each of the multiple second drain contact structures physically separated from the remaining second drain contact structures, and each of the multiple second drain con-tact structures is disposed on a different one of the multiple p-doped GaN blocks, wherein each of the B₂ multiple second drain contact structures conductively couples to the first drain contact structure; and forming a source contact structure disposed on the AlGaN layer.
The method of claim 20, wherein the AlGaN layer has a chemical composition of Al(X)In(Y)Ga(1-X-Y)N, wherein X and Y are nonzero concentrations of aluminum and indium, respectively.
The method of claim 20, wherein a first contour of a two-dimensional electron gas (2DEG) of the GaN-based transistor is present below the p-doped GaN structure, and wherein a second contour of the 2DEG is present below the p-doped GaN structure and at least one of the multiple p-doped GaN blocks.
The method of claim 20, wherein a first contour of a 2DEG of the GaN-based transistor has a first depletion region, wherein a second contour of a 2DEG of the GaN-based transistor has second and third depletion regions.
The method of claim 20, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a first distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a second different dis-tance from each other.
The method of claim 20, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a same distance from each other.
The method of claim 20, wherein the AlGaN layer has a uniform thickness.
The method of claim 20, wherein the p-doped GaN structure and the multiple p-doped GaN blocks are concur-rently formed. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based enhancement-mode HEMT with block-based hybrid drain contact structure
Materials described outside the worked examples.
GaN
AlGaN
Al(X)Ga(1-X)N
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(a) depicts top-down views of an illustrative gal- lium nitride (GaN)-based transistor that implements a block- 65 based hybrid drain contact structure, …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,046,666 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(a) depicts top-down views of an illustrative gal- lium nitride (GaN)-based transistor that implements a block- 65 based hybrid drain contact structure, …
FIG. 2(b) depicts top-down views of yet another illustra- tive gallium nitride-based transistor that implements the block-based hybrid drain contact structure, …
FIGS. 3(a)-3(d) are illustrative flow diagrams depicting cross-sectional side views of an illustrative gallium nitride- based transistor, in accordance with …
FIGS. 4(a)-4(d) are illustrative flow diagrams depicting cross-sectional side views of an illustrative gallium nitride- based transistor, in accordance with …
FIG. 5 depicts an illustrative method to fabricate a gallium nitride-based transistor that implements the block-based hybrid drain contact structure, in …
FIGS. 25 4(a)-4(d). The method 500 begins with obtaining a substrate 302 including a heterostructure 301 (step 510;
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: depositing a p-type gallium nitride (GaN) layer on a heterostructure over a substrate; selectively etching the p-type gallium nitride (GaN) layer to form a p-type GaN structure in a gate area of a GaN transistor and multiple p-type GaN blocks in a drain area of the GaN transistor, wherein the p-type GaN structure and the multiple p-type GaN blocks have a same thickness; and forming a first drain contact structure supported by the heterostructure, wherein the multiple p-type GaN blocks are located between the p-type GaN structure and the first drain contact structure.
The method of claim 1, further comprising: forming a gate contact structure supported by the p-type GaN structure; forming a source contact structure supported by the heterostructure; and forming blocks of a second drain contact structure sup-ported by the multiple p-type GaN blocks.
The method of claim 1, wherein the heterostructure comprises a GaN layer and an AlGaN layer disposed on the GaN layer.
The method of claim 1, wherein a first contour of a two-dimensional electron gas (2DEG) of the GaN transistor has a first depletion region, wherein a second contour of the 2DEG has second and third depletion regions.
A method of forming a gallium nitride (GaN)-based transistor, comprising: forming a GaN layer over a substrate; forming an aluminum nitride gallium (AlGaN) layer over the GaN layer; forming a p-doped GaN structure over the AlGaN layer; forming a source contact structure over the AlGaN layer; forming a first drain contact structure over the AlGaN layer; and B₂ forming multiple p-doped GaN blocks over the AlGaN layer and located between the p-doped GaN structure and the first drain contact structure, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein: first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers; and the p-doped GaN structure and the multiple p-doped GaN blocks have a same thickness.
The method of claim 6 further comprising: forming multiple second drain contact structures located between the p-doped GaN structure and the first drain contact structure, each of the multiple second drain contact structures physically separated from the remaining second drain contact structures, and each of the multiple second drain contact structures disposed on a different one of the multiple p-doped GaN blocks, wherein each of the multiple second drain contact structures electrically couples to the first drain contact structure; and forming a gate contact structure on the p-doped GaN structure.
The method of claim 6, wherein the second contour of the 2DEG has first and second depletion regions, wherein the first depletion region is positioned below the p-doped GaN structure, and wherein the second depletion region is positioned below one of the multiple p-doped GaN blocks.
The method of claim 6, wherein the AlGaN layer has a uniform thickness.
The method of claim 6, wherein the p-doped GaN structure and the multiple p-doped GaN blocks are concur-rently formed.
A method of forming a transistor, comprising: forming a GaN layer supported over a substrate; forming an aluminum nitride gallium (AlGaN) layer over the GaN layer; forming a p-doped GaN structure and multiple p-doped GaN blocks over the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein the p-doped GaN structure and the multiple p-doped GaN blocks have a same thickness; forming a source contact structure over the AlGaN layer; forming a drain contact structure over the multiple p-doped GaN blocks, wherein a linear portion of the drain contact structure overlies the multiple p-doped GaN blocks; and forming a gate contact structure over the p-doped GaN structure, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.
The method of claim 11, wherein the second contour of the 2DEG has a first depletion region below the drain contact structure and a second depletion region below the gate contact structure.
The method of claim 11, wherein the first contour of the 2DEG has a single depletion region, wherein the second contour of 2DEG has two depletion regions.
The method of claim 11, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a first distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a second distance from each other.
The method of claim 11, wherein the AlGaN layer has a uniform thickness.
The method of claim 11, wherein the p-doped GaN structure and the multiple p-doped GaN blocks are concur-rently formed.
A method, comprising: forming a GaN layer over a substrate; forming an aluminum nitride gallium (AlGaN) layer over the GaN layer; forming a p-doped GaN layer over the AlGaN layer; forming a gate contact structure on the p-doped GaN layer; forming a first drain contact structure on the AlGaN layer; forming multiple p-doped GaN blocks over the AlGaN layer, wherein the multiple p-doped GaN blocks are located between the p-doped GaN layer and the first drain contact structure, and wherein the p-doped GaN layer and the multiple p-doped GaN blocks have a same thickness; forming multiple second drain contact structures, each of the multiple second drain contact structures physically separated from the remaining second drain contact structures, and each of the multiple second drain con-tact structures is disposed on a different one of the multiple p-doped GaN blocks, wherein each of the B₂ multiple second drain contact structures conductively couples to the first drain contact structure; and forming a source contact structure disposed on the AlGaN layer.
The method of claim 20, wherein the AlGaN layer has a chemical composition of Al(X)In(Y)Ga(1-X-Y)N, wherein X and Y are nonzero concentrations of aluminum and indium, respectively.
The method of claim 20, wherein a first contour of a two-dimensional electron gas (2DEG) of the GaN-based transistor is present below the p-doped GaN structure, and wherein a second contour of the 2DEG is present below the p-doped GaN structure and at least one of the multiple p-doped GaN blocks.
The method of claim 20, wherein a first contour of a 2DEG of the GaN-based transistor has a first depletion region, wherein a second contour of a 2DEG of the GaN-based transistor has second and third depletion regions.
The method of claim 20, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a first distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a second different dis-tance from each other.
The method of claim 20, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a same distance from each other.
The method of claim 20, wherein the AlGaN layer has a uniform thickness.
The method of claim 20, wherein the p-doped GaN structure and the multiple p-doped GaN blocks are concur-rently formed. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based enhancement-mode HEMT with block-based hybrid drain contact structure
Materials described outside the worked examples.
GaN
AlGaN
Al(X)Ga(1-X)N
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(a) depicts top-down views of an illustrative gal- lium nitride (GaN)-based transistor that implements a block- 65 based hybrid drain contact structure, …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,046,666 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(a) depicts top-down views of an illustrative gal- lium nitride (GaN)-based transistor that implements a block- 65 based hybrid drain contact structure, …
FIG. 2(b) depicts top-down views of yet another illustra- tive gallium nitride-based transistor that implements the block-based hybrid drain contact structure, …
FIGS. 3(a)-3(d) are illustrative flow diagrams depicting cross-sectional side views of an illustrative gallium nitride- based transistor, in accordance with …
FIGS. 4(a)-4(d) are illustrative flow diagrams depicting cross-sectional side views of an illustrative gallium nitride- based transistor, in accordance with …
FIG. 5 depicts an illustrative method to fabricate a gallium nitride-based transistor that implements the block-based hybrid drain contact structure, in …
FIGS. 25 4(a)-4(d). The method 500 begins with obtaining a substrate 302 including a heterostructure 301 (step 510;
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: depositing a p-type gallium nitride (GaN) layer on a heterostructure over a substrate; selectively etching the p-type gallium nitride (GaN) layer to form a p-type GaN structure in a gate area of a GaN transistor and multiple p-type GaN blocks in a drain area of the GaN transistor, wherein the p-type GaN structure and the multiple p-type GaN blocks have a same thickness; and forming a first drain contact structure supported by the heterostructure, wherein the multiple p-type GaN blocks are located between the p-type GaN structure and the first drain contact structure.
The method of claim 1, further comprising: forming a gate contact structure supported by the p-type GaN structure; forming a source contact structure supported by the heterostructure; and forming blocks of a second drain contact structure sup-ported by the multiple p-type GaN blocks.
The method of claim 1, wherein the heterostructure comprises a GaN layer and an AlGaN layer disposed on the GaN layer.
The method of claim 1, wherein a first contour of a two-dimensional electron gas (2DEG) of the GaN transistor has a first depletion region, wherein a second contour of the 2DEG has second and third depletion regions.
A method of forming a gallium nitride (GaN)-based transistor, comprising: forming a GaN layer over a substrate; forming an aluminum nitride gallium (AlGaN) layer over the GaN layer; forming a p-doped GaN structure over the AlGaN layer; forming a source contact structure over the AlGaN layer; forming a first drain contact structure over the AlGaN layer; and B₂ forming multiple p-doped GaN blocks over the AlGaN layer and located between the p-doped GaN structure and the first drain contact structure, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein: first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers; and the p-doped GaN structure and the multiple p-doped GaN blocks have a same thickness.
The method of claim 6 further comprising: forming multiple second drain contact structures located between the p-doped GaN structure and the first drain contact structure, each of the multiple second drain contact structures physically separated from the remaining second drain contact structures, and each of the multiple second drain contact structures disposed on a different one of the multiple p-doped GaN blocks, wherein each of the multiple second drain contact structures electrically couples to the first drain contact structure; and forming a gate contact structure on the p-doped GaN structure.
The method of claim 6, wherein the second contour of the 2DEG has first and second depletion regions, wherein the first depletion region is positioned below the p-doped GaN structure, and wherein the second depletion region is positioned below one of the multiple p-doped GaN blocks.
The method of claim 6, wherein the AlGaN layer has a uniform thickness.
The method of claim 6, wherein the p-doped GaN structure and the multiple p-doped GaN blocks are concur-rently formed.
A method of forming a transistor, comprising: forming a GaN layer supported over a substrate; forming an aluminum nitride gallium (AlGaN) layer over the GaN layer; forming a p-doped GaN structure and multiple p-doped GaN blocks over the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein the p-doped GaN structure and the multiple p-doped GaN blocks have a same thickness; forming a source contact structure over the AlGaN layer; forming a drain contact structure over the multiple p-doped GaN blocks, wherein a linear portion of the drain contact structure overlies the multiple p-doped GaN blocks; and forming a gate contact structure over the p-doped GaN structure, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.
The method of claim 11, wherein the second contour of the 2DEG has a first depletion region below the drain contact structure and a second depletion region below the gate contact structure.
The method of claim 11, wherein the first contour of the 2DEG has a single depletion region, wherein the second contour of 2DEG has two depletion regions.
The method of claim 11, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a first distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a second distance from each other.
The method of claim 11, wherein the AlGaN layer has a uniform thickness.
The method of claim 11, wherein the p-doped GaN structure and the multiple p-doped GaN blocks are concur-rently formed.
A method, comprising: forming a GaN layer over a substrate; forming an aluminum nitride gallium (AlGaN) layer over the GaN layer; forming a p-doped GaN layer over the AlGaN layer; forming a gate contact structure on the p-doped GaN layer; forming a first drain contact structure on the AlGaN layer; forming multiple p-doped GaN blocks over the AlGaN layer, wherein the multiple p-doped GaN blocks are located between the p-doped GaN layer and the first drain contact structure, and wherein the p-doped GaN layer and the multiple p-doped GaN blocks have a same thickness; forming multiple second drain contact structures, each of the multiple second drain contact structures physically separated from the remaining second drain contact structures, and each of the multiple second drain con-tact structures is disposed on a different one of the multiple p-doped GaN blocks, wherein each of the B₂ multiple second drain contact structures conductively couples to the first drain contact structure; and forming a source contact structure disposed on the AlGaN layer.
The method of claim 20, wherein the AlGaN layer has a chemical composition of Al(X)In(Y)Ga(1-X-Y)N, wherein X and Y are nonzero concentrations of aluminum and indium, respectively.
The method of claim 20, wherein a first contour of a two-dimensional electron gas (2DEG) of the GaN-based transistor is present below the p-doped GaN structure, and wherein a second contour of the 2DEG is present below the p-doped GaN structure and at least one of the multiple p-doped GaN blocks.
The method of claim 20, wherein a first contour of a 2DEG of the GaN-based transistor has a first depletion region, wherein a second contour of a 2DEG of the GaN-based transistor has second and third depletion regions.
The method of claim 20, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a first distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a second different dis-tance from each other.
The method of claim 20, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a same distance from each other.
The method of claim 20, wherein the AlGaN layer has a uniform thickness.
The method of claim 20, wherein the p-doped GaN structure and the multiple p-doped GaN blocks are concur-rently formed. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based enhancement-mode HEMT with block-based hybrid drain contact structure
Materials described outside the worked examples.
GaN
AlGaN
Al(X)Ga(1-X)N
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(a) depicts top-down views of an illustrative gal- lium nitride (GaN)-based transistor that implements a block- 65 based hybrid drain contact structure, …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,046,666 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(a) depicts top-down views of an illustrative gal- lium nitride (GaN)-based transistor that implements a block- 65 based hybrid drain contact structure, …
FIG. 2(b) depicts top-down views of yet another illustra- tive gallium nitride-based transistor that implements the block-based hybrid drain contact structure, …
FIGS. 3(a)-3(d) are illustrative flow diagrams depicting cross-sectional side views of an illustrative gallium nitride- based transistor, in accordance with …
FIGS. 4(a)-4(d) are illustrative flow diagrams depicting cross-sectional side views of an illustrative gallium nitride- based transistor, in accordance with …
FIG. 5 depicts an illustrative method to fabricate a gallium nitride-based transistor that implements the block-based hybrid drain contact structure, in …
FIGS. 25 4(a)-4(d). The method 500 begins with obtaining a substrate 302 including a heterostructure 301 (step 510;
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: depositing a p-type gallium nitride (GaN) layer on a heterostructure over a substrate; selectively etching the p-type gallium nitride (GaN) layer to form a p-type GaN structure in a gate area of a GaN transistor and multiple p-type GaN blocks in a drain area of the GaN transistor, wherein the p-type GaN structure and the multiple p-type GaN blocks have a same thickness; and forming a first drain contact structure supported by the heterostructure, wherein the multiple p-type GaN blocks are located between the p-type GaN structure and the first drain contact structure.
The method of claim 1, further comprising: forming a gate contact structure supported by the p-type GaN structure; forming a source contact structure supported by the heterostructure; and forming blocks of a second drain contact structure sup-ported by the multiple p-type GaN blocks.
The method of claim 1, wherein the heterostructure comprises a GaN layer and an AlGaN layer disposed on the GaN layer.
The method of claim 1, wherein a first contour of a two-dimensional electron gas (2DEG) of the GaN transistor has a first depletion region, wherein a second contour of the 2DEG has second and third depletion regions.
A method of forming a gallium nitride (GaN)-based transistor, comprising: forming a GaN layer over a substrate; forming an aluminum nitride gallium (AlGaN) layer over the GaN layer; forming a p-doped GaN structure over the AlGaN layer; forming a source contact structure over the AlGaN layer; forming a first drain contact structure over the AlGaN layer; and B₂ forming multiple p-doped GaN blocks over the AlGaN layer and located between the p-doped GaN structure and the first drain contact structure, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein: first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers; and the p-doped GaN structure and the multiple p-doped GaN blocks have a same thickness.
The method of claim 6 further comprising: forming multiple second drain contact structures located between the p-doped GaN structure and the first drain contact structure, each of the multiple second drain contact structures physically separated from the remaining second drain contact structures, and each of the multiple second drain contact structures disposed on a different one of the multiple p-doped GaN blocks, wherein each of the multiple second drain contact structures electrically couples to the first drain contact structure; and forming a gate contact structure on the p-doped GaN structure.
The method of claim 6, wherein the second contour of the 2DEG has first and second depletion regions, wherein the first depletion region is positioned below the p-doped GaN structure, and wherein the second depletion region is positioned below one of the multiple p-doped GaN blocks.
The method of claim 6, wherein the AlGaN layer has a uniform thickness.
The method of claim 6, wherein the p-doped GaN structure and the multiple p-doped GaN blocks are concur-rently formed.
A method of forming a transistor, comprising: forming a GaN layer supported over a substrate; forming an aluminum nitride gallium (AlGaN) layer over the GaN layer; forming a p-doped GaN structure and multiple p-doped GaN blocks over the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein the p-doped GaN structure and the multiple p-doped GaN blocks have a same thickness; forming a source contact structure over the AlGaN layer; forming a drain contact structure over the multiple p-doped GaN blocks, wherein a linear portion of the drain contact structure overlies the multiple p-doped GaN blocks; and forming a gate contact structure over the p-doped GaN structure, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.
The method of claim 11, wherein the second contour of the 2DEG has a first depletion region below the drain contact structure and a second depletion region below the gate contact structure.
The method of claim 11, wherein the first contour of the 2DEG has a single depletion region, wherein the second contour of 2DEG has two depletion regions.
The method of claim 11, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a first distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a second distance from each other.
The method of claim 11, wherein the AlGaN layer has a uniform thickness.
The method of claim 11, wherein the p-doped GaN structure and the multiple p-doped GaN blocks are concur-rently formed.
A method, comprising: forming a GaN layer over a substrate; forming an aluminum nitride gallium (AlGaN) layer over the GaN layer; forming a p-doped GaN layer over the AlGaN layer; forming a gate contact structure on the p-doped GaN layer; forming a first drain contact structure on the AlGaN layer; forming multiple p-doped GaN blocks over the AlGaN layer, wherein the multiple p-doped GaN blocks are located between the p-doped GaN layer and the first drain contact structure, and wherein the p-doped GaN layer and the multiple p-doped GaN blocks have a same thickness; forming multiple second drain contact structures, each of the multiple second drain contact structures physically separated from the remaining second drain contact structures, and each of the multiple second drain con-tact structures is disposed on a different one of the multiple p-doped GaN blocks, wherein each of the B₂ multiple second drain contact structures conductively couples to the first drain contact structure; and forming a source contact structure disposed on the AlGaN layer.
The method of claim 20, wherein the AlGaN layer has a chemical composition of Al(X)In(Y)Ga(1-X-Y)N, wherein X and Y are nonzero concentrations of aluminum and indium, respectively.
The method of claim 20, wherein a first contour of a two-dimensional electron gas (2DEG) of the GaN-based transistor is present below the p-doped GaN structure, and wherein a second contour of the 2DEG is present below the p-doped GaN structure and at least one of the multiple p-doped GaN blocks.
The method of claim 20, wherein a first contour of a 2DEG of the GaN-based transistor has a first depletion region, wherein a second contour of a 2DEG of the GaN-based transistor has second and third depletion regions.
The method of claim 20, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a first distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a second different dis-tance from each other.
The method of claim 20, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a same distance from each other.
The method of claim 20, wherein the AlGaN layer has a uniform thickness.
The method of claim 20, wherein the p-doped GaN structure and the multiple p-doped GaN blocks are concur-rently formed. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based enhancement-mode HEMT with block-based hybrid drain contact structure
Materials described outside the worked examples.
GaN
AlGaN
Al(X)Ga(1-X)N
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(a) depicts top-down views of an illustrative gal- lium nitride (GaN)-based transistor that implements a block- 65 based hybrid drain contact structure, …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
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