Patent
Atlas literature
Patent
US 10,553,689Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross-sectional illustration of a transistor that includes a bulk field plate coupled to the gate electrode in a bulk conductive structure.
Figure 2A is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an embodiment of the invention.
Figure 2B is a cross-sectional illustration of a transistor that includes a single field plate, according to an embodiment of the invention.
Figure 2C is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an additional embodiment of the invention.
Figure 3A is a cross-sectional illustration of a portion of a transistor, according to an embodiment of the invention.
Figure 3B is a cross-sectional illustration of the transistor in
Figure 3C is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3D is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3E is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3F is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3G is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3H is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 4 is a cross-sectional illustration of an interposer implementing one or more embodiments of the invention.
Figure 5 is a schematic of a computing device that includes one or more transistors built in accordance with an embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a semiconductor substrate having a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region; a first interlayer dielectric (ILD) formed over the channel region; a second ILD formed over the first ILD; and a first field plate formed in the second ILD, wherein the first field plate is not formed as a single bulk conductive feature with the gate electrode, and wherein a top surface of the first field plate is substantially coplanar with a top surface of the second ILD. Currently amended
The semiconductor device of claim 1, wherein the first field plate is coupled to the gate electrode or the source electrode with one or more vias. Original
The semiconductor device of claim 1, wherein the first field plate is not electrically coupled to the gate electrode, and not electrically coupled to the source electrode. Original
The semiconductor device of claim 1, wherein the first IL D is a different material than the second ILD. Original
The semiconductor device of claim 1, further comprising: a third ILD; and a second field plate formed in the third ILD, wherein the second field plate is not formed as a single bulk conductive feature with the gate electrode or the first field plate. Original
A method of forming electric field plates over a transistor, comprising: forming a transistor that includes a source region, a drain region, a channel region between the source and drain region, and a gate electrode over the channel region; forming a first interlayer dielectric (ILD) over the channel region; forming a second IL D over the first ILD; patterning the second IL D to form a first field plate opening; depositing a conductive material into the first field plate opening to form a first field plate; forming a third ILD over the second IL D and the first field plate; patterning the third ILD to form a second field plate opening; and depositing a conductive material into the second field plate opening to form a second field plate. Original
The method of claim 13, wherein the first ILD is formed with a sputtering or chemical vapor deposition process. Original
The method of claim 13, wherein the first ILD is a different material than the second ILD. Original
The method of claim 13, wherein the first fi eld plate opening is patterned at the same time one or more interconnect line openings are patterned in the second ILD, and wherein the first field plate is deposited at the same time the interconnect lines are formed in the second ILD. Original
The method of claim 13, wherein the gate electrode is a different material than the first field plate and the second field plate. Original
The method of claim 13, wherein the first field plate and the second field plate are not electrically coupled to the gate electrode, and not electrically coupled to the source electrode. Original
The method of claim 13, wherein the first field plate and the second field plate are electrically coupled by one or more v ias. Original
The method of claim 13, wherein one of the first field plate and the second field plate is electrically coupled to the gate electrode, and the other of the first field plate and the second field plate is electrically coupled to the source electrode Original
The method of claim 13, wherein the channel region is G aN. Original
A semiconductor device comprising: a semiconductor substrate having a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region, wherein the channel region is GaN, and wherein a polarization layer is formed over a top surface of the channel region; a first interlayer dielectric (ILD) formed over the channel region; a second ILD formed over the first ILD, second ILD; a first field plate formed in the second as a single bulk conductive feature with the gate formed in the third ILD, wherein the second field feature with the gate electrode or the first field
Layer stacks claimed or described, ordered top of device to substrate.
high-voltage transistor with stacked field plates
GaN high-voltage transistor with polarization layer and stacked field plates
Materials described outside the worked examples.
GaN
polarization layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a cross-sectional illustration of a transistor that includes a bulk field plate coupled to the gate electrode in a bulk conductive structure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,553,689Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross-sectional illustration of a transistor that includes a bulk field plate coupled to the gate electrode in a bulk conductive structure.
Figure 2A is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an embodiment of the invention.
Figure 2B is a cross-sectional illustration of a transistor that includes a single field plate, according to an embodiment of the invention.
Figure 2C is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an additional embodiment of the invention.
Figure 3A is a cross-sectional illustration of a portion of a transistor, according to an embodiment of the invention.
Figure 3B is a cross-sectional illustration of the transistor in
Figure 3C is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3D is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3E is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3F is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3G is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3H is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 4 is a cross-sectional illustration of an interposer implementing one or more embodiments of the invention.
Figure 5 is a schematic of a computing device that includes one or more transistors built in accordance with an embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a semiconductor substrate having a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region; a first interlayer dielectric (ILD) formed over the channel region; a second ILD formed over the first ILD; and a first field plate formed in the second ILD, wherein the first field plate is not formed as a single bulk conductive feature with the gate electrode, and wherein a top surface of the first field plate is substantially coplanar with a top surface of the second ILD. Currently amended
The semiconductor device of claim 1, wherein the first field plate is coupled to the gate electrode or the source electrode with one or more vias. Original
The semiconductor device of claim 1, wherein the first field plate is not electrically coupled to the gate electrode, and not electrically coupled to the source electrode. Original
The semiconductor device of claim 1, wherein the first IL D is a different material than the second ILD. Original
The semiconductor device of claim 1, further comprising: a third ILD; and a second field plate formed in the third ILD, wherein the second field plate is not formed as a single bulk conductive feature with the gate electrode or the first field plate. Original
A method of forming electric field plates over a transistor, comprising: forming a transistor that includes a source region, a drain region, a channel region between the source and drain region, and a gate electrode over the channel region; forming a first interlayer dielectric (ILD) over the channel region; forming a second IL D over the first ILD; patterning the second IL D to form a first field plate opening; depositing a conductive material into the first field plate opening to form a first field plate; forming a third ILD over the second IL D and the first field plate; patterning the third ILD to form a second field plate opening; and depositing a conductive material into the second field plate opening to form a second field plate. Original
The method of claim 13, wherein the first ILD is formed with a sputtering or chemical vapor deposition process. Original
The method of claim 13, wherein the first ILD is a different material than the second ILD. Original
The method of claim 13, wherein the first fi eld plate opening is patterned at the same time one or more interconnect line openings are patterned in the second ILD, and wherein the first field plate is deposited at the same time the interconnect lines are formed in the second ILD. Original
The method of claim 13, wherein the gate electrode is a different material than the first field plate and the second field plate. Original
The method of claim 13, wherein the first field plate and the second field plate are not electrically coupled to the gate electrode, and not electrically coupled to the source electrode. Original
The method of claim 13, wherein the first field plate and the second field plate are electrically coupled by one or more v ias. Original
The method of claim 13, wherein one of the first field plate and the second field plate is electrically coupled to the gate electrode, and the other of the first field plate and the second field plate is electrically coupled to the source electrode Original
The method of claim 13, wherein the channel region is G aN. Original
A semiconductor device comprising: a semiconductor substrate having a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region, wherein the channel region is GaN, and wherein a polarization layer is formed over a top surface of the channel region; a first interlayer dielectric (ILD) formed over the channel region; a second ILD formed over the first ILD, second ILD; a first field plate formed in the second as a single bulk conductive feature with the gate formed in the third ILD, wherein the second field feature with the gate electrode or the first field
Layer stacks claimed or described, ordered top of device to substrate.
high-voltage transistor with stacked field plates
GaN high-voltage transistor with polarization layer and stacked field plates
Materials described outside the worked examples.
GaN
polarization layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a cross-sectional illustration of a transistor that includes a bulk field plate coupled to the gate electrode in a bulk conductive structure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,553,689Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross-sectional illustration of a transistor that includes a bulk field plate coupled to the gate electrode in a bulk conductive structure.
Figure 2A is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an embodiment of the invention.
Figure 2B is a cross-sectional illustration of a transistor that includes a single field plate, according to an embodiment of the invention.
Figure 2C is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an additional embodiment of the invention.
Figure 3A is a cross-sectional illustration of a portion of a transistor, according to an embodiment of the invention.
Figure 3B is a cross-sectional illustration of the transistor in
Figure 3C is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3D is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3E is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3F is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3G is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3H is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 4 is a cross-sectional illustration of an interposer implementing one or more embodiments of the invention.
Figure 5 is a schematic of a computing device that includes one or more transistors built in accordance with an embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a semiconductor substrate having a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region; a first interlayer dielectric (ILD) formed over the channel region; a second ILD formed over the first ILD; and a first field plate formed in the second ILD, wherein the first field plate is not formed as a single bulk conductive feature with the gate electrode, and wherein a top surface of the first field plate is substantially coplanar with a top surface of the second ILD. Currently amended
The semiconductor device of claim 1, wherein the first field plate is coupled to the gate electrode or the source electrode with one or more vias. Original
The semiconductor device of claim 1, wherein the first field plate is not electrically coupled to the gate electrode, and not electrically coupled to the source electrode. Original
The semiconductor device of claim 1, wherein the first IL D is a different material than the second ILD. Original
The semiconductor device of claim 1, further comprising: a third ILD; and a second field plate formed in the third ILD, wherein the second field plate is not formed as a single bulk conductive feature with the gate electrode or the first field plate. Original
A method of forming electric field plates over a transistor, comprising: forming a transistor that includes a source region, a drain region, a channel region between the source and drain region, and a gate electrode over the channel region; forming a first interlayer dielectric (ILD) over the channel region; forming a second IL D over the first ILD; patterning the second IL D to form a first field plate opening; depositing a conductive material into the first field plate opening to form a first field plate; forming a third ILD over the second IL D and the first field plate; patterning the third ILD to form a second field plate opening; and depositing a conductive material into the second field plate opening to form a second field plate. Original
The method of claim 13, wherein the first ILD is formed with a sputtering or chemical vapor deposition process. Original
The method of claim 13, wherein the first ILD is a different material than the second ILD. Original
The method of claim 13, wherein the first fi eld plate opening is patterned at the same time one or more interconnect line openings are patterned in the second ILD, and wherein the first field plate is deposited at the same time the interconnect lines are formed in the second ILD. Original
The method of claim 13, wherein the gate electrode is a different material than the first field plate and the second field plate. Original
The method of claim 13, wherein the first field plate and the second field plate are not electrically coupled to the gate electrode, and not electrically coupled to the source electrode. Original
The method of claim 13, wherein the first field plate and the second field plate are electrically coupled by one or more v ias. Original
The method of claim 13, wherein one of the first field plate and the second field plate is electrically coupled to the gate electrode, and the other of the first field plate and the second field plate is electrically coupled to the source electrode Original
The method of claim 13, wherein the channel region is G aN. Original
A semiconductor device comprising: a semiconductor substrate having a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region, wherein the channel region is GaN, and wherein a polarization layer is formed over a top surface of the channel region; a first interlayer dielectric (ILD) formed over the channel region; a second ILD formed over the first ILD, second ILD; a first field plate formed in the second as a single bulk conductive feature with the gate formed in the third ILD, wherein the second field feature with the gate electrode or the first field
Layer stacks claimed or described, ordered top of device to substrate.
high-voltage transistor with stacked field plates
GaN high-voltage transistor with polarization layer and stacked field plates
Materials described outside the worked examples.
GaN
polarization layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a cross-sectional illustration of a transistor that includes a bulk field plate coupled to the gate electrode in a bulk conductive structure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,553,689Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross-sectional illustration of a transistor that includes a bulk field plate coupled to the gate electrode in a bulk conductive structure.
Figure 2A is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an embodiment of the invention.
Figure 2B is a cross-sectional illustration of a transistor that includes a single field plate, according to an embodiment of the invention.
Figure 2C is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an additional embodiment of the invention.
Figure 3A is a cross-sectional illustration of a portion of a transistor, according to an embodiment of the invention.
Figure 3B is a cross-sectional illustration of the transistor in
Figure 3C is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3D is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3E is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3F is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3G is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3H is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 4 is a cross-sectional illustration of an interposer implementing one or more embodiments of the invention.
Figure 5 is a schematic of a computing device that includes one or more transistors built in accordance with an embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a semiconductor substrate having a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region; a first interlayer dielectric (ILD) formed over the channel region; a second ILD formed over the first ILD; and a first field plate formed in the second ILD, wherein the first field plate is not formed as a single bulk conductive feature with the gate electrode, and wherein a top surface of the first field plate is substantially coplanar with a top surface of the second ILD. Currently amended
The semiconductor device of claim 1, wherein the first field plate is coupled to the gate electrode or the source electrode with one or more vias. Original
The semiconductor device of claim 1, wherein the first field plate is not electrically coupled to the gate electrode, and not electrically coupled to the source electrode. Original
The semiconductor device of claim 1, wherein the first IL D is a different material than the second ILD. Original
The semiconductor device of claim 1, further comprising: a third ILD; and a second field plate formed in the third ILD, wherein the second field plate is not formed as a single bulk conductive feature with the gate electrode or the first field plate. Original
A method of forming electric field plates over a transistor, comprising: forming a transistor that includes a source region, a drain region, a channel region between the source and drain region, and a gate electrode over the channel region; forming a first interlayer dielectric (ILD) over the channel region; forming a second IL D over the first ILD; patterning the second IL D to form a first field plate opening; depositing a conductive material into the first field plate opening to form a first field plate; forming a third ILD over the second IL D and the first field plate; patterning the third ILD to form a second field plate opening; and depositing a conductive material into the second field plate opening to form a second field plate. Original
The method of claim 13, wherein the first ILD is formed with a sputtering or chemical vapor deposition process. Original
The method of claim 13, wherein the first ILD is a different material than the second ILD. Original
The method of claim 13, wherein the first fi eld plate opening is patterned at the same time one or more interconnect line openings are patterned in the second ILD, and wherein the first field plate is deposited at the same time the interconnect lines are formed in the second ILD. Original
The method of claim 13, wherein the gate electrode is a different material than the first field plate and the second field plate. Original
The method of claim 13, wherein the first field plate and the second field plate are not electrically coupled to the gate electrode, and not electrically coupled to the source electrode. Original
The method of claim 13, wherein the first field plate and the second field plate are electrically coupled by one or more v ias. Original
The method of claim 13, wherein one of the first field plate and the second field plate is electrically coupled to the gate electrode, and the other of the first field plate and the second field plate is electrically coupled to the source electrode Original
The method of claim 13, wherein the channel region is G aN. Original
A semiconductor device comprising: a semiconductor substrate having a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region, wherein the channel region is GaN, and wherein a polarization layer is formed over a top surface of the channel region; a first interlayer dielectric (ILD) formed over the channel region; a second ILD formed over the first ILD, second ILD; a first field plate formed in the second as a single bulk conductive feature with the gate formed in the third ILD, wherein the second field feature with the gate electrode or the first field
Layer stacks claimed or described, ordered top of device to substrate.
high-voltage transistor with stacked field plates
GaN high-voltage transistor with polarization layer and stacked field plates
Materials described outside the worked examples.
GaN
polarization layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a cross-sectional illustration of a transistor that includes a bulk field plate coupled to the gate electrode in a bulk conductive structure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Related documents with shared materials, methods, properties, or citations.
first interlayer dielectric (ILD)
second interlayer dielectric (ILD)
Figure 2A is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an embodiment of the invention.
Figure 2B is a cross-sectional illustration of a transistor that includes a single field plate, according to an embodiment of the invention.
Figure 2C is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an additional embodiment of the invention.
Figure 3A is a cross-sectional illustration of a portion of a transistor, according to an embodiment of the invention.
Figure 3B is a cross-sectional illustration of the transistor in
Figure 3C is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3D is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3E is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3F is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3G is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3H is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 5 is a schematic of a computing device that includes one or more transistors built in accordance with an embodiment of the invention.
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first interlayer dielectric (ILD)
second interlayer dielectric (ILD)
Figure 2A is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an embodiment of the invention.
Figure 2B is a cross-sectional illustration of a transistor that includes a single field plate, according to an embodiment of the invention.
Figure 2C is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an additional embodiment of the invention.
Figure 3A is a cross-sectional illustration of a portion of a transistor, according to an embodiment of the invention.
Figure 3B is a cross-sectional illustration of the transistor in
Figure 3C is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3D is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3E is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3F is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3G is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3H is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 5 is a schematic of a computing device that includes one or more transistors built in accordance with an embodiment of the invention.
| — |
first interlayer dielectric (ILD)
second interlayer dielectric (ILD)
Figure 2A is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an embodiment of the invention.
Figure 2B is a cross-sectional illustration of a transistor that includes a single field plate, according to an embodiment of the invention.
Figure 2C is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an additional embodiment of the invention.
Figure 3A is a cross-sectional illustration of a portion of a transistor, according to an embodiment of the invention.
Figure 3B is a cross-sectional illustration of the transistor in
Figure 3C is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3D is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3E is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3F is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3G is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3H is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 5 is a schematic of a computing device that includes one or more transistors built in accordance with an embodiment of the invention.
| — |
first interlayer dielectric (ILD)
second interlayer dielectric (ILD)
Figure 2A is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an embodiment of the invention.
Figure 2B is a cross-sectional illustration of a transistor that includes a single field plate, according to an embodiment of the invention.
Figure 2C is a cross-sectional illustration of a transistor that includes a plurality of field plates, according to an additional embodiment of the invention.
Figure 3A is a cross-sectional illustration of a portion of a transistor, according to an embodiment of the invention.
Figure 3B is a cross-sectional illustration of the transistor in
Figure 3C is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3D is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3E is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3F is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3G is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 3H is a plan view and corresponding cross-sectional illustration of the transistor in
Figure 5 is a schematic of a computing device that includes one or more transistors built in accordance with an embodiment of the invention.
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