Claims 1 -9. Cancelled. canceled

A method of making a HEMT and Schottky diode integrated circuit device comprising the steps of: providing a substrate; disposing a back barrier layer on said substrate; disposing a channel layer on said back barrier layer; disposing a top barrier layer on said channel layer; optionally forming a cap layer on said top barrier layer; depositing a first mask over at least said back layer, said channel layer and said top barrier layer and patterning same to define two regions of said first mask, one region of which is used in forming the HEMT and the other region of which will is used in forming said Schottky diode; removing at least said channel layer and said top barrier layer where not protected by said two regions of said first mask to thereby define edges in said channel layer and in said top barrier layer; depositing a second mask in regions not projected by said first mask and removing said two regions of said first mask to thereby form two openings in said second mask, a first one of said opening being associated with the HEMT device and the second one of the openings being associated with the Schottky diode; forming sidewall spacers on exposed sidewalls of said first and second openings; 629607-1 Response to Final Official Action Dated Apri l 19, 2016 USSN 14/464,077 Page 3 increasing the depth of a portion of the first opening as needed so that a gate opening between the sidewall idcway spacers in said first opening meets said top SVG 14464077.07-18-2016.IQSRR₆K₈RXEAPX3.CLM.2.7.358.623.380.647.svg 0.08 0.073 Chemistry Black and white barrier layer or the optionally formed cap layer; increasing the depth of a portion of the second opening as needed so that an anode opening between the sidewall SVG 14464077.07-18-2016.IQSRR₆K₈RXEAPX3.CLM.2.11.628.973.650.997.svg 0.08 0.073 Chemistry Black and white idcway spacers in said second opening at least penetrates said low resistance layer; filling said first and second openings and said gate opening and anode opening with metal, the metal in said first opening and in said gate opening forming a gate of the HMET device and the metal in the second opening and in the anode opening forming an anode of the Schottky diode; forming first and second metal contacts on said barrier layer abutting at least edges of said low resistance layer, the metal first and second contacts being disposed spaced a distance from a projecting portion of the gate metal; and forming third and forth metal contacts on said barrier layer abutting at least edges of said low resistance layer, the metal third and second forth contacts being disposed spaced a distance from the anode metal.

A method of making a diode comprising: forming a metallic anode structure; forming a 2DEG carrier region disposed laterally of said anode structure, the formed 2DEG carrier region having a proximate edge at a first end of said 2DEG carrier region, the first edge being in physical contact with said metallic anode structure, said 2DEG carrier region being formed with a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; 629607-1 Response to Final Official Action Dated Apri l 19, 2016 USSN 14/464,077 Page forming a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; and forming a metallic cathode structure in contact with said low resistance doped semiconductor region.

A method of making an integrated circuit, the integrated circuit including at least one transistor and at least one diode, the method of making the integrated circuit comprising: forming a metallic anode structure; forming an 2DEG carrier region disposed laterally of said anode structure, the formed 2DEG carrier region having a proximate edge at a first end of said 2DEG carrier region, the first edge being in physical contact with said metallic anode structure, said 2DEG carrier region being formed with a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; forming a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; forming a metallic cathode structure in contact with said low resistance doped semiconductor region; forming a T-shaped gate having a leg which projects from a head portion of said T-shaped gate; 629607-1 Response to Final Official Action Dated Apri l 19, 2016 USSN 14/464,077 Page 6 forming another 2DEG carrier region disposed under said leg of said T-shaped gate; forming second and third low resistance doped semiconductor regions disposed laterally of said third low resistance doped semiconductor regions said another 2DEG carrier region; forming a metallic respectively with said second and third low resistance carrier region, said low resistance doped semiconductor 2DEG carrier region, said another 2DEG carrier doped semiconductor regions all being supported

Claims 18 -26. Cancelled. canceled another 2DEG carrier region, the second and each having an edge in contact with an edge of source and drain electrodes in contact doped semiconductor regions; said 2DEG region being disposed laterally of said region and said second and third low resistance by a common substrate.

Claims 1 -9. Cancelled. canceled

A method of making a HEMT and Schottky diode integrated circuit device comprising the steps of: providing a substrate; disposing a back barrier layer on said substrate; disposing a channel layer on said back barrier layer; disposing a top barrier layer on said channel layer; optionally forming a cap layer on said top barrier layer; depositing a first mask over at least said back layer, said channel layer and said top barrier layer and patterning same to define two regions of said first mask, one region of which is used in forming the HEMT and the other region of which will is used in forming said Schottky diode; removing at least said channel layer and said top barrier layer where not protected by said two regions of said first mask to thereby define edges in said channel layer and in said top barrier layer; depositing a second mask in regions not projected by said first mask and removing said two regions of said first mask to thereby form two openings in said second mask, a first one of said opening being associated with the HEMT device and the second one of the openings being associated with the Schottky diode; forming sidewall spacers on exposed sidewalls of said first and second openings; 629607-1 Response to Final Official Action Dated Apri l 19, 2016 USSN 14/464,077 Page 3 increasing the depth of a portion of the first opening as needed so that a gate opening between the sidewall idcway spacers in said first opening meets said top SVG 14464077.07-18-2016.IQSRR₆K₈RXEAPX3.CLM.2.7.358.623.380.647.svg 0.08 0.073 Chemistry Black and white barrier layer or the optionally formed cap layer; increasing the depth of a portion of the second opening as needed so that an anode opening between the sidewall SVG 14464077.07-18-2016.IQSRR₆K₈RXEAPX3.CLM.2.11.628.973.650.997.svg 0.08 0.073 Chemistry Black and white idcway spacers in said second opening at least penetrates said low resistance layer; filling said first and second openings and said gate opening and anode opening with metal, the metal in said first opening and in said gate opening forming a gate of the HMET device and the metal in the second opening and in the anode opening forming an anode of the Schottky diode; forming first and second metal contacts on said barrier layer abutting at least edges of said low resistance layer, the metal first and second contacts being disposed spaced a distance from a projecting portion of the gate metal; and forming third and forth metal contacts on said barrier layer abutting at least edges of said low resistance layer, the metal third and second forth contacts being disposed spaced a distance from the anode metal.

A method of making a diode comprising: forming a metallic anode structure; forming a 2DEG carrier region disposed laterally of said anode structure, the formed 2DEG carrier region having a proximate edge at a first end of said 2DEG carrier region, the first edge being in physical contact with said metallic anode structure, said 2DEG carrier region being formed with a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; 629607-1 Response to Final Official Action Dated Apri l 19, 2016 USSN 14/464,077 Page forming a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; and forming a metallic cathode structure in contact with said low resistance doped semiconductor region.

A method of making an integrated circuit, the integrated circuit including at least one transistor and at least one diode, the method of making the integrated circuit comprising: forming a metallic anode structure; forming an 2DEG carrier region disposed laterally of said anode structure, the formed 2DEG carrier region having a proximate edge at a first end of said 2DEG carrier region, the first edge being in physical contact with said metallic anode structure, said 2DEG carrier region being formed with a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; forming a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; forming a metallic cathode structure in contact with said low resistance doped semiconductor region; forming a T-shaped gate having a leg which projects from a head portion of said T-shaped gate; 629607-1 Response to Final Official Action Dated Apri l 19, 2016 USSN 14/464,077 Page 6 forming another 2DEG carrier region disposed under said leg of said T-shaped gate; forming second and third low resistance doped semiconductor regions disposed laterally of said third low resistance doped semiconductor regions said another 2DEG carrier region; forming a metallic respectively with said second and third low resistance carrier region, said low resistance doped semiconductor 2DEG carrier region, said another 2DEG carrier doped semiconductor regions all being supported

Claims 18 -26. Cancelled. canceled another 2DEG carrier region, the second and each having an edge in contact with an edge of source and drain electrodes in contact doped semiconductor regions; said 2DEG region being disposed laterally of said region and said second and third low resistance by a common substrate.

Claims 1 -9. Cancelled. canceled

A method of making a HEMT and Schottky diode integrated circuit device comprising the steps of: providing a substrate; disposing a back barrier layer on said substrate; disposing a channel layer on said back barrier layer; disposing a top barrier layer on said channel layer; optionally forming a cap layer on said top barrier layer; depositing a first mask over at least said back layer, said channel layer and said top barrier layer and patterning same to define two regions of said first mask, one region of which is used in forming the HEMT and the other region of which will is used in forming said Schottky diode; removing at least said channel layer and said top barrier layer where not protected by said two regions of said first mask to thereby define edges in said channel layer and in said top barrier layer; depositing a second mask in regions not projected by said first mask and removing said two regions of said first mask to thereby form two openings in said second mask, a first one of said opening being associated with the HEMT device and the second one of the openings being associated with the Schottky diode; forming sidewall spacers on exposed sidewalls of said first and second openings; 629607-1 Response to Final Official Action Dated Apri l 19, 2016 USSN 14/464,077 Page 3 increasing the depth of a portion of the first opening as needed so that a gate opening between the sidewall idcway spacers in said first opening meets said top SVG 14464077.07-18-2016.IQSRR₆K₈RXEAPX3.CLM.2.7.358.623.380.647.svg 0.08 0.073 Chemistry Black and white barrier layer or the optionally formed cap layer; increasing the depth of a portion of the second opening as needed so that an anode opening between the sidewall SVG 14464077.07-18-2016.IQSRR₆K₈RXEAPX3.CLM.2.11.628.973.650.997.svg 0.08 0.073 Chemistry Black and white idcway spacers in said second opening at least penetrates said low resistance layer; filling said first and second openings and said gate opening and anode opening with metal, the metal in said first opening and in said gate opening forming a gate of the HMET device and the metal in the second opening and in the anode opening forming an anode of the Schottky diode; forming first and second metal contacts on said barrier layer abutting at least edges of said low resistance layer, the metal first and second contacts being disposed spaced a distance from a projecting portion of the gate metal; and forming third and forth metal contacts on said barrier layer abutting at least edges of said low resistance layer, the metal third and second forth contacts being disposed spaced a distance from the anode metal.

A method of making a diode comprising: forming a metallic anode structure; forming a 2DEG carrier region disposed laterally of said anode structure, the formed 2DEG carrier region having a proximate edge at a first end of said 2DEG carrier region, the first edge being in physical contact with said metallic anode structure, said 2DEG carrier region being formed with a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; 629607-1 Response to Final Official Action Dated Apri l 19, 2016 USSN 14/464,077 Page forming a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; and forming a metallic cathode structure in contact with said low resistance doped semiconductor region.

A method of making an integrated circuit, the integrated circuit including at least one transistor and at least one diode, the method of making the integrated circuit comprising: forming a metallic anode structure; forming an 2DEG carrier region disposed laterally of said anode structure, the formed 2DEG carrier region having a proximate edge at a first end of said 2DEG carrier region, the first edge being in physical contact with said metallic anode structure, said 2DEG carrier region being formed with a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; forming a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; forming a metallic cathode structure in contact with said low resistance doped semiconductor region; forming a T-shaped gate having a leg which projects from a head portion of said T-shaped gate; 629607-1 Response to Final Official Action Dated Apri l 19, 2016 USSN 14/464,077 Page 6 forming another 2DEG carrier region disposed under said leg of said T-shaped gate; forming second and third low resistance doped semiconductor regions disposed laterally of said third low resistance doped semiconductor regions said another 2DEG carrier region; forming a metallic respectively with said second and third low resistance carrier region, said low resistance doped semiconductor 2DEG carrier region, said another 2DEG carrier doped semiconductor regions all being supported

Claims 18 -26. Cancelled. canceled another 2DEG carrier region, the second and each having an edge in contact with an edge of source and drain electrodes in contact doped semiconductor regions; said 2DEG region being disposed laterally of said region and said second and third low resistance by a common substrate.

Claims 1 -9. Cancelled. canceled

A method of making a HEMT and Schottky diode integrated circuit device comprising the steps of: providing a substrate; disposing a back barrier layer on said substrate; disposing a channel layer on said back barrier layer; disposing a top barrier layer on said channel layer; optionally forming a cap layer on said top barrier layer; depositing a first mask over at least said back layer, said channel layer and said top barrier layer and patterning same to define two regions of said first mask, one region of which is used in forming the HEMT and the other region of which will is used in forming said Schottky diode; removing at least said channel layer and said top barrier layer where not protected by said two regions of said first mask to thereby define edges in said channel layer and in said top barrier layer; depositing a second mask in regions not projected by said first mask and removing said two regions of said first mask to thereby form two openings in said second mask, a first one of said opening being associated with the HEMT device and the second one of the openings being associated with the Schottky diode; forming sidewall spacers on exposed sidewalls of said first and second openings; 629607-1 Response to Final Official Action Dated Apri l 19, 2016 USSN 14/464,077 Page 3 increasing the depth of a portion of the first opening as needed so that a gate opening between the sidewall idcway spacers in said first opening meets said top SVG 14464077.07-18-2016.IQSRR₆K₈RXEAPX3.CLM.2.7.358.623.380.647.svg 0.08 0.073 Chemistry Black and white barrier layer or the optionally formed cap layer; increasing the depth of a portion of the second opening as needed so that an anode opening between the sidewall SVG 14464077.07-18-2016.IQSRR₆K₈RXEAPX3.CLM.2.11.628.973.650.997.svg 0.08 0.073 Chemistry Black and white idcway spacers in said second opening at least penetrates said low resistance layer; filling said first and second openings and said gate opening and anode opening with metal, the metal in said first opening and in said gate opening forming a gate of the HMET device and the metal in the second opening and in the anode opening forming an anode of the Schottky diode; forming first and second metal contacts on said barrier layer abutting at least edges of said low resistance layer, the metal first and second contacts being disposed spaced a distance from a projecting portion of the gate metal; and forming third and forth metal contacts on said barrier layer abutting at least edges of said low resistance layer, the metal third and second forth contacts being disposed spaced a distance from the anode metal.

A method of making a diode comprising: forming a metallic anode structure; forming a 2DEG carrier region disposed laterally of said anode structure, the formed 2DEG carrier region having a proximate edge at a first end of said 2DEG carrier region, the first edge being in physical contact with said metallic anode structure, said 2DEG carrier region being formed with a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; 629607-1 Response to Final Official Action Dated Apri l 19, 2016 USSN 14/464,077 Page forming a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; and forming a metallic cathode structure in contact with said low resistance doped semiconductor region.

A method of making an integrated circuit, the integrated circuit including at least one transistor and at least one diode, the method of making the integrated circuit comprising: forming a metallic anode structure; forming an 2DEG carrier region disposed laterally of said anode structure, the formed 2DEG carrier region having a proximate edge at a first end of said 2DEG carrier region, the first edge being in physical contact with said metallic anode structure, said 2DEG carrier region being formed with a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; forming a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; forming a metallic cathode structure in contact with said low resistance doped semiconductor region; forming a T-shaped gate having a leg which projects from a head portion of said T-shaped gate; 629607-1 Response to Final Official Action Dated Apri l 19, 2016 USSN 14/464,077 Page 6 forming another 2DEG carrier region disposed under said leg of said T-shaped gate; forming second and third low resistance doped semiconductor regions disposed laterally of said third low resistance doped semiconductor regions said another 2DEG carrier region; forming a metallic respectively with said second and third low resistance carrier region, said low resistance doped semiconductor 2DEG carrier region, said another 2DEG carrier doped semiconductor regions all being supported

Claims 18 -26. Cancelled. canceled another 2DEG carrier region, the second and each having an edge in contact with an edge of source and drain electrodes in contact doped semiconductor regions; said 2DEG region being disposed laterally of said region and said second and third low resistance by a common substrate.