Patent
US 10,985,259GaN HEMT DEVICE STRUCTURE AND METHOD OF FABRICATION
Thomas MACELWEE
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,985,259Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabrication of a GaN H EMT device structure as defined in claim 10 comprising: providing a substrate; growing an epitaxial layer stack on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN channel layer and an overlying A lx Gai- x N barrier layer to form a 2DEG channel region; providing a passivation layer over the epitaxial layer stack and selectively removing the passivation layer from a gate region to define a gate slot exposing a surface of the Al xGai-x N barrier layer; digitally etching said surface of the Al x Gai -x N barrier layer to thin the Al x Gai -x N barrier layer within the gate slot to provide a gate slot having steep sidewalls and a surface of a first thickness of the Al x Gai -x N barrier layer at a bottom of the gate slot; and selectively providing p-GaN on said surface of the first thickness of the A lx Gai- x N barrier layer by selective area growth to form a p-GaN mesa within the gate slot; and defining openings through the passivation layer to source and drain regions and providing source and drain electrodes thereon, and providing a gate electrode on the p-GaN mesa. Currently amended
The method of claim 1, wherein the dielectric passivation layer has a thickness and composition that forms a p-dopant diffusion barrier. Previously presented
The method of claim 1, wherein selective area growth of p-GaN comprises a low temperature growth process at a temperature below 950C, which forms p-GaN on said surface of the A lx Gai-x N barrier layer within the gate slot and forms polycrystalline p-GaN extending over the passivation layer, the polycrystalline p-GaN extending over the masking layer then being removed, leaving the p-GaN mesa within the gate slot. Previously presented
The method of claim 1, further comprising a step of cleaning said surface of the A lx Gai- x N barrier layer in the gate slot before selective area growth of p-GaN in the gate slot. Previously presented
Canceled
Canceled
Canceled
A GaN H EMT device structure, comprising: a substrate; an epitaxial layer stack grown on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN layer and an overlying Al x Gai -x N barrier layer to form a 2DEG channel region; a passivation layer formed on the A lx Gai- x N barrier layer, a gate slot defined in a gate region, the gate slot extending through the passivation layer into the A lx Gai- x N barrier layer, the gate slot having steep sidewalls and a bottom of the gate slot being a surface defined by a first thickness of the Al xGai-x N barrier la y er within the gate slot; source and drain openings through the passivation layer defined on source and drain regions of the Al xGai-x N barrier layer; a p-doped GaN mesa on said surface of the first thickness of the Al x Gai -x N barrier layer within the gate slot; source and drain electrodes formed on the source and drain regions-a gate electrode formed on the p-doped GaN mesa; wherein the A 1x Gai- x N barrier layer comprises a- said first thickness in the gate region underlying the p-GaN mesa in the gate slot, and a second thickness, greater than the first thickness, in access regions extending between the gate region and the source region and between the gate region and the drain region; and the composition of the A lx Gai -x N barrier layer having an A l% in a range wherein the first thickness provides a specified threshold voltage and the second thickness provides a specified Rdson of the GaN H EMT device structure. Currently amended
The GaN H EMT device structure of claim 10, wherein the passivation layer comprises at least a first layer of a dielectric material that forms a p-dopant diffusion barrier. Previously presented
The GaN H EMT device structure of claim 10, wherein the composition of the Al x Gai -x N barrier layer has an A l% in a range of 15 % to 25 %. Previously presented
A method of fabrication of the GaN HEMT device structure as defined in claim 20, comprising: providing a substrate; growing an epitaxial layer stack on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN channel layer and an overlying A lx Gai -x N barrier layer to form a 2DEG channel region, wherein the A lx Gai -x N barrier layer comprises a first thickness having a first A l%, and a second thickness having a second A l%, greater than the first Al %; providing a passivation layer over the epitaxial layer stack and selectively removing the passivation layer in a gate region to define a gate slot exposing a surface of the A lx Gai- x N barrier layer; digitally etching said surface of the Al x Gai -x N barrier layer to remove the second thickness of the Al x Gai -x N barrier layer within the gate slot to provide a gate slot having steep sidewalls and a surface of the first thickness of the Al x Gai -x N barrier layer at a bottom of the gate slot; selectively providing p-GaN on said surface of the first thickness Al xGai-x N barrier layer by selective area growth to form a p-GaN mesa within the gate slot; defining openings through the passivation layer to source and drain regions and providing source and drain electrodes thereon, and providing a gate electrode on the p-GaN mesa. Currently amended
The method of claim 15, comprising selecting the first A l% and the first thickness of the Al x Gai -x N barrier layer to provide a specified threshold voltage for E-mode operation, and selecting the second A l% and the second thickness of the A lx Gai- x N barrier layer to provide a specified Rdson and dynamic Rdson of the GaN HEMT. Previously presented
A G aN H EMT device structure comprising: a substrate; an epitaxial layer stack grown on the substrate, the epitaxial layer stack comprising a buffer layer and a G aN heterostructure comprising a G aN layer and an overlying A lxGai-x N barrier layer to form a 2DEG channel region, wherein the A lxG ai- x N barrier layer comprises a first thickness having a first A l%, and a second thickness having a second A l%, greater than the first Al %; a passivation layer formed on the A lxGai-x N barrier layer having a gate slot defined on a gate region of the Al xGai-x N barrier layer, the gate slot extending through the passivation layer into the AlxGai-x N barrier layer, the gate slot having steep sidewalls and a bottom of the gate slot being defined by a surface of the first thickness of the Al xGai-x N barrier layer; source and drain openings defined through the passivation layer on source and drain regions of A lxGai-x N ba rri er layer; a p-doped G aN mesa formed on a- said surface of the first thickness of the A lxG ai- x N ba rri er layer within the gate slot; source and drain electrodes formed on source and drain regions a gate electrode formed on the p- doped G aN mesa; and SVG 16212755.09-22-2020.KFE₁PV₅HRXEAPX1.CLM.1.svg 0.16 6.51 Black and white,, t wherein the A lxG ai- x N barrier layer comprises said first thickness in the gate region underlying the p-G aN mesa in the gate slot and comprises said first and second thicknesses in access regions extending between the gate region and the source region and between the gate region and the drain region. Currently amended
The G aN H EMT device structure of claim 20, wherein the first A l% and the first thickness of the A lxGai-x N barrier layer provide a specified threshold voltage for E- mode operation, and the second A l% and the second thickness of the Al xGai-x N barrier layer provide a specified Rdson and dynamic Rdson of the G aN H EMT device structure. Previously presented
The GaN H EMT device structure of claim 20, wherein the first A l% is in the range from % to 18 % and the first thickness of the A lx Gai- x N barrier layer is in the range 1 5 nm to 2 0 nm to provide a specified threshold voltage for E-mode operation, and the second Al% is in the range from 20 % to 25 % and the second thickness of the Al x Gai -x N barrier layer is in the range from 5 nm to lO nm to provide a specified Rdson and dynamic Rdson of the GaN HEMT. Previously presented
The GaN H EMT device structure of claim 20, wherein the passivation layer comprises at least a first layer of a dielectric material of a thickness that forms a p-dopant diffusion barrier. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT device structure (single-thickness barrier variant)
Materials described outside the worked examples.
GaN channel layer
GaN
AlxGa₁-xN barrier layer
AlxGa₁-xN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
E-mode threshold voltage at least 1.3V | ≥ 1.3 | — |
E-mode threshold voltage range 1.3V to 1.6V or more | 1.3–1.6 | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,985,259Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabrication of a GaN H EMT device structure as defined in claim 10 comprising: providing a substrate; growing an epitaxial layer stack on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN channel layer and an overlying A lx Gai- x N barrier layer to form a 2DEG channel region; providing a passivation layer over the epitaxial layer stack and selectively removing the passivation layer from a gate region to define a gate slot exposing a surface of the Al xGai-x N barrier layer; digitally etching said surface of the Al x Gai -x N barrier layer to thin the Al x Gai -x N barrier layer within the gate slot to provide a gate slot having steep sidewalls and a surface of a first thickness of the Al x Gai -x N barrier layer at a bottom of the gate slot; and selectively providing p-GaN on said surface of the first thickness of the A lx Gai- x N barrier layer by selective area growth to form a p-GaN mesa within the gate slot; and defining openings through the passivation layer to source and drain regions and providing source and drain electrodes thereon, and providing a gate electrode on the p-GaN mesa. Currently amended
The method of claim 1, wherein the dielectric passivation layer has a thickness and composition that forms a p-dopant diffusion barrier. Previously presented
The method of claim 1, wherein selective area growth of p-GaN comprises a low temperature growth process at a temperature below 950C, which forms p-GaN on said surface of the A lx Gai-x N barrier layer within the gate slot and forms polycrystalline p-GaN extending over the passivation layer, the polycrystalline p-GaN extending over the masking layer then being removed, leaving the p-GaN mesa within the gate slot. Previously presented
The method of claim 1, further comprising a step of cleaning said surface of the A lx Gai- x N barrier layer in the gate slot before selective area growth of p-GaN in the gate slot. Previously presented
Canceled
Canceled
Canceled
A GaN H EMT device structure, comprising: a substrate; an epitaxial layer stack grown on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN layer and an overlying Al x Gai -x N barrier layer to form a 2DEG channel region; a passivation layer formed on the A lx Gai- x N barrier layer, a gate slot defined in a gate region, the gate slot extending through the passivation layer into the A lx Gai- x N barrier layer, the gate slot having steep sidewalls and a bottom of the gate slot being a surface defined by a first thickness of the Al xGai-x N barrier la y er within the gate slot; source and drain openings through the passivation layer defined on source and drain regions of the Al xGai-x N barrier layer; a p-doped GaN mesa on said surface of the first thickness of the Al x Gai -x N barrier layer within the gate slot; source and drain electrodes formed on the source and drain regions-a gate electrode formed on the p-doped GaN mesa; wherein the A 1x Gai- x N barrier layer comprises a- said first thickness in the gate region underlying the p-GaN mesa in the gate slot, and a second thickness, greater than the first thickness, in access regions extending between the gate region and the source region and between the gate region and the drain region; and the composition of the A lx Gai -x N barrier layer having an A l% in a range wherein the first thickness provides a specified threshold voltage and the second thickness provides a specified Rdson of the GaN H EMT device structure. Currently amended
The GaN H EMT device structure of claim 10, wherein the passivation layer comprises at least a first layer of a dielectric material that forms a p-dopant diffusion barrier. Previously presented
The GaN H EMT device structure of claim 10, wherein the composition of the Al x Gai -x N barrier layer has an A l% in a range of 15 % to 25 %. Previously presented
A method of fabrication of the GaN HEMT device structure as defined in claim 20, comprising: providing a substrate; growing an epitaxial layer stack on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN channel layer and an overlying A lx Gai -x N barrier layer to form a 2DEG channel region, wherein the A lx Gai -x N barrier layer comprises a first thickness having a first A l%, and a second thickness having a second A l%, greater than the first Al %; providing a passivation layer over the epitaxial layer stack and selectively removing the passivation layer in a gate region to define a gate slot exposing a surface of the A lx Gai- x N barrier layer; digitally etching said surface of the Al x Gai -x N barrier layer to remove the second thickness of the Al x Gai -x N barrier layer within the gate slot to provide a gate slot having steep sidewalls and a surface of the first thickness of the Al x Gai -x N barrier layer at a bottom of the gate slot; selectively providing p-GaN on said surface of the first thickness Al xGai-x N barrier layer by selective area growth to form a p-GaN mesa within the gate slot; defining openings through the passivation layer to source and drain regions and providing source and drain electrodes thereon, and providing a gate electrode on the p-GaN mesa. Currently amended
The method of claim 15, comprising selecting the first A l% and the first thickness of the Al x Gai -x N barrier layer to provide a specified threshold voltage for E-mode operation, and selecting the second A l% and the second thickness of the A lx Gai- x N barrier layer to provide a specified Rdson and dynamic Rdson of the GaN HEMT. Previously presented
A G aN H EMT device structure comprising: a substrate; an epitaxial layer stack grown on the substrate, the epitaxial layer stack comprising a buffer layer and a G aN heterostructure comprising a G aN layer and an overlying A lxGai-x N barrier layer to form a 2DEG channel region, wherein the A lxG ai- x N barrier layer comprises a first thickness having a first A l%, and a second thickness having a second A l%, greater than the first Al %; a passivation layer formed on the A lxGai-x N barrier layer having a gate slot defined on a gate region of the Al xGai-x N barrier layer, the gate slot extending through the passivation layer into the AlxGai-x N barrier layer, the gate slot having steep sidewalls and a bottom of the gate slot being defined by a surface of the first thickness of the Al xGai-x N barrier layer; source and drain openings defined through the passivation layer on source and drain regions of A lxGai-x N ba rri er layer; a p-doped G aN mesa formed on a- said surface of the first thickness of the A lxG ai- x N ba rri er layer within the gate slot; source and drain electrodes formed on source and drain regions a gate electrode formed on the p- doped G aN mesa; and SVG 16212755.09-22-2020.KFE₁PV₅HRXEAPX1.CLM.1.svg 0.16 6.51 Black and white,, t wherein the A lxG ai- x N barrier layer comprises said first thickness in the gate region underlying the p-G aN mesa in the gate slot and comprises said first and second thicknesses in access regions extending between the gate region and the source region and between the gate region and the drain region. Currently amended
The G aN H EMT device structure of claim 20, wherein the first A l% and the first thickness of the A lxGai-x N barrier layer provide a specified threshold voltage for E- mode operation, and the second A l% and the second thickness of the Al xGai-x N barrier layer provide a specified Rdson and dynamic Rdson of the G aN H EMT device structure. Previously presented
The GaN H EMT device structure of claim 20, wherein the first A l% is in the range from % to 18 % and the first thickness of the A lx Gai- x N barrier layer is in the range 1 5 nm to 2 0 nm to provide a specified threshold voltage for E-mode operation, and the second Al% is in the range from 20 % to 25 % and the second thickness of the Al x Gai -x N barrier layer is in the range from 5 nm to lO nm to provide a specified Rdson and dynamic Rdson of the GaN HEMT. Previously presented
The GaN H EMT device structure of claim 20, wherein the passivation layer comprises at least a first layer of a dielectric material of a thickness that forms a p-dopant diffusion barrier. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT device structure (single-thickness barrier variant)
Materials described outside the worked examples.
GaN channel layer
GaN
AlxGa₁-xN barrier layer
AlxGa₁-xN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
E-mode threshold voltage at least 1.3V | ≥ 1.3 | — |
E-mode threshold voltage range 1.3V to 1.6V or more | 1.3–1.6 | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,985,259Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabrication of a GaN H EMT device structure as defined in claim 10 comprising: providing a substrate; growing an epitaxial layer stack on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN channel layer and an overlying A lx Gai- x N barrier layer to form a 2DEG channel region; providing a passivation layer over the epitaxial layer stack and selectively removing the passivation layer from a gate region to define a gate slot exposing a surface of the Al xGai-x N barrier layer; digitally etching said surface of the Al x Gai -x N barrier layer to thin the Al x Gai -x N barrier layer within the gate slot to provide a gate slot having steep sidewalls and a surface of a first thickness of the Al x Gai -x N barrier layer at a bottom of the gate slot; and selectively providing p-GaN on said surface of the first thickness of the A lx Gai- x N barrier layer by selective area growth to form a p-GaN mesa within the gate slot; and defining openings through the passivation layer to source and drain regions and providing source and drain electrodes thereon, and providing a gate electrode on the p-GaN mesa. Currently amended
The method of claim 1, wherein the dielectric passivation layer has a thickness and composition that forms a p-dopant diffusion barrier. Previously presented
The method of claim 1, wherein selective area growth of p-GaN comprises a low temperature growth process at a temperature below 950C, which forms p-GaN on said surface of the A lx Gai-x N barrier layer within the gate slot and forms polycrystalline p-GaN extending over the passivation layer, the polycrystalline p-GaN extending over the masking layer then being removed, leaving the p-GaN mesa within the gate slot. Previously presented
The method of claim 1, further comprising a step of cleaning said surface of the A lx Gai- x N barrier layer in the gate slot before selective area growth of p-GaN in the gate slot. Previously presented
Canceled
Canceled
Canceled
A GaN H EMT device structure, comprising: a substrate; an epitaxial layer stack grown on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN layer and an overlying Al x Gai -x N barrier layer to form a 2DEG channel region; a passivation layer formed on the A lx Gai- x N barrier layer, a gate slot defined in a gate region, the gate slot extending through the passivation layer into the A lx Gai- x N barrier layer, the gate slot having steep sidewalls and a bottom of the gate slot being a surface defined by a first thickness of the Al xGai-x N barrier la y er within the gate slot; source and drain openings through the passivation layer defined on source and drain regions of the Al xGai-x N barrier layer; a p-doped GaN mesa on said surface of the first thickness of the Al x Gai -x N barrier layer within the gate slot; source and drain electrodes formed on the source and drain regions-a gate electrode formed on the p-doped GaN mesa; wherein the A 1x Gai- x N barrier layer comprises a- said first thickness in the gate region underlying the p-GaN mesa in the gate slot, and a second thickness, greater than the first thickness, in access regions extending between the gate region and the source region and between the gate region and the drain region; and the composition of the A lx Gai -x N barrier layer having an A l% in a range wherein the first thickness provides a specified threshold voltage and the second thickness provides a specified Rdson of the GaN H EMT device structure. Currently amended
The GaN H EMT device structure of claim 10, wherein the passivation layer comprises at least a first layer of a dielectric material that forms a p-dopant diffusion barrier. Previously presented
The GaN H EMT device structure of claim 10, wherein the composition of the Al x Gai -x N barrier layer has an A l% in a range of 15 % to 25 %. Previously presented
A method of fabrication of the GaN HEMT device structure as defined in claim 20, comprising: providing a substrate; growing an epitaxial layer stack on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN channel layer and an overlying A lx Gai -x N barrier layer to form a 2DEG channel region, wherein the A lx Gai -x N barrier layer comprises a first thickness having a first A l%, and a second thickness having a second A l%, greater than the first Al %; providing a passivation layer over the epitaxial layer stack and selectively removing the passivation layer in a gate region to define a gate slot exposing a surface of the A lx Gai- x N barrier layer; digitally etching said surface of the Al x Gai -x N barrier layer to remove the second thickness of the Al x Gai -x N barrier layer within the gate slot to provide a gate slot having steep sidewalls and a surface of the first thickness of the Al x Gai -x N barrier layer at a bottom of the gate slot; selectively providing p-GaN on said surface of the first thickness Al xGai-x N barrier layer by selective area growth to form a p-GaN mesa within the gate slot; defining openings through the passivation layer to source and drain regions and providing source and drain electrodes thereon, and providing a gate electrode on the p-GaN mesa. Currently amended
The method of claim 15, comprising selecting the first A l% and the first thickness of the Al x Gai -x N barrier layer to provide a specified threshold voltage for E-mode operation, and selecting the second A l% and the second thickness of the A lx Gai- x N barrier layer to provide a specified Rdson and dynamic Rdson of the GaN HEMT. Previously presented
A G aN H EMT device structure comprising: a substrate; an epitaxial layer stack grown on the substrate, the epitaxial layer stack comprising a buffer layer and a G aN heterostructure comprising a G aN layer and an overlying A lxGai-x N barrier layer to form a 2DEG channel region, wherein the A lxG ai- x N barrier layer comprises a first thickness having a first A l%, and a second thickness having a second A l%, greater than the first Al %; a passivation layer formed on the A lxGai-x N barrier layer having a gate slot defined on a gate region of the Al xGai-x N barrier layer, the gate slot extending through the passivation layer into the AlxGai-x N barrier layer, the gate slot having steep sidewalls and a bottom of the gate slot being defined by a surface of the first thickness of the Al xGai-x N barrier layer; source and drain openings defined through the passivation layer on source and drain regions of A lxGai-x N ba rri er layer; a p-doped G aN mesa formed on a- said surface of the first thickness of the A lxG ai- x N ba rri er layer within the gate slot; source and drain electrodes formed on source and drain regions a gate electrode formed on the p- doped G aN mesa; and SVG 16212755.09-22-2020.KFE₁PV₅HRXEAPX1.CLM.1.svg 0.16 6.51 Black and white,, t wherein the A lxG ai- x N barrier layer comprises said first thickness in the gate region underlying the p-G aN mesa in the gate slot and comprises said first and second thicknesses in access regions extending between the gate region and the source region and between the gate region and the drain region. Currently amended
The G aN H EMT device structure of claim 20, wherein the first A l% and the first thickness of the A lxGai-x N barrier layer provide a specified threshold voltage for E- mode operation, and the second A l% and the second thickness of the Al xGai-x N barrier layer provide a specified Rdson and dynamic Rdson of the G aN H EMT device structure. Previously presented
The GaN H EMT device structure of claim 20, wherein the first A l% is in the range from % to 18 % and the first thickness of the A lx Gai- x N barrier layer is in the range 1 5 nm to 2 0 nm to provide a specified threshold voltage for E-mode operation, and the second Al% is in the range from 20 % to 25 % and the second thickness of the Al x Gai -x N barrier layer is in the range from 5 nm to lO nm to provide a specified Rdson and dynamic Rdson of the GaN HEMT. Previously presented
The GaN H EMT device structure of claim 20, wherein the passivation layer comprises at least a first layer of a dielectric material of a thickness that forms a p-dopant diffusion barrier. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT device structure (single-thickness barrier variant)
Materials described outside the worked examples.
GaN channel layer
GaN
AlxGa₁-xN barrier layer
AlxGa₁-xN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
E-mode threshold voltage at least 1.3V | ≥ 1.3 | — |
E-mode threshold voltage range 1.3V to 1.6V or more | 1.3–1.6 | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,985,259Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabrication of a GaN H EMT device structure as defined in claim 10 comprising: providing a substrate; growing an epitaxial layer stack on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN channel layer and an overlying A lx Gai- x N barrier layer to form a 2DEG channel region; providing a passivation layer over the epitaxial layer stack and selectively removing the passivation layer from a gate region to define a gate slot exposing a surface of the Al xGai-x N barrier layer; digitally etching said surface of the Al x Gai -x N barrier layer to thin the Al x Gai -x N barrier layer within the gate slot to provide a gate slot having steep sidewalls and a surface of a first thickness of the Al x Gai -x N barrier layer at a bottom of the gate slot; and selectively providing p-GaN on said surface of the first thickness of the A lx Gai- x N barrier layer by selective area growth to form a p-GaN mesa within the gate slot; and defining openings through the passivation layer to source and drain regions and providing source and drain electrodes thereon, and providing a gate electrode on the p-GaN mesa. Currently amended
The method of claim 1, wherein the dielectric passivation layer has a thickness and composition that forms a p-dopant diffusion barrier. Previously presented
The method of claim 1, wherein selective area growth of p-GaN comprises a low temperature growth process at a temperature below 950C, which forms p-GaN on said surface of the A lx Gai-x N barrier layer within the gate slot and forms polycrystalline p-GaN extending over the passivation layer, the polycrystalline p-GaN extending over the masking layer then being removed, leaving the p-GaN mesa within the gate slot. Previously presented
The method of claim 1, further comprising a step of cleaning said surface of the A lx Gai- x N barrier layer in the gate slot before selective area growth of p-GaN in the gate slot. Previously presented
Canceled
Canceled
Canceled
A GaN H EMT device structure, comprising: a substrate; an epitaxial layer stack grown on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN layer and an overlying Al x Gai -x N barrier layer to form a 2DEG channel region; a passivation layer formed on the A lx Gai- x N barrier layer, a gate slot defined in a gate region, the gate slot extending through the passivation layer into the A lx Gai- x N barrier layer, the gate slot having steep sidewalls and a bottom of the gate slot being a surface defined by a first thickness of the Al xGai-x N barrier la y er within the gate slot; source and drain openings through the passivation layer defined on source and drain regions of the Al xGai-x N barrier layer; a p-doped GaN mesa on said surface of the first thickness of the Al x Gai -x N barrier layer within the gate slot; source and drain electrodes formed on the source and drain regions-a gate electrode formed on the p-doped GaN mesa; wherein the A 1x Gai- x N barrier layer comprises a- said first thickness in the gate region underlying the p-GaN mesa in the gate slot, and a second thickness, greater than the first thickness, in access regions extending between the gate region and the source region and between the gate region and the drain region; and the composition of the A lx Gai -x N barrier layer having an A l% in a range wherein the first thickness provides a specified threshold voltage and the second thickness provides a specified Rdson of the GaN H EMT device structure. Currently amended
The GaN H EMT device structure of claim 10, wherein the passivation layer comprises at least a first layer of a dielectric material that forms a p-dopant diffusion barrier. Previously presented
The GaN H EMT device structure of claim 10, wherein the composition of the Al x Gai -x N barrier layer has an A l% in a range of 15 % to 25 %. Previously presented
A method of fabrication of the GaN HEMT device structure as defined in claim 20, comprising: providing a substrate; growing an epitaxial layer stack on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN channel layer and an overlying A lx Gai -x N barrier layer to form a 2DEG channel region, wherein the A lx Gai -x N barrier layer comprises a first thickness having a first A l%, and a second thickness having a second A l%, greater than the first Al %; providing a passivation layer over the epitaxial layer stack and selectively removing the passivation layer in a gate region to define a gate slot exposing a surface of the A lx Gai- x N barrier layer; digitally etching said surface of the Al x Gai -x N barrier layer to remove the second thickness of the Al x Gai -x N barrier layer within the gate slot to provide a gate slot having steep sidewalls and a surface of the first thickness of the Al x Gai -x N barrier layer at a bottom of the gate slot; selectively providing p-GaN on said surface of the first thickness Al xGai-x N barrier layer by selective area growth to form a p-GaN mesa within the gate slot; defining openings through the passivation layer to source and drain regions and providing source and drain electrodes thereon, and providing a gate electrode on the p-GaN mesa. Currently amended
The method of claim 15, comprising selecting the first A l% and the first thickness of the Al x Gai -x N barrier layer to provide a specified threshold voltage for E-mode operation, and selecting the second A l% and the second thickness of the A lx Gai- x N barrier layer to provide a specified Rdson and dynamic Rdson of the GaN HEMT. Previously presented
A G aN H EMT device structure comprising: a substrate; an epitaxial layer stack grown on the substrate, the epitaxial layer stack comprising a buffer layer and a G aN heterostructure comprising a G aN layer and an overlying A lxGai-x N barrier layer to form a 2DEG channel region, wherein the A lxG ai- x N barrier layer comprises a first thickness having a first A l%, and a second thickness having a second A l%, greater than the first Al %; a passivation layer formed on the A lxGai-x N barrier layer having a gate slot defined on a gate region of the Al xGai-x N barrier layer, the gate slot extending through the passivation layer into the AlxGai-x N barrier layer, the gate slot having steep sidewalls and a bottom of the gate slot being defined by a surface of the first thickness of the Al xGai-x N barrier layer; source and drain openings defined through the passivation layer on source and drain regions of A lxGai-x N ba rri er layer; a p-doped G aN mesa formed on a- said surface of the first thickness of the A lxG ai- x N ba rri er layer within the gate slot; source and drain electrodes formed on source and drain regions a gate electrode formed on the p- doped G aN mesa; and SVG 16212755.09-22-2020.KFE₁PV₅HRXEAPX1.CLM.1.svg 0.16 6.51 Black and white,, t wherein the A lxG ai- x N barrier layer comprises said first thickness in the gate region underlying the p-G aN mesa in the gate slot and comprises said first and second thicknesses in access regions extending between the gate region and the source region and between the gate region and the drain region. Currently amended
The G aN H EMT device structure of claim 20, wherein the first A l% and the first thickness of the A lxGai-x N barrier layer provide a specified threshold voltage for E- mode operation, and the second A l% and the second thickness of the Al xGai-x N barrier layer provide a specified Rdson and dynamic Rdson of the G aN H EMT device structure. Previously presented
The GaN H EMT device structure of claim 20, wherein the first A l% is in the range from % to 18 % and the first thickness of the A lx Gai- x N barrier layer is in the range 1 5 nm to 2 0 nm to provide a specified threshold voltage for E-mode operation, and the second Al% is in the range from 20 % to 25 % and the second thickness of the Al x Gai -x N barrier layer is in the range from 5 nm to lO nm to provide a specified Rdson and dynamic Rdson of the GaN HEMT. Previously presented
The GaN H EMT device structure of claim 20, wherein the passivation layer comprises at least a first layer of a dielectric material of a thickness that forms a p-dopant diffusion barrier. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT device structure (single-thickness barrier variant)
Materials described outside the worked examples.
GaN channel layer
GaN
AlxGa₁-xN barrier layer
AlxGa₁-xN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
E-mode threshold voltage at least 1.3V | ≥ 1.3 | — |
E-mode threshold voltage range 1.3V to 1.6V or more | 1.3–1.6 | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
GaN HEMT device structure (dual Al% barrier variant)
dielectric passivation layer
magnesium p-dopant
Mg
buffer layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
| 1.3–1.6 V |
| — |
Thickness | 15–20 nm | — |
Thickness | 5–10 nm | — |
Voltage | ≥ 1.3 V | — |
Voltage | ≥ 1.6 V | — |
GaN HEMT device structure (dual Al% barrier variant)
dielectric passivation layer
magnesium p-dopant
Mg
buffer layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
| 1.3–1.6 V |
| — |
Thickness | 15–20 nm | — |
Thickness | 5–10 nm | — |
Voltage | ≥ 1.3 V | — |
Voltage | ≥ 1.6 V | — |
GaN HEMT device structure (dual Al% barrier variant)
dielectric passivation layer
magnesium p-dopant
Mg
buffer layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
| 1.3–1.6 V |
| — |
Thickness | 15–20 nm | — |
Thickness | 5–10 nm | — |
Voltage | ≥ 1.3 V | — |
Voltage | ≥ 1.6 V | — |
GaN HEMT device structure (dual Al% barrier variant)
dielectric passivation layer
magnesium p-dopant
Mg
buffer layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
| 1.3–1.6 V |
| — |
Thickness | 15–20 nm | — |
Thickness | 5–10 nm | — |
Voltage | ≥ 1.3 V | — |
Voltage | ≥ 1.6 V | — |