Patent
US 11,557,682LOW TURN-ON VOLTAGE GaN DIODES HAVING ANODE METAL WITH CONSISTENT CRYSTAL ORIENTATION AND PREPARATION METHOD THEREOF
Jing Ning
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,557,682Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As shown in
FIG.2 is a flowchart of a method for preparing a low turn-on voltage GaN diode having an anode metal with a consistent crystal orientation provided by an …
FIG. 3f. Wherein, the process conditions f o r etching the Si O 2 dielectric layer are as follows: gas flow of carbon tetrafluoride (CF 4): 15 s cc m (standard …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) diode, comprising: an anode that includes a stack of metals of tungsten (W) or molybdenum (Mo) and gold (Au) each with a same crystal orientation the metal of W or Mo having a thickness of 20-120 nanometers (nm) and the Au having a thickness of 100-200 nm; a plurality of layers that include a substrate layer, a GaN buffer layer, a GaN channel layer and an aluminum gallium nitride (AlGaN) barrier layer which are arranged in sequence relative to each other; a cathode arranged on the AlGaN barrier layer, wherein the cathode includes a stack of metals of titanium (Ti), aluminum (Al), nickel (Ni) and gold (Au); a groove arranged in the GaN channel layer and the AlGaN barrier layer, the anode being provided on a bottom and a side wall of the groove and part of the AlGaN barrier layer; a dielectric layer provided on an uncovered portion of the AlGaN barrier layer that is not covered by the cathode and the anode, wherein, a contact portion of the anode with the groove and the AlGaN barrier layer is the metal of W or Mo. Currently amended
The GaN diode according to claim 1, wherein the bottom of the groove is located 2-20 nanometers (nm) below an interface between the AlGaN barrier layer and the GaN channel layer. Currently amended
The GaN diode according to claim 1, wherein the dielectric layer is a silicon dioxide (Si O 2) dielectric layer with a thickness of 100-300 nm. Currently amended
Canceled
A method for preparing a low turn-on voltage gallium nitride (GaN) diode having an anode metal with a consistent crystal orientation, wherein comprising steps of: Si: cleaning an epitaxial wafer of an aluminum gallium nitride (AlGaN)/GaN structure; S2: preparing a mesa isolation on the epitaxial wafer; Supplemental Amendment in further response to office action of S3: depositing a titanium (Ti)/aluminum (Al)/nickel (Ni)/gold (Au) metal stack on the epitaxial wafer to form a cathode of a diode; S4: etching an A l GaN barrier layer and a G aN channel layer to below an A l GaN/GaN interface to form a groove, depositing a stack of tungsten (W) or Mo metal and Au metal in the groove and on a part of the AlGaN barrier layer to form an anode of the diode, wherein a contact portion of the anode with the groove and the AlGaN barrier layer is W or Mo metal; S5: depositing a silicon dioxide (SiO 2) dielectric layer on an uncovered portion of the epitaxial wafer and etching a through-hole region to a surface of cathode metal using a reactive ion etching (an R IE) machine. Withdrawn
The method according to claim 5, wherein step S₂ includes: S 21: performing spin coating, baking, photolithography and development on the cleaned epitaxial wafer; S 22: etching an outside portion of a G aN mesa using inductively coupled plastma (I CP); S 23: placing the etched epitaxial wafer into an acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen to form a device mesa isolation. Withdrawn
The method according to claim 5, wherein step S₃ includes: S₃ 1: performing spin coating, baking, photolithography and development on a mesa- isolated epitaxial wafer; S 32: depositing the Ti/Al/Ni/Au metal stack on the epitaxial wafer using an electron beam evaporation equipment; S 33: soaking the epitaxial wafer deposited with the metal stack in an acetone solution to strip metals outside the cathode metal, then placing the stripped epitaxial wafer into the acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen and annealing in a rapid annealing furnace to form the cathode of the diode. Withdrawn
The method according to claim 5, wherein step S₄ includes: S 41: performing spin coating, baking, photolithography and development on the epitaxial wafer with the cathode; S 42: etching the AlGaN barrier layer and the G aN channel layer to 2-20 nm below the AlGaN/G aN interface using an I CP etching machine to form a groove; Supplemental Amendment in further response to office action of S 43: depositing W or Mo metal and a thickness of 2-20 nm in the groove and on a part of the AlGaN barrier layer using a molecular beam epitaxy technology, depositing W or Mo metal with a thickness of 20-100 nm on W or Mo metal with using an electron beam evaporation equipment, and depositing Au metal with a thickness of 100-200 nm on W or Mo metal to form the stack of W or Mo metal and Au metal; S 44: soaking the epitaxial wafer deposited with the metal stack in an acetone solution to strip the metal outside the anode metal, then placing the stripped epitaxial wafer into the acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen to form the anode of the diode. Withdrawn
The method according to claim 5, wherein step S₅ includes: S₅ 1: depositing a SiO 2 dielectric layer with a thickness of 100-300 nm on the uncovered portion of the epitaxial wafer using a plasma enhanced chemical vapor deposition equipment; S 52: performing spin coating, baking, through-hole photolithography and development on the epitaxial wafer with the dielectric layer in sequence, and etching the through-hole region to the surface of the cathode metal using an RIE machine; S 53: placing the etched epitaxial wafer into an acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen to form the low-turn- on voltage GaN diode. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
low turn-on voltage GaN Schottky diode
Materials described outside the worked examples.
tungsten
W
molybdenum
Mo
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3f. Wherein, the process conditions f o r etching the Si O 2 dielectric layer are as follows: gas flow of carbon tetrafluoride (CF 4): 15 s cc m (standard …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–20 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,557,682Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As shown in
FIG.2 is a flowchart of a method for preparing a low turn-on voltage GaN diode having an anode metal with a consistent crystal orientation provided by an …
FIG. 3f. Wherein, the process conditions f o r etching the Si O 2 dielectric layer are as follows: gas flow of carbon tetrafluoride (CF 4): 15 s cc m (standard …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) diode, comprising: an anode that includes a stack of metals of tungsten (W) or molybdenum (Mo) and gold (Au) each with a same crystal orientation the metal of W or Mo having a thickness of 20-120 nanometers (nm) and the Au having a thickness of 100-200 nm; a plurality of layers that include a substrate layer, a GaN buffer layer, a GaN channel layer and an aluminum gallium nitride (AlGaN) barrier layer which are arranged in sequence relative to each other; a cathode arranged on the AlGaN barrier layer, wherein the cathode includes a stack of metals of titanium (Ti), aluminum (Al), nickel (Ni) and gold (Au); a groove arranged in the GaN channel layer and the AlGaN barrier layer, the anode being provided on a bottom and a side wall of the groove and part of the AlGaN barrier layer; a dielectric layer provided on an uncovered portion of the AlGaN barrier layer that is not covered by the cathode and the anode, wherein, a contact portion of the anode with the groove and the AlGaN barrier layer is the metal of W or Mo. Currently amended
The GaN diode according to claim 1, wherein the bottom of the groove is located 2-20 nanometers (nm) below an interface between the AlGaN barrier layer and the GaN channel layer. Currently amended
The GaN diode according to claim 1, wherein the dielectric layer is a silicon dioxide (Si O 2) dielectric layer with a thickness of 100-300 nm. Currently amended
Canceled
A method for preparing a low turn-on voltage gallium nitride (GaN) diode having an anode metal with a consistent crystal orientation, wherein comprising steps of: Si: cleaning an epitaxial wafer of an aluminum gallium nitride (AlGaN)/GaN structure; S2: preparing a mesa isolation on the epitaxial wafer; Supplemental Amendment in further response to office action of S3: depositing a titanium (Ti)/aluminum (Al)/nickel (Ni)/gold (Au) metal stack on the epitaxial wafer to form a cathode of a diode; S4: etching an A l GaN barrier layer and a G aN channel layer to below an A l GaN/GaN interface to form a groove, depositing a stack of tungsten (W) or Mo metal and Au metal in the groove and on a part of the AlGaN barrier layer to form an anode of the diode, wherein a contact portion of the anode with the groove and the AlGaN barrier layer is W or Mo metal; S5: depositing a silicon dioxide (SiO 2) dielectric layer on an uncovered portion of the epitaxial wafer and etching a through-hole region to a surface of cathode metal using a reactive ion etching (an R IE) machine. Withdrawn
The method according to claim 5, wherein step S₂ includes: S 21: performing spin coating, baking, photolithography and development on the cleaned epitaxial wafer; S 22: etching an outside portion of a G aN mesa using inductively coupled plastma (I CP); S 23: placing the etched epitaxial wafer into an acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen to form a device mesa isolation. Withdrawn
The method according to claim 5, wherein step S₃ includes: S₃ 1: performing spin coating, baking, photolithography and development on a mesa- isolated epitaxial wafer; S 32: depositing the Ti/Al/Ni/Au metal stack on the epitaxial wafer using an electron beam evaporation equipment; S 33: soaking the epitaxial wafer deposited with the metal stack in an acetone solution to strip metals outside the cathode metal, then placing the stripped epitaxial wafer into the acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen and annealing in a rapid annealing furnace to form the cathode of the diode. Withdrawn
The method according to claim 5, wherein step S₄ includes: S 41: performing spin coating, baking, photolithography and development on the epitaxial wafer with the cathode; S 42: etching the AlGaN barrier layer and the G aN channel layer to 2-20 nm below the AlGaN/G aN interface using an I CP etching machine to form a groove; Supplemental Amendment in further response to office action of S 43: depositing W or Mo metal and a thickness of 2-20 nm in the groove and on a part of the AlGaN barrier layer using a molecular beam epitaxy technology, depositing W or Mo metal with a thickness of 20-100 nm on W or Mo metal with using an electron beam evaporation equipment, and depositing Au metal with a thickness of 100-200 nm on W or Mo metal to form the stack of W or Mo metal and Au metal; S 44: soaking the epitaxial wafer deposited with the metal stack in an acetone solution to strip the metal outside the anode metal, then placing the stripped epitaxial wafer into the acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen to form the anode of the diode. Withdrawn
The method according to claim 5, wherein step S₅ includes: S₅ 1: depositing a SiO 2 dielectric layer with a thickness of 100-300 nm on the uncovered portion of the epitaxial wafer using a plasma enhanced chemical vapor deposition equipment; S 52: performing spin coating, baking, through-hole photolithography and development on the epitaxial wafer with the dielectric layer in sequence, and etching the through-hole region to the surface of the cathode metal using an RIE machine; S 53: placing the etched epitaxial wafer into an acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen to form the low-turn- on voltage GaN diode. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
low turn-on voltage GaN Schottky diode
Materials described outside the worked examples.
tungsten
W
molybdenum
Mo
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3f. Wherein, the process conditions f o r etching the Si O 2 dielectric layer are as follows: gas flow of carbon tetrafluoride (CF 4): 15 s cc m (standard …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–20 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,557,682Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As shown in
FIG.2 is a flowchart of a method for preparing a low turn-on voltage GaN diode having an anode metal with a consistent crystal orientation provided by an …
FIG. 3f. Wherein, the process conditions f o r etching the Si O 2 dielectric layer are as follows: gas flow of carbon tetrafluoride (CF 4): 15 s cc m (standard …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) diode, comprising: an anode that includes a stack of metals of tungsten (W) or molybdenum (Mo) and gold (Au) each with a same crystal orientation the metal of W or Mo having a thickness of 20-120 nanometers (nm) and the Au having a thickness of 100-200 nm; a plurality of layers that include a substrate layer, a GaN buffer layer, a GaN channel layer and an aluminum gallium nitride (AlGaN) barrier layer which are arranged in sequence relative to each other; a cathode arranged on the AlGaN barrier layer, wherein the cathode includes a stack of metals of titanium (Ti), aluminum (Al), nickel (Ni) and gold (Au); a groove arranged in the GaN channel layer and the AlGaN barrier layer, the anode being provided on a bottom and a side wall of the groove and part of the AlGaN barrier layer; a dielectric layer provided on an uncovered portion of the AlGaN barrier layer that is not covered by the cathode and the anode, wherein, a contact portion of the anode with the groove and the AlGaN barrier layer is the metal of W or Mo. Currently amended
The GaN diode according to claim 1, wherein the bottom of the groove is located 2-20 nanometers (nm) below an interface between the AlGaN barrier layer and the GaN channel layer. Currently amended
The GaN diode according to claim 1, wherein the dielectric layer is a silicon dioxide (Si O 2) dielectric layer with a thickness of 100-300 nm. Currently amended
Canceled
A method for preparing a low turn-on voltage gallium nitride (GaN) diode having an anode metal with a consistent crystal orientation, wherein comprising steps of: Si: cleaning an epitaxial wafer of an aluminum gallium nitride (AlGaN)/GaN structure; S2: preparing a mesa isolation on the epitaxial wafer; Supplemental Amendment in further response to office action of S3: depositing a titanium (Ti)/aluminum (Al)/nickel (Ni)/gold (Au) metal stack on the epitaxial wafer to form a cathode of a diode; S4: etching an A l GaN barrier layer and a G aN channel layer to below an A l GaN/GaN interface to form a groove, depositing a stack of tungsten (W) or Mo metal and Au metal in the groove and on a part of the AlGaN barrier layer to form an anode of the diode, wherein a contact portion of the anode with the groove and the AlGaN barrier layer is W or Mo metal; S5: depositing a silicon dioxide (SiO 2) dielectric layer on an uncovered portion of the epitaxial wafer and etching a through-hole region to a surface of cathode metal using a reactive ion etching (an R IE) machine. Withdrawn
The method according to claim 5, wherein step S₂ includes: S 21: performing spin coating, baking, photolithography and development on the cleaned epitaxial wafer; S 22: etching an outside portion of a G aN mesa using inductively coupled plastma (I CP); S 23: placing the etched epitaxial wafer into an acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen to form a device mesa isolation. Withdrawn
The method according to claim 5, wherein step S₃ includes: S₃ 1: performing spin coating, baking, photolithography and development on a mesa- isolated epitaxial wafer; S 32: depositing the Ti/Al/Ni/Au metal stack on the epitaxial wafer using an electron beam evaporation equipment; S 33: soaking the epitaxial wafer deposited with the metal stack in an acetone solution to strip metals outside the cathode metal, then placing the stripped epitaxial wafer into the acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen and annealing in a rapid annealing furnace to form the cathode of the diode. Withdrawn
The method according to claim 5, wherein step S₄ includes: S 41: performing spin coating, baking, photolithography and development on the epitaxial wafer with the cathode; S 42: etching the AlGaN barrier layer and the G aN channel layer to 2-20 nm below the AlGaN/G aN interface using an I CP etching machine to form a groove; Supplemental Amendment in further response to office action of S 43: depositing W or Mo metal and a thickness of 2-20 nm in the groove and on a part of the AlGaN barrier layer using a molecular beam epitaxy technology, depositing W or Mo metal with a thickness of 20-100 nm on W or Mo metal with using an electron beam evaporation equipment, and depositing Au metal with a thickness of 100-200 nm on W or Mo metal to form the stack of W or Mo metal and Au metal; S 44: soaking the epitaxial wafer deposited with the metal stack in an acetone solution to strip the metal outside the anode metal, then placing the stripped epitaxial wafer into the acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen to form the anode of the diode. Withdrawn
The method according to claim 5, wherein step S₅ includes: S₅ 1: depositing a SiO 2 dielectric layer with a thickness of 100-300 nm on the uncovered portion of the epitaxial wafer using a plasma enhanced chemical vapor deposition equipment; S 52: performing spin coating, baking, through-hole photolithography and development on the epitaxial wafer with the dielectric layer in sequence, and etching the through-hole region to the surface of the cathode metal using an RIE machine; S 53: placing the etched epitaxial wafer into an acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen to form the low-turn- on voltage GaN diode. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
low turn-on voltage GaN Schottky diode
Materials described outside the worked examples.
tungsten
W
molybdenum
Mo
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3f. Wherein, the process conditions f o r etching the Si O 2 dielectric layer are as follows: gas flow of carbon tetrafluoride (CF 4): 15 s cc m (standard …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–20 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,557,682Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As shown in
FIG.2 is a flowchart of a method for preparing a low turn-on voltage GaN diode having an anode metal with a consistent crystal orientation provided by an …
FIG. 3f. Wherein, the process conditions f o r etching the Si O 2 dielectric layer are as follows: gas flow of carbon tetrafluoride (CF 4): 15 s cc m (standard …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) diode, comprising: an anode that includes a stack of metals of tungsten (W) or molybdenum (Mo) and gold (Au) each with a same crystal orientation the metal of W or Mo having a thickness of 20-120 nanometers (nm) and the Au having a thickness of 100-200 nm; a plurality of layers that include a substrate layer, a GaN buffer layer, a GaN channel layer and an aluminum gallium nitride (AlGaN) barrier layer which are arranged in sequence relative to each other; a cathode arranged on the AlGaN barrier layer, wherein the cathode includes a stack of metals of titanium (Ti), aluminum (Al), nickel (Ni) and gold (Au); a groove arranged in the GaN channel layer and the AlGaN barrier layer, the anode being provided on a bottom and a side wall of the groove and part of the AlGaN barrier layer; a dielectric layer provided on an uncovered portion of the AlGaN barrier layer that is not covered by the cathode and the anode, wherein, a contact portion of the anode with the groove and the AlGaN barrier layer is the metal of W or Mo. Currently amended
The GaN diode according to claim 1, wherein the bottom of the groove is located 2-20 nanometers (nm) below an interface between the AlGaN barrier layer and the GaN channel layer. Currently amended
The GaN diode according to claim 1, wherein the dielectric layer is a silicon dioxide (Si O 2) dielectric layer with a thickness of 100-300 nm. Currently amended
Canceled
A method for preparing a low turn-on voltage gallium nitride (GaN) diode having an anode metal with a consistent crystal orientation, wherein comprising steps of: Si: cleaning an epitaxial wafer of an aluminum gallium nitride (AlGaN)/GaN structure; S2: preparing a mesa isolation on the epitaxial wafer; Supplemental Amendment in further response to office action of S3: depositing a titanium (Ti)/aluminum (Al)/nickel (Ni)/gold (Au) metal stack on the epitaxial wafer to form a cathode of a diode; S4: etching an A l GaN barrier layer and a G aN channel layer to below an A l GaN/GaN interface to form a groove, depositing a stack of tungsten (W) or Mo metal and Au metal in the groove and on a part of the AlGaN barrier layer to form an anode of the diode, wherein a contact portion of the anode with the groove and the AlGaN barrier layer is W or Mo metal; S5: depositing a silicon dioxide (SiO 2) dielectric layer on an uncovered portion of the epitaxial wafer and etching a through-hole region to a surface of cathode metal using a reactive ion etching (an R IE) machine. Withdrawn
The method according to claim 5, wherein step S₂ includes: S 21: performing spin coating, baking, photolithography and development on the cleaned epitaxial wafer; S 22: etching an outside portion of a G aN mesa using inductively coupled plastma (I CP); S 23: placing the etched epitaxial wafer into an acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen to form a device mesa isolation. Withdrawn
The method according to claim 5, wherein step S₃ includes: S₃ 1: performing spin coating, baking, photolithography and development on a mesa- isolated epitaxial wafer; S 32: depositing the Ti/Al/Ni/Au metal stack on the epitaxial wafer using an electron beam evaporation equipment; S 33: soaking the epitaxial wafer deposited with the metal stack in an acetone solution to strip metals outside the cathode metal, then placing the stripped epitaxial wafer into the acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen and annealing in a rapid annealing furnace to form the cathode of the diode. Withdrawn
The method according to claim 5, wherein step S₄ includes: S 41: performing spin coating, baking, photolithography and development on the epitaxial wafer with the cathode; S 42: etching the AlGaN barrier layer and the G aN channel layer to 2-20 nm below the AlGaN/G aN interface using an I CP etching machine to form a groove; Supplemental Amendment in further response to office action of S 43: depositing W or Mo metal and a thickness of 2-20 nm in the groove and on a part of the AlGaN barrier layer using a molecular beam epitaxy technology, depositing W or Mo metal with a thickness of 20-100 nm on W or Mo metal with using an electron beam evaporation equipment, and depositing Au metal with a thickness of 100-200 nm on W or Mo metal to form the stack of W or Mo metal and Au metal; S 44: soaking the epitaxial wafer deposited with the metal stack in an acetone solution to strip the metal outside the anode metal, then placing the stripped epitaxial wafer into the acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen to form the anode of the diode. Withdrawn
The method according to claim 5, wherein step S₅ includes: S₅ 1: depositing a SiO 2 dielectric layer with a thickness of 100-300 nm on the uncovered portion of the epitaxial wafer using a plasma enhanced chemical vapor deposition equipment; S 52: performing spin coating, baking, through-hole photolithography and development on the epitaxial wafer with the dielectric layer in sequence, and etching the through-hole region to the surface of the cathode metal using an RIE machine; S 53: placing the etched epitaxial wafer into an acetone solution and an isopropanol solution in sequence, performing ultrasonic cleaning, and then drying with nitrogen to form the low-turn- on voltage GaN diode. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
low turn-on voltage GaN Schottky diode
Materials described outside the worked examples.
tungsten
W
molybdenum
Mo
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3f. Wherein, the process conditions f o r etching the Si O 2 dielectric layer are as follows: gas flow of carbon tetrafluoride (CF 4): 15 s cc m (standard …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–20 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
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