Patent
US 8,487,316METHOD OF MANUFACTURING AN INTEGRATED SEMICONDUCTOR SUBSTRATE STRUCTURE
Kai CHENG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,487,316Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated semiconductor substrate structure comprising: a substrate; a GaN-heterostructure being present in a first device area for definition of GaN- based devices, the GaN-heterostructure being covered at least partially with a protection layer; and a semiconductor substrate layer being present in a second device area for definition of CMOS devices, wherein at least one of the GaN heterostructure and the semiconductor substrate layer are provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are late r ally ju x tapo s ed, wherein the substrate is a silicon-on-insulator (SOI) substrate co m prisin g a handling layer, a buried insulating layer and a device la y er, wherein the device layer has a substrate orientation suitable for the growth of the GaN heterostructure, wherein the semiconductor layer is present on the handling layer of the SOI substrate structure, the buried dielectric layer and the device la y er having been removed in the second device area, wherein the semiconductor layer is recrystallized to have a crystal orientation identical to that of the handling layer of the SOI substrate structure.
The integrated semiconductor substrate structure of Claim 1, wherein an insulation layer is present between the GaN heterostructure and the semiconductor substrate layer on at least one sidewall of the at least one trench.
A method of manufacturing an integrated circuit comprising providing the integrated semiconductor substrate structure of Claim 1, the method further comprising: defining a GaN device in the first device area; defining at least one CMOS device in the second device area; and providing an interconnect structure for both the GaN device and the at least CMOS device.
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A method of manufacturing an integrated semiconductor substrate structure provided with a first device area for definition of GaN-based devices and a second device area for definition of CMOS devices, the method comprising: providing a semiconductor substrate; growing a GaN-heterostructure on the substrate; applying a protection layer on top of the GaN heterostructure, the protection layer being patterned so as to expose or leave exposed the GaN heterostructure in the second device area; -3- Application No.: 12/914,930 Filing Date: providing a semiconductor substate layer in the second device area, by forming at least one trench through the GaN heterostructure to expose a substrate layer of the substrate in the second device area and selectively growing the semiconductor layer in the at least one trench; and removing the protection layer at least partially to expose the first device area; and recrystallizing the semiconductor layer, so that the semiconductor layer obtains a crystal orientation identical to that of the underlying substrate layer.
The method of Claim 11, wherein the trench is provided with at least one sidewall, the sidewall being provided with an insulating layer prior to growth of the semiconductor layer.
The method of Claim 11, wherein a top surface of the semiconductor structure is polished after layer growth in the at least one trench.
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An integrated circuit comprising: a substrate; a GaN-heterostructure being present in a f irst device area for definition of GaN- based devices, the GaN-heterostructure being covered at least partially with a protection layer; a semiconductor substfate layer being present in a second device area for definition of CMOS devices; a GaN device defined in the first device area and a CMOS device defined in the second device area; and an interconnect structure interconnecting the CMOS devices and the GaN-based devices, -4- Application No.: 12/914,930 Filing Date: wherein the integrated semiconductor substrate structure is provided with a planarized surface in that at least one of the GaN heterostructure and the semiconductor s ubst r ate layer are provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed, wherein the substrate is a silicon-on-insulator (SO I) substrate comprising a handling layer, a buried insulating layer and a device layer, wherein the device layer has a substrate orientation suitable for the growth of the GaN heterostructure, wherein the semiconductor layer is present on the handling layer of the SOI substrate structure, the buried dielectric layer and the device layer having been removed in the second device area, wherein the semiconductor layer is recrystallized to have a crystal orientation identical to that of the handling layer of the SO I substrate structure.
The integrated circuit of Claim 16, wherein an insulation layer is present between the GaN heterostructure and the semiconductor suhstrate layer on at least one sidewall of the at least one trench.
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Layer stacks claimed or described, ordered top of device to substrate.
integrated semiconductor substrate structure
GaN-based device
Materials described outside the worked examples.
GaN heterostructure
semiconductor substrate layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–5000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,487,316Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated semiconductor substrate structure comprising: a substrate; a GaN-heterostructure being present in a first device area for definition of GaN- based devices, the GaN-heterostructure being covered at least partially with a protection layer; and a semiconductor substrate layer being present in a second device area for definition of CMOS devices, wherein at least one of the GaN heterostructure and the semiconductor substrate layer are provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are late r ally ju x tapo s ed, wherein the substrate is a silicon-on-insulator (SOI) substrate co m prisin g a handling layer, a buried insulating layer and a device la y er, wherein the device layer has a substrate orientation suitable for the growth of the GaN heterostructure, wherein the semiconductor layer is present on the handling layer of the SOI substrate structure, the buried dielectric layer and the device la y er having been removed in the second device area, wherein the semiconductor layer is recrystallized to have a crystal orientation identical to that of the handling layer of the SOI substrate structure.
The integrated semiconductor substrate structure of Claim 1, wherein an insulation layer is present between the GaN heterostructure and the semiconductor substrate layer on at least one sidewall of the at least one trench.
A method of manufacturing an integrated circuit comprising providing the integrated semiconductor substrate structure of Claim 1, the method further comprising: defining a GaN device in the first device area; defining at least one CMOS device in the second device area; and providing an interconnect structure for both the GaN device and the at least CMOS device.
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A method of manufacturing an integrated semiconductor substrate structure provided with a first device area for definition of GaN-based devices and a second device area for definition of CMOS devices, the method comprising: providing a semiconductor substrate; growing a GaN-heterostructure on the substrate; applying a protection layer on top of the GaN heterostructure, the protection layer being patterned so as to expose or leave exposed the GaN heterostructure in the second device area; -3- Application No.: 12/914,930 Filing Date: providing a semiconductor substate layer in the second device area, by forming at least one trench through the GaN heterostructure to expose a substrate layer of the substrate in the second device area and selectively growing the semiconductor layer in the at least one trench; and removing the protection layer at least partially to expose the first device area; and recrystallizing the semiconductor layer, so that the semiconductor layer obtains a crystal orientation identical to that of the underlying substrate layer.
The method of Claim 11, wherein the trench is provided with at least one sidewall, the sidewall being provided with an insulating layer prior to growth of the semiconductor layer.
The method of Claim 11, wherein a top surface of the semiconductor structure is polished after layer growth in the at least one trench.
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An integrated circuit comprising: a substrate; a GaN-heterostructure being present in a f irst device area for definition of GaN- based devices, the GaN-heterostructure being covered at least partially with a protection layer; a semiconductor substfate layer being present in a second device area for definition of CMOS devices; a GaN device defined in the first device area and a CMOS device defined in the second device area; and an interconnect structure interconnecting the CMOS devices and the GaN-based devices, -4- Application No.: 12/914,930 Filing Date: wherein the integrated semiconductor substrate structure is provided with a planarized surface in that at least one of the GaN heterostructure and the semiconductor s ubst r ate layer are provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed, wherein the substrate is a silicon-on-insulator (SO I) substrate comprising a handling layer, a buried insulating layer and a device layer, wherein the device layer has a substrate orientation suitable for the growth of the GaN heterostructure, wherein the semiconductor layer is present on the handling layer of the SOI substrate structure, the buried dielectric layer and the device layer having been removed in the second device area, wherein the semiconductor layer is recrystallized to have a crystal orientation identical to that of the handling layer of the SO I substrate structure.
The integrated circuit of Claim 16, wherein an insulation layer is present between the GaN heterostructure and the semiconductor suhstrate layer on at least one sidewall of the at least one trench.
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Layer stacks claimed or described, ordered top of device to substrate.
integrated semiconductor substrate structure
GaN-based device
Materials described outside the worked examples.
GaN heterostructure
semiconductor substrate layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–5000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,487,316Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated semiconductor substrate structure comprising: a substrate; a GaN-heterostructure being present in a first device area for definition of GaN- based devices, the GaN-heterostructure being covered at least partially with a protection layer; and a semiconductor substrate layer being present in a second device area for definition of CMOS devices, wherein at least one of the GaN heterostructure and the semiconductor substrate layer are provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are late r ally ju x tapo s ed, wherein the substrate is a silicon-on-insulator (SOI) substrate co m prisin g a handling layer, a buried insulating layer and a device la y er, wherein the device layer has a substrate orientation suitable for the growth of the GaN heterostructure, wherein the semiconductor layer is present on the handling layer of the SOI substrate structure, the buried dielectric layer and the device la y er having been removed in the second device area, wherein the semiconductor layer is recrystallized to have a crystal orientation identical to that of the handling layer of the SOI substrate structure.
The integrated semiconductor substrate structure of Claim 1, wherein an insulation layer is present between the GaN heterostructure and the semiconductor substrate layer on at least one sidewall of the at least one trench.
A method of manufacturing an integrated circuit comprising providing the integrated semiconductor substrate structure of Claim 1, the method further comprising: defining a GaN device in the first device area; defining at least one CMOS device in the second device area; and providing an interconnect structure for both the GaN device and the at least CMOS device.
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A method of manufacturing an integrated semiconductor substrate structure provided with a first device area for definition of GaN-based devices and a second device area for definition of CMOS devices, the method comprising: providing a semiconductor substrate; growing a GaN-heterostructure on the substrate; applying a protection layer on top of the GaN heterostructure, the protection layer being patterned so as to expose or leave exposed the GaN heterostructure in the second device area; -3- Application No.: 12/914,930 Filing Date: providing a semiconductor substate layer in the second device area, by forming at least one trench through the GaN heterostructure to expose a substrate layer of the substrate in the second device area and selectively growing the semiconductor layer in the at least one trench; and removing the protection layer at least partially to expose the first device area; and recrystallizing the semiconductor layer, so that the semiconductor layer obtains a crystal orientation identical to that of the underlying substrate layer.
The method of Claim 11, wherein the trench is provided with at least one sidewall, the sidewall being provided with an insulating layer prior to growth of the semiconductor layer.
The method of Claim 11, wherein a top surface of the semiconductor structure is polished after layer growth in the at least one trench.
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An integrated circuit comprising: a substrate; a GaN-heterostructure being present in a f irst device area for definition of GaN- based devices, the GaN-heterostructure being covered at least partially with a protection layer; a semiconductor substfate layer being present in a second device area for definition of CMOS devices; a GaN device defined in the first device area and a CMOS device defined in the second device area; and an interconnect structure interconnecting the CMOS devices and the GaN-based devices, -4- Application No.: 12/914,930 Filing Date: wherein the integrated semiconductor substrate structure is provided with a planarized surface in that at least one of the GaN heterostructure and the semiconductor s ubst r ate layer are provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed, wherein the substrate is a silicon-on-insulator (SO I) substrate comprising a handling layer, a buried insulating layer and a device layer, wherein the device layer has a substrate orientation suitable for the growth of the GaN heterostructure, wherein the semiconductor layer is present on the handling layer of the SOI substrate structure, the buried dielectric layer and the device layer having been removed in the second device area, wherein the semiconductor layer is recrystallized to have a crystal orientation identical to that of the handling layer of the SO I substrate structure.
The integrated circuit of Claim 16, wherein an insulation layer is present between the GaN heterostructure and the semiconductor suhstrate layer on at least one sidewall of the at least one trench.
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canceled
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Layer stacks claimed or described, ordered top of device to substrate.
integrated semiconductor substrate structure
GaN-based device
Materials described outside the worked examples.
GaN heterostructure
semiconductor substrate layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–5000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,487,316Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated semiconductor substrate structure comprising: a substrate; a GaN-heterostructure being present in a first device area for definition of GaN- based devices, the GaN-heterostructure being covered at least partially with a protection layer; and a semiconductor substrate layer being present in a second device area for definition of CMOS devices, wherein at least one of the GaN heterostructure and the semiconductor substrate layer are provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are late r ally ju x tapo s ed, wherein the substrate is a silicon-on-insulator (SOI) substrate co m prisin g a handling layer, a buried insulating layer and a device la y er, wherein the device layer has a substrate orientation suitable for the growth of the GaN heterostructure, wherein the semiconductor layer is present on the handling layer of the SOI substrate structure, the buried dielectric layer and the device la y er having been removed in the second device area, wherein the semiconductor layer is recrystallized to have a crystal orientation identical to that of the handling layer of the SOI substrate structure.
The integrated semiconductor substrate structure of Claim 1, wherein an insulation layer is present between the GaN heterostructure and the semiconductor substrate layer on at least one sidewall of the at least one trench.
A method of manufacturing an integrated circuit comprising providing the integrated semiconductor substrate structure of Claim 1, the method further comprising: defining a GaN device in the first device area; defining at least one CMOS device in the second device area; and providing an interconnect structure for both the GaN device and the at least CMOS device.
3-10.. canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
A method of manufacturing an integrated semiconductor substrate structure provided with a first device area for definition of GaN-based devices and a second device area for definition of CMOS devices, the method comprising: providing a semiconductor substrate; growing a GaN-heterostructure on the substrate; applying a protection layer on top of the GaN heterostructure, the protection layer being patterned so as to expose or leave exposed the GaN heterostructure in the second device area; -3- Application No.: 12/914,930 Filing Date: providing a semiconductor substate layer in the second device area, by forming at least one trench through the GaN heterostructure to expose a substrate layer of the substrate in the second device area and selectively growing the semiconductor layer in the at least one trench; and removing the protection layer at least partially to expose the first device area; and recrystallizing the semiconductor layer, so that the semiconductor layer obtains a crystal orientation identical to that of the underlying substrate layer.
The method of Claim 11, wherein the trench is provided with at least one sidewall, the sidewall being provided with an insulating layer prior to growth of the semiconductor layer.
The method of Claim 11, wherein a top surface of the semiconductor structure is polished after layer growth in the at least one trench.
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An integrated circuit comprising: a substrate; a GaN-heterostructure being present in a f irst device area for definition of GaN- based devices, the GaN-heterostructure being covered at least partially with a protection layer; a semiconductor substfate layer being present in a second device area for definition of CMOS devices; a GaN device defined in the first device area and a CMOS device defined in the second device area; and an interconnect structure interconnecting the CMOS devices and the GaN-based devices, -4- Application No.: 12/914,930 Filing Date: wherein the integrated semiconductor substrate structure is provided with a planarized surface in that at least one of the GaN heterostructure and the semiconductor s ubst r ate layer are provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed, wherein the substrate is a silicon-on-insulator (SO I) substrate comprising a handling layer, a buried insulating layer and a device layer, wherein the device layer has a substrate orientation suitable for the growth of the GaN heterostructure, wherein the semiconductor layer is present on the handling layer of the SOI substrate structure, the buried dielectric layer and the device layer having been removed in the second device area, wherein the semiconductor layer is recrystallized to have a crystal orientation identical to that of the handling layer of the SO I substrate structure.
The integrated circuit of Claim 16, wherein an insulation layer is present between the GaN heterostructure and the semiconductor suhstrate layer on at least one sidewall of the at least one trench.
1 8-20.. canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
integrated semiconductor substrate structure
GaN-based device
Materials described outside the worked examples.
GaN heterostructure
semiconductor substrate layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–5000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
integrated circuit with GaN and CMOS devices and interconnect
SOI substrate
protection layer
insulation layer
silicon oxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
silicon (111) substrate
Si
silicon carbide
SiC
| — |
Thickness | 100–200 nm | — |
Thickness | 50–200 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 1 µm | — |
integrated circuit with GaN and CMOS devices and interconnect
SOI substrate
protection layer
insulation layer
silicon oxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
silicon (111) substrate
Si
silicon carbide
SiC
| — |
Thickness | 100–200 nm | — |
Thickness | 50–200 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 1 µm | — |
integrated circuit with GaN and CMOS devices and interconnect
SOI substrate
protection layer
insulation layer
silicon oxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
silicon (111) substrate
Si
silicon carbide
SiC
| — |
Thickness | 100–200 nm | — |
Thickness | 50–200 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 1 µm | — |
integrated circuit with GaN and CMOS devices and interconnect
SOI substrate
protection layer
insulation layer
silicon oxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
silicon (111) substrate
Si
silicon carbide
SiC
| — |
Thickness | 100–200 nm | — |
Thickness | 50–200 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 1 µm | — |