Patent
US 10,692,752GALLIUM NITRIDE SEMICONDUCTOR STRUCTURE AND PROCESS FOR FABRICATING THEREOF
Joseph KAPLUN
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,692,752Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A process of fabrication of a semiconductor substrate structure, comprising: (i) fabricating a fi rst intermediate structure comprising: a silicon carbide (S i C) wafer substrate; a microcrystalline diamond (MCD) layer bonded to the silicon carbide (S iC) wafer substrate, the MCD layer having a fi rst MCD surface and a second MCD surface; a fi rst bonding material layer disposed between the MCD layer and the silicon carbide (S i C) wafer substrate, said fi rst bonding material layer being bonded to the Si C wafer substrate and to the fi rst MCD surface of the fi rst MCD layer; and a second bonding material layer disposed on the second MCD surface of the MCD layer and having an outer surface being exposed; (ii) fabricating a second intermediate structure comprising: a gallium nitride (GaN) active layer, a carrier substrate, and an adhesive layer therebetween; the GaN active layer having a fi rst GaN surface bonded to the carrier substrate via the adhesive layer, and a second GaN surface being exposed; (111) bonding said fi rst intermediate structure to said second intermediate structure, where the second GaN surface of the GaN active layer of the structure is bonded to the outer surface of the second bonding material layer; (i v) removing the carrier substrate together with the adhesive layer formed between the Si- carrier substrate and the fi rst GaN surface of the GaN active layer; thereby obtaining said semiconductor substrate structure comprising: the S i C wafer substrate; the GaN active layer; and the MCD layer disposed between the S i C wafer substrate and the GaN active layer, and bonded to the S i C wafer substrate via the fi rst bonding material layer and to the GaN active layer via the second bonding material layer. Currently amended
2. The process of claim 1, wherein the carrier substrate is a sapphire carrier substrate. Previously presented
3. The process of claim 1, wherein the fabricating of the fi rst intermediate structure comprises: providing a fi rst host wafer substrate; growing the MCD layer on the fi rst host wafer substrate, the fi rst MCD surface and the second MCD surface of the MCD layer having surface topographical irregularities; polishing the fi rst MCD surface to decrease the surface topographical irregularities up to a predetermined fi rst degree of smoothness; forming the fi rst bonding material layer on the fi rst MCD surface, a surface of the bonding material layer having a predetermined second degree of smoothness smoother than the fi rst degree of smoothness; providing the S i C wafer substrate; bonding the S i C wafer substrate to the MCD layer via the fi rst bonding material layer; removing the fi rst host wafer substrate; polishing the second MCD surface to decrease the surface topographical irregularities up to the predetermined fi rst degree of smoothness; forming a second bonding material layer on the second MCD surface, the surface of the second bonding material layer having the predetermined second degree of smoothness smoother than the fi rst degree of smoothness. Previously presented
5. The process of claim 1, wherein said fabricating of the second intermediate structure comprises: providing a fourth intermediate structure comprising: providing a second host wafer substrate; growing a gallium nitride (GaN) layer on the second host substrate, said GaN layer comprising: the GaN active layer having a fi rst GaN surface being exposed in the fourth intermediate structure, and a nucleation layer grown on the second host substrate; providing a carrier substrate and bonding said carrier substrate to the fi rst GaN surface using an adhesive material forming an adhesive layer between the carrier substrate and the first GaN surface; removing said second host substrate; removing the nucleation la y er to expose a second GaN surface of the GaN active layer; and carrying out an edge trimming of the GaN active layer. Previously presented
8. The process of claim 1. wherein the bonding of the second GaN surface of the GaN active la y er of the second intermediate structure to the outer surface of the second bonding material layer is by direct bonding. Previously presented
10. The process of claim 1, w herein the bonding of the second GaN surface of the GaN active layer of the second intermediate structure to the outer surface of the second bonding material layer is by adhesive bonding. Previously presented
9. The process of claim I. wherein the second bondin g material layer provides direct bonding to the second MCD surface of the MCD layer. Previously presented
11. The process of claim I. Nw herein the second bonding material layer provides adhesive bonding to the second MCD surface of the MCD layer. Previously presented
16. A semiconductor substrate structure comprising: a silicon carbide (S i C) wafer substrate; an active gallium nitride (GaN) layer; and a layer of microcrystalline diamond (MCD) layer disposed between the S i C wafer substrate and the GaN active layer, and bonded to the S i C wafer substrate and to the GaN active layer; and a first bonding material layer for bonding the MCD layer to the S i C wafer substrate, and a second bonding material layer for bonding the MCD layer to the GaN active layer; wherein the first bonding material layer and the second bonding material layer are made of an adhesive material and provide adhesive bonding. Previously presented
17. The semiconductor substrate structure of claim 16, wherein the GaN active layer has a thickness in the range of about 0.8 micrometers to 1.0 micrometer. Previously presented
18. The semiconductor substrate structure of claim 16, wherein the MCD layer has a thickness in the range of about 5 micrometers to 95 micrometers. Previously presented
19. The semiconductor substrate structure of claim 16, wherein the first bonding material layer and the second bonding material layer has a thickness in the range of about 5 nm to 50 nm. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN/MCD/SiC semiconductor substrate structure
Materials described outside the worked examples.
silicon carbide wafer substrate
SiC
gallium nitride active layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN active layer thickness (claimed range) | 0.8–1 | GaN |
MCD layer thickness (claimed range) | 5–95 |
Related documents with shared materials, methods, properties, or citations.
SELF-DENSIFYING INTERCONNECTION BETWEEN A HIGH-TEMPERATURE SEMICONDUCTOR DEVICE SELECTED FROM GaN OR SiC AND A SUBSTRATE
INDIUM SURFACTANT ASSISTED HVPE OF HIGH QUALITY GALLIUM NITRIDE AND GALLIUM NITRIDE ALLOY FILMS
Patent
Atlas literature
Patent
US 10,692,752Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A process of fabrication of a semiconductor substrate structure, comprising: (i) fabricating a fi rst intermediate structure comprising: a silicon carbide (S i C) wafer substrate; a microcrystalline diamond (MCD) layer bonded to the silicon carbide (S iC) wafer substrate, the MCD layer having a fi rst MCD surface and a second MCD surface; a fi rst bonding material layer disposed between the MCD layer and the silicon carbide (S i C) wafer substrate, said fi rst bonding material layer being bonded to the Si C wafer substrate and to the fi rst MCD surface of the fi rst MCD layer; and a second bonding material layer disposed on the second MCD surface of the MCD layer and having an outer surface being exposed; (ii) fabricating a second intermediate structure comprising: a gallium nitride (GaN) active layer, a carrier substrate, and an adhesive layer therebetween; the GaN active layer having a fi rst GaN surface bonded to the carrier substrate via the adhesive layer, and a second GaN surface being exposed; (111) bonding said fi rst intermediate structure to said second intermediate structure, where the second GaN surface of the GaN active layer of the structure is bonded to the outer surface of the second bonding material layer; (i v) removing the carrier substrate together with the adhesive layer formed between the Si- carrier substrate and the fi rst GaN surface of the GaN active layer; thereby obtaining said semiconductor substrate structure comprising: the S i C wafer substrate; the GaN active layer; and the MCD layer disposed between the S i C wafer substrate and the GaN active layer, and bonded to the S i C wafer substrate via the fi rst bonding material layer and to the GaN active layer via the second bonding material layer. Currently amended
2. The process of claim 1, wherein the carrier substrate is a sapphire carrier substrate. Previously presented
3. The process of claim 1, wherein the fabricating of the fi rst intermediate structure comprises: providing a fi rst host wafer substrate; growing the MCD layer on the fi rst host wafer substrate, the fi rst MCD surface and the second MCD surface of the MCD layer having surface topographical irregularities; polishing the fi rst MCD surface to decrease the surface topographical irregularities up to a predetermined fi rst degree of smoothness; forming the fi rst bonding material layer on the fi rst MCD surface, a surface of the bonding material layer having a predetermined second degree of smoothness smoother than the fi rst degree of smoothness; providing the S i C wafer substrate; bonding the S i C wafer substrate to the MCD layer via the fi rst bonding material layer; removing the fi rst host wafer substrate; polishing the second MCD surface to decrease the surface topographical irregularities up to the predetermined fi rst degree of smoothness; forming a second bonding material layer on the second MCD surface, the surface of the second bonding material layer having the predetermined second degree of smoothness smoother than the fi rst degree of smoothness. Previously presented
5. The process of claim 1, wherein said fabricating of the second intermediate structure comprises: providing a fourth intermediate structure comprising: providing a second host wafer substrate; growing a gallium nitride (GaN) layer on the second host substrate, said GaN layer comprising: the GaN active layer having a fi rst GaN surface being exposed in the fourth intermediate structure, and a nucleation layer grown on the second host substrate; providing a carrier substrate and bonding said carrier substrate to the fi rst GaN surface using an adhesive material forming an adhesive layer between the carrier substrate and the first GaN surface; removing said second host substrate; removing the nucleation la y er to expose a second GaN surface of the GaN active layer; and carrying out an edge trimming of the GaN active layer. Previously presented
8. The process of claim 1. wherein the bonding of the second GaN surface of the GaN active la y er of the second intermediate structure to the outer surface of the second bonding material layer is by direct bonding. Previously presented
10. The process of claim 1, w herein the bonding of the second GaN surface of the GaN active layer of the second intermediate structure to the outer surface of the second bonding material layer is by adhesive bonding. Previously presented
9. The process of claim I. wherein the second bondin g material layer provides direct bonding to the second MCD surface of the MCD layer. Previously presented
11. The process of claim I. Nw herein the second bonding material layer provides adhesive bonding to the second MCD surface of the MCD layer. Previously presented
16. A semiconductor substrate structure comprising: a silicon carbide (S i C) wafer substrate; an active gallium nitride (GaN) layer; and a layer of microcrystalline diamond (MCD) layer disposed between the S i C wafer substrate and the GaN active layer, and bonded to the S i C wafer substrate and to the GaN active layer; and a first bonding material layer for bonding the MCD layer to the S i C wafer substrate, and a second bonding material layer for bonding the MCD layer to the GaN active layer; wherein the first bonding material layer and the second bonding material layer are made of an adhesive material and provide adhesive bonding. Previously presented
17. The semiconductor substrate structure of claim 16, wherein the GaN active layer has a thickness in the range of about 0.8 micrometers to 1.0 micrometer. Previously presented
18. The semiconductor substrate structure of claim 16, wherein the MCD layer has a thickness in the range of about 5 micrometers to 95 micrometers. Previously presented
19. The semiconductor substrate structure of claim 16, wherein the first bonding material layer and the second bonding material layer has a thickness in the range of about 5 nm to 50 nm. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN/MCD/SiC semiconductor substrate structure
Materials described outside the worked examples.
silicon carbide wafer substrate
SiC
gallium nitride active layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN active layer thickness (claimed range) | 0.8–1 | GaN |
MCD layer thickness (claimed range) | 5–95 |
Related documents with shared materials, methods, properties, or citations.
SELF-DENSIFYING INTERCONNECTION BETWEEN A HIGH-TEMPERATURE SEMICONDUCTOR DEVICE SELECTED FROM GaN OR SiC AND A SUBSTRATE
INDIUM SURFACTANT ASSISTED HVPE OF HIGH QUALITY GALLIUM NITRIDE AND GALLIUM NITRIDE ALLOY FILMS
Patent
Atlas literature
Patent
US 10,692,752Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A process of fabrication of a semiconductor substrate structure, comprising: (i) fabricating a fi rst intermediate structure comprising: a silicon carbide (S i C) wafer substrate; a microcrystalline diamond (MCD) layer bonded to the silicon carbide (S iC) wafer substrate, the MCD layer having a fi rst MCD surface and a second MCD surface; a fi rst bonding material layer disposed between the MCD layer and the silicon carbide (S i C) wafer substrate, said fi rst bonding material layer being bonded to the Si C wafer substrate and to the fi rst MCD surface of the fi rst MCD layer; and a second bonding material layer disposed on the second MCD surface of the MCD layer and having an outer surface being exposed; (ii) fabricating a second intermediate structure comprising: a gallium nitride (GaN) active layer, a carrier substrate, and an adhesive layer therebetween; the GaN active layer having a fi rst GaN surface bonded to the carrier substrate via the adhesive layer, and a second GaN surface being exposed; (111) bonding said fi rst intermediate structure to said second intermediate structure, where the second GaN surface of the GaN active layer of the structure is bonded to the outer surface of the second bonding material layer; (i v) removing the carrier substrate together with the adhesive layer formed between the Si- carrier substrate and the fi rst GaN surface of the GaN active layer; thereby obtaining said semiconductor substrate structure comprising: the S i C wafer substrate; the GaN active layer; and the MCD layer disposed between the S i C wafer substrate and the GaN active layer, and bonded to the S i C wafer substrate via the fi rst bonding material layer and to the GaN active layer via the second bonding material layer. Currently amended
2. The process of claim 1, wherein the carrier substrate is a sapphire carrier substrate. Previously presented
3. The process of claim 1, wherein the fabricating of the fi rst intermediate structure comprises: providing a fi rst host wafer substrate; growing the MCD layer on the fi rst host wafer substrate, the fi rst MCD surface and the second MCD surface of the MCD layer having surface topographical irregularities; polishing the fi rst MCD surface to decrease the surface topographical irregularities up to a predetermined fi rst degree of smoothness; forming the fi rst bonding material layer on the fi rst MCD surface, a surface of the bonding material layer having a predetermined second degree of smoothness smoother than the fi rst degree of smoothness; providing the S i C wafer substrate; bonding the S i C wafer substrate to the MCD layer via the fi rst bonding material layer; removing the fi rst host wafer substrate; polishing the second MCD surface to decrease the surface topographical irregularities up to the predetermined fi rst degree of smoothness; forming a second bonding material layer on the second MCD surface, the surface of the second bonding material layer having the predetermined second degree of smoothness smoother than the fi rst degree of smoothness. Previously presented
5. The process of claim 1, wherein said fabricating of the second intermediate structure comprises: providing a fourth intermediate structure comprising: providing a second host wafer substrate; growing a gallium nitride (GaN) layer on the second host substrate, said GaN layer comprising: the GaN active layer having a fi rst GaN surface being exposed in the fourth intermediate structure, and a nucleation layer grown on the second host substrate; providing a carrier substrate and bonding said carrier substrate to the fi rst GaN surface using an adhesive material forming an adhesive layer between the carrier substrate and the first GaN surface; removing said second host substrate; removing the nucleation la y er to expose a second GaN surface of the GaN active layer; and carrying out an edge trimming of the GaN active layer. Previously presented
8. The process of claim 1. wherein the bonding of the second GaN surface of the GaN active la y er of the second intermediate structure to the outer surface of the second bonding material layer is by direct bonding. Previously presented
10. The process of claim 1, w herein the bonding of the second GaN surface of the GaN active layer of the second intermediate structure to the outer surface of the second bonding material layer is by adhesive bonding. Previously presented
9. The process of claim I. wherein the second bondin g material layer provides direct bonding to the second MCD surface of the MCD layer. Previously presented
11. The process of claim I. Nw herein the second bonding material layer provides adhesive bonding to the second MCD surface of the MCD layer. Previously presented
16. A semiconductor substrate structure comprising: a silicon carbide (S i C) wafer substrate; an active gallium nitride (GaN) layer; and a layer of microcrystalline diamond (MCD) layer disposed between the S i C wafer substrate and the GaN active layer, and bonded to the S i C wafer substrate and to the GaN active layer; and a first bonding material layer for bonding the MCD layer to the S i C wafer substrate, and a second bonding material layer for bonding the MCD layer to the GaN active layer; wherein the first bonding material layer and the second bonding material layer are made of an adhesive material and provide adhesive bonding. Previously presented
17. The semiconductor substrate structure of claim 16, wherein the GaN active layer has a thickness in the range of about 0.8 micrometers to 1.0 micrometer. Previously presented
18. The semiconductor substrate structure of claim 16, wherein the MCD layer has a thickness in the range of about 5 micrometers to 95 micrometers. Previously presented
19. The semiconductor substrate structure of claim 16, wherein the first bonding material layer and the second bonding material layer has a thickness in the range of about 5 nm to 50 nm. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN/MCD/SiC semiconductor substrate structure
Materials described outside the worked examples.
silicon carbide wafer substrate
SiC
gallium nitride active layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN active layer thickness (claimed range) | 0.8–1 | GaN |
MCD layer thickness (claimed range) | 5–95 |
Related documents with shared materials, methods, properties, or citations.
SELF-DENSIFYING INTERCONNECTION BETWEEN A HIGH-TEMPERATURE SEMICONDUCTOR DEVICE SELECTED FROM GaN OR SiC AND A SUBSTRATE
INDIUM SURFACTANT ASSISTED HVPE OF HIGH QUALITY GALLIUM NITRIDE AND GALLIUM NITRIDE ALLOY FILMS
Patent
Atlas literature
Patent
US 10,692,752Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A process of fabrication of a semiconductor substrate structure, comprising: (i) fabricating a fi rst intermediate structure comprising: a silicon carbide (S i C) wafer substrate; a microcrystalline diamond (MCD) layer bonded to the silicon carbide (S iC) wafer substrate, the MCD layer having a fi rst MCD surface and a second MCD surface; a fi rst bonding material layer disposed between the MCD layer and the silicon carbide (S i C) wafer substrate, said fi rst bonding material layer being bonded to the Si C wafer substrate and to the fi rst MCD surface of the fi rst MCD layer; and a second bonding material layer disposed on the second MCD surface of the MCD layer and having an outer surface being exposed; (ii) fabricating a second intermediate structure comprising: a gallium nitride (GaN) active layer, a carrier substrate, and an adhesive layer therebetween; the GaN active layer having a fi rst GaN surface bonded to the carrier substrate via the adhesive layer, and a second GaN surface being exposed; (111) bonding said fi rst intermediate structure to said second intermediate structure, where the second GaN surface of the GaN active layer of the structure is bonded to the outer surface of the second bonding material layer; (i v) removing the carrier substrate together with the adhesive layer formed between the Si- carrier substrate and the fi rst GaN surface of the GaN active layer; thereby obtaining said semiconductor substrate structure comprising: the S i C wafer substrate; the GaN active layer; and the MCD layer disposed between the S i C wafer substrate and the GaN active layer, and bonded to the S i C wafer substrate via the fi rst bonding material layer and to the GaN active layer via the second bonding material layer. Currently amended
2. The process of claim 1, wherein the carrier substrate is a sapphire carrier substrate. Previously presented
3. The process of claim 1, wherein the fabricating of the fi rst intermediate structure comprises: providing a fi rst host wafer substrate; growing the MCD layer on the fi rst host wafer substrate, the fi rst MCD surface and the second MCD surface of the MCD layer having surface topographical irregularities; polishing the fi rst MCD surface to decrease the surface topographical irregularities up to a predetermined fi rst degree of smoothness; forming the fi rst bonding material layer on the fi rst MCD surface, a surface of the bonding material layer having a predetermined second degree of smoothness smoother than the fi rst degree of smoothness; providing the S i C wafer substrate; bonding the S i C wafer substrate to the MCD layer via the fi rst bonding material layer; removing the fi rst host wafer substrate; polishing the second MCD surface to decrease the surface topographical irregularities up to the predetermined fi rst degree of smoothness; forming a second bonding material layer on the second MCD surface, the surface of the second bonding material layer having the predetermined second degree of smoothness smoother than the fi rst degree of smoothness. Previously presented
5. The process of claim 1, wherein said fabricating of the second intermediate structure comprises: providing a fourth intermediate structure comprising: providing a second host wafer substrate; growing a gallium nitride (GaN) layer on the second host substrate, said GaN layer comprising: the GaN active layer having a fi rst GaN surface being exposed in the fourth intermediate structure, and a nucleation layer grown on the second host substrate; providing a carrier substrate and bonding said carrier substrate to the fi rst GaN surface using an adhesive material forming an adhesive layer between the carrier substrate and the first GaN surface; removing said second host substrate; removing the nucleation la y er to expose a second GaN surface of the GaN active layer; and carrying out an edge trimming of the GaN active layer. Previously presented
8. The process of claim 1. wherein the bonding of the second GaN surface of the GaN active la y er of the second intermediate structure to the outer surface of the second bonding material layer is by direct bonding. Previously presented
10. The process of claim 1, w herein the bonding of the second GaN surface of the GaN active layer of the second intermediate structure to the outer surface of the second bonding material layer is by adhesive bonding. Previously presented
9. The process of claim I. wherein the second bondin g material layer provides direct bonding to the second MCD surface of the MCD layer. Previously presented
11. The process of claim I. Nw herein the second bonding material layer provides adhesive bonding to the second MCD surface of the MCD layer. Previously presented
16. A semiconductor substrate structure comprising: a silicon carbide (S i C) wafer substrate; an active gallium nitride (GaN) layer; and a layer of microcrystalline diamond (MCD) layer disposed between the S i C wafer substrate and the GaN active layer, and bonded to the S i C wafer substrate and to the GaN active layer; and a first bonding material layer for bonding the MCD layer to the S i C wafer substrate, and a second bonding material layer for bonding the MCD layer to the GaN active layer; wherein the first bonding material layer and the second bonding material layer are made of an adhesive material and provide adhesive bonding. Previously presented
17. The semiconductor substrate structure of claim 16, wherein the GaN active layer has a thickness in the range of about 0.8 micrometers to 1.0 micrometer. Previously presented
18. The semiconductor substrate structure of claim 16, wherein the MCD layer has a thickness in the range of about 5 micrometers to 95 micrometers. Previously presented
19. The semiconductor substrate structure of claim 16, wherein the first bonding material layer and the second bonding material layer has a thickness in the range of about 5 nm to 50 nm. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN/MCD/SiC semiconductor substrate structure
Materials described outside the worked examples.
silicon carbide wafer substrate
SiC
gallium nitride active layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN active layer thickness (claimed range) | 0.8–1 | GaN |
MCD layer thickness (claimed range) | 5–95 |
Related documents with shared materials, methods, properties, or citations.
SELF-DENSIFYING INTERCONNECTION BETWEEN A HIGH-TEMPERATURE SEMICONDUCTOR DEVICE SELECTED FROM GaN OR SiC AND A SUBSTRATE
INDIUM SURFACTANT ASSISTED HVPE OF HIGH QUALITY GALLIUM NITRIDE AND GALLIUM NITRIDE ALLOY FILMS
silicon dioxide bonding material layer
SiO₂
sapphire carrier substrate
silicon host wafer substrate
Si
adhesive bonding material
polyimide polymer
Bisbenzocyclobutene (BCB) Electronic Resin
Bonding material layer thickness (claimed range) | 5–50 | — |
First degree of smoothness (MCD surface after polishing) | ≤ 2 | microcrystalline diamond layer |
Second degree of smoothness (bonding layer surface after polishing) | ≤ 0.5 | SiO₂ |
SiC substrate thermal conductivity (background reference) | 350–400 | SiC |
Polycrystalline diamond thermal conductivity (background reference) | 800–2000 | — |
Thickness | 5–50 nm | — |
Thickness | 30–100 nm | — |
Temperature | 1000–1500 K | — |
Duration | 10–100 seconds | — |
Thickness | 300–600 µm | — |
Thickness | 5–95 µm | — |
Thickness | 90–110 µm | — |
Thickness | 3–6 mm | — |
Thickness | 0.5–1 µm | — |
Thickness | 8- 2 micrometers | — |
Thickness | 0.1–1.5 µm | — |
Thickness | 0.8–1 µm | — |
Thickness | ≥ 2 nm | — |
Thickness | ≥ 0.5 nm | — |
silicon dioxide bonding material layer
SiO₂
sapphire carrier substrate
silicon host wafer substrate
Si
adhesive bonding material
polyimide polymer
Bisbenzocyclobutene (BCB) Electronic Resin
Bonding material layer thickness (claimed range) | 5–50 | — |
First degree of smoothness (MCD surface after polishing) | ≤ 2 | microcrystalline diamond layer |
Second degree of smoothness (bonding layer surface after polishing) | ≤ 0.5 | SiO₂ |
SiC substrate thermal conductivity (background reference) | 350–400 | SiC |
Polycrystalline diamond thermal conductivity (background reference) | 800–2000 | — |
Thickness | 5–50 nm | — |
Thickness | 30–100 nm | — |
Temperature | 1000–1500 K | — |
Duration | 10–100 seconds | — |
Thickness | 300–600 µm | — |
Thickness | 5–95 µm | — |
Thickness | 90–110 µm | — |
Thickness | 3–6 mm | — |
Thickness | 0.5–1 µm | — |
Thickness | 8- 2 micrometers | — |
Thickness | 0.1–1.5 µm | — |
Thickness | 0.8–1 µm | — |
Thickness | ≥ 2 nm | — |
Thickness | ≥ 0.5 nm | — |
silicon dioxide bonding material layer
SiO₂
sapphire carrier substrate
silicon host wafer substrate
Si
adhesive bonding material
polyimide polymer
Bisbenzocyclobutene (BCB) Electronic Resin
Bonding material layer thickness (claimed range) | 5–50 | — |
First degree of smoothness (MCD surface after polishing) | ≤ 2 | microcrystalline diamond layer |
Second degree of smoothness (bonding layer surface after polishing) | ≤ 0.5 | SiO₂ |
SiC substrate thermal conductivity (background reference) | 350–400 | SiC |
Polycrystalline diamond thermal conductivity (background reference) | 800–2000 | — |
Thickness | 5–50 nm | — |
Thickness | 30–100 nm | — |
Temperature | 1000–1500 K | — |
Duration | 10–100 seconds | — |
Thickness | 300–600 µm | — |
Thickness | 5–95 µm | — |
Thickness | 90–110 µm | — |
Thickness | 3–6 mm | — |
Thickness | 0.5–1 µm | — |
Thickness | 8- 2 micrometers | — |
Thickness | 0.1–1.5 µm | — |
Thickness | 0.8–1 µm | — |
Thickness | ≥ 2 nm | — |
Thickness | ≥ 0.5 nm | — |
silicon dioxide bonding material layer
SiO₂
sapphire carrier substrate
silicon host wafer substrate
Si
adhesive bonding material
polyimide polymer
Bisbenzocyclobutene (BCB) Electronic Resin
Bonding material layer thickness (claimed range) | 5–50 | — |
First degree of smoothness (MCD surface after polishing) | ≤ 2 | microcrystalline diamond layer |
Second degree of smoothness (bonding layer surface after polishing) | ≤ 0.5 | SiO₂ |
SiC substrate thermal conductivity (background reference) | 350–400 | SiC |
Polycrystalline diamond thermal conductivity (background reference) | 800–2000 | — |
Thickness | 5–50 nm | — |
Thickness | 30–100 nm | — |
Temperature | 1000–1500 K | — |
Duration | 10–100 seconds | — |
Thickness | 300–600 µm | — |
Thickness | 5–95 µm | — |
Thickness | 90–110 µm | — |
Thickness | 3–6 mm | — |
Thickness | 0.5–1 µm | — |
Thickness | 8- 2 micrometers | — |
Thickness | 0.1–1.5 µm | — |
Thickness | 0.8–1 µm | — |
Thickness | ≥ 2 nm | — |
Thickness | ≥ 0.5 nm | — |