Patent
US 9,324,844METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN CHANNEL
Isik C. Kizilyalli
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,324,844Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B shows the vertical JFET turned on, meaning the depletion regions 109 are 20 separated, allowing current to flow in a vertical direction 110 from the …
FIGS. 2-9 illustrate a process for creating a first type of vertical JFET that utilizes etching of an epitaxial layer to form the channel of the vertical JFET. …
FIG. 3 illustrates the formation of a second GaN epitaxial layer 301 above the first GaN epitaxial layer 201. The second GaN epitaxial layer 301, which …
FIG. 4 illustrates the formation of a third GaN epitaxial layer 401 above the second GaN epitaxial layer 301. The third GaN epitaxial layer 401, which …
FIG. 5. An outside angle 504 of greater than 90 degrees can facilitate deposition and/or regrowth of subsequent layers and can help improve 10 KILPATRICK …
FIG. 6 illustrates the formation of a fourth GaN epitaxial layer 601. The fourth GaN epitaxial layer 601, which forms gate portions of the vertical JFET 100, …
FIG. 7 illustrates the formation of a metallic structure 701 below the GaN substrate 200. The metallic structure 701 can be one or more layers of ohmic metal …
FIG. 8 illustrates the formation of additional metallic structures 801 on the fourth GaN epitaxial layer 601. The additional metallic structures 801 can be one …
FIG. 9, these metallic structures provide 25 for electrical connectivity to the drain, source, and gate of the vertical JFET. The various epitaxial layers do …
FIG. 10 is a simplified cross-sectional diagram illustrating the formation of a first GaN epitaxial layer 1 00 1 on a G aN substrate 1 000 to form a drift region …
FIG. 11 illustrates the formation of a second GaN epitaxial layer 1101 above the 20 first GaN epitaxial layer 1001. The second GaN epitaxial layer 1101, which …
FIG. 12 illustrates the removal of at least a portion of the second GaN epitaxial layer 1101 to expose a surface 1201 of the first GaN epitaxial layer 1001. …
FIG. 13 illustrates the formation of a GaN channel region 1301, which is formed in the removed portion(s) of the second GaN epitaxial layer 1101. The GaN …
FIG. 14 illustrates the formation of a GaN epitaxial structure 1401 above the GaN channel region 1301. The GaN epitaxial structure 1401, which eventually can …
FIG. 15 illustrates the formation of a metallic structure 1501 coupled with the GaN substrate 1000. The metallic structure 1501 provides a gate contact for the …
FIG. 16 illustrates the formation of additional metallic structures 1601 on the second GaN epitaxial layer 1101. The additional metallic structures 1601 serve …
FIG. 17, the formation of further metallic structures 1701, 1702 on the additional metallic structures 1601 and the GaN epitaxial structure 1401, respectively …
FIG. 18 is a simplified flowchart illustrating a method of fabricating a vertical JF ET with a regrown gate region according to an embodiment of the present …
FIG. 19 is a simplified flowchart illustrating a method of fabricating a vertical JFET 25 with a regrown channel region according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical JFET, the method comprising: providing a gallium nitride (GaN) substrate; forming an n-type GaN epitaxial layer coupled to the GaN substrate; forming a p-type GaN epitaxial layer coupled to the n-type GaN epitaxial layer, wherein the p-type GaN epitaxial layer is characterized by a p-type dopant concentration; removing at least a portion of the p-type GaN epitaxial layer to expose a portion of the n-type GaN epitaxial layer; forming an n-type GaN channel region coupled to the n-type GaN epitaxial layer and at least a portion of the p-type GaN epitaxial layer; forming an n-type GaN epitaxial structure coupled to the n-type GaN channel region; forming a first metallic structure electrically coupled to the GaN substrate; forming a second metallic structure electrically coupled to the p-type GaN epitaxial layer; and forming a third metallic structure electrically coupled to the n-type GaN epitaxial structure.
The method of claim 1 wherein a thickness of the n-type GaN epitaxial layer is between about 1 m and about 100 pm.
The method of claim 1 wherein the n-type GaN epitaxial layer is characterized by a first n-type dopant concentration, the n-type GaN channel region is characterized by a second n-type dopant concentration, and the n-type GaN epitaxial Page 2 of 5 App l. No. 14/604,600 PATENT Am dt. dated Response to Office Action of structure is characterized by a third n-type dopant concentration greater than the first n-type dopant concentration.
The method of claim 1 wherein the n-type GaN epitaxial layer comprises an n-type dopant including at least one of silicon and oxygen.
The method of claim [[1]]4 wherein at least one of the first n-type dopant concentration, the second n-type dopant concentration, or the third n-type dopant concentration varies as a function of thickness.
A method for fabricating an epitaxial structure, the method comp ri sing: providing a I II-nitride substrate; forming a first I II -nitride epitaxial layer of a first conductivity type coupled to the III -nitride substrate, wherein the first I II -nitride epitaxial layer has a first dopant concentration; forming a second I II -nitride epitaxial layer of a second conductivity type coupled to the first I II -nitride epitaxial layer, wherein the second I II -nitride epitaxial layer has a second dopant concentration; removing at least a portion of the second I II -nitride epitaxial layer to expose a surface of the first I II -nitride epitaxial layer; and forming a I II -nitride epitaxial channel region of the first conductivity type coupled to the surface of the first I II -nitride epitaxial layer, wherein the I II -nitride epitaxial channel region has a third dopant concentration.
The method of claim 7 further comprising forming a I II -nitride epitaxial structure of the first conductivity type coupled to the I II -nitride epitaxial channel region, the I II -nitride epitaxial structure having a dopant concentration greater than greater than the first dopant concentration.
The method of claim 7 wherein the first conductivity type is n type, and the second conductivity type is p type.
The method of claim 7 wherein at least one of the first dopant concentration, the second dopant concentration, or the third dopant concentration is non-uniform.
The method of claim 7 wherein a thickness of the first III- nitride epitaxial layer is between 1 p m and 100 pm. Page 4 of
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN JFET
vertical III-nitride JFET (generic)
Materials described outside the worked examples.
GaN substrate
GaN
III-nitride substrate
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 2-9 illustrate a process for creating a first type of vertical JFET that utilizes etching of an epitaxial layer to form the channel of the vertical JFET. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,324,844Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B shows the vertical JFET turned on, meaning the depletion regions 109 are 20 separated, allowing current to flow in a vertical direction 110 from the …
FIGS. 2-9 illustrate a process for creating a first type of vertical JFET that utilizes etching of an epitaxial layer to form the channel of the vertical JFET. …
FIG. 3 illustrates the formation of a second GaN epitaxial layer 301 above the first GaN epitaxial layer 201. The second GaN epitaxial layer 301, which …
FIG. 4 illustrates the formation of a third GaN epitaxial layer 401 above the second GaN epitaxial layer 301. The third GaN epitaxial layer 401, which …
FIG. 5. An outside angle 504 of greater than 90 degrees can facilitate deposition and/or regrowth of subsequent layers and can help improve 10 KILPATRICK …
FIG. 6 illustrates the formation of a fourth GaN epitaxial layer 601. The fourth GaN epitaxial layer 601, which forms gate portions of the vertical JFET 100, …
FIG. 7 illustrates the formation of a metallic structure 701 below the GaN substrate 200. The metallic structure 701 can be one or more layers of ohmic metal …
FIG. 8 illustrates the formation of additional metallic structures 801 on the fourth GaN epitaxial layer 601. The additional metallic structures 801 can be one …
FIG. 9, these metallic structures provide 25 for electrical connectivity to the drain, source, and gate of the vertical JFET. The various epitaxial layers do …
FIG. 10 is a simplified cross-sectional diagram illustrating the formation of a first GaN epitaxial layer 1 00 1 on a G aN substrate 1 000 to form a drift region …
FIG. 11 illustrates the formation of a second GaN epitaxial layer 1101 above the 20 first GaN epitaxial layer 1001. The second GaN epitaxial layer 1101, which …
FIG. 12 illustrates the removal of at least a portion of the second GaN epitaxial layer 1101 to expose a surface 1201 of the first GaN epitaxial layer 1001. …
FIG. 13 illustrates the formation of a GaN channel region 1301, which is formed in the removed portion(s) of the second GaN epitaxial layer 1101. The GaN …
FIG. 14 illustrates the formation of a GaN epitaxial structure 1401 above the GaN channel region 1301. The GaN epitaxial structure 1401, which eventually can …
FIG. 15 illustrates the formation of a metallic structure 1501 coupled with the GaN substrate 1000. The metallic structure 1501 provides a gate contact for the …
FIG. 16 illustrates the formation of additional metallic structures 1601 on the second GaN epitaxial layer 1101. The additional metallic structures 1601 serve …
FIG. 17, the formation of further metallic structures 1701, 1702 on the additional metallic structures 1601 and the GaN epitaxial structure 1401, respectively …
FIG. 18 is a simplified flowchart illustrating a method of fabricating a vertical JF ET with a regrown gate region according to an embodiment of the present …
FIG. 19 is a simplified flowchart illustrating a method of fabricating a vertical JFET 25 with a regrown channel region according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical JFET, the method comprising: providing a gallium nitride (GaN) substrate; forming an n-type GaN epitaxial layer coupled to the GaN substrate; forming a p-type GaN epitaxial layer coupled to the n-type GaN epitaxial layer, wherein the p-type GaN epitaxial layer is characterized by a p-type dopant concentration; removing at least a portion of the p-type GaN epitaxial layer to expose a portion of the n-type GaN epitaxial layer; forming an n-type GaN channel region coupled to the n-type GaN epitaxial layer and at least a portion of the p-type GaN epitaxial layer; forming an n-type GaN epitaxial structure coupled to the n-type GaN channel region; forming a first metallic structure electrically coupled to the GaN substrate; forming a second metallic structure electrically coupled to the p-type GaN epitaxial layer; and forming a third metallic structure electrically coupled to the n-type GaN epitaxial structure.
The method of claim 1 wherein a thickness of the n-type GaN epitaxial layer is between about 1 m and about 100 pm.
The method of claim 1 wherein the n-type GaN epitaxial layer is characterized by a first n-type dopant concentration, the n-type GaN channel region is characterized by a second n-type dopant concentration, and the n-type GaN epitaxial Page 2 of 5 App l. No. 14/604,600 PATENT Am dt. dated Response to Office Action of structure is characterized by a third n-type dopant concentration greater than the first n-type dopant concentration.
The method of claim 1 wherein the n-type GaN epitaxial layer comprises an n-type dopant including at least one of silicon and oxygen.
The method of claim [[1]]4 wherein at least one of the first n-type dopant concentration, the second n-type dopant concentration, or the third n-type dopant concentration varies as a function of thickness.
A method for fabricating an epitaxial structure, the method comp ri sing: providing a I II-nitride substrate; forming a first I II -nitride epitaxial layer of a first conductivity type coupled to the III -nitride substrate, wherein the first I II -nitride epitaxial layer has a first dopant concentration; forming a second I II -nitride epitaxial layer of a second conductivity type coupled to the first I II -nitride epitaxial layer, wherein the second I II -nitride epitaxial layer has a second dopant concentration; removing at least a portion of the second I II -nitride epitaxial layer to expose a surface of the first I II -nitride epitaxial layer; and forming a I II -nitride epitaxial channel region of the first conductivity type coupled to the surface of the first I II -nitride epitaxial layer, wherein the I II -nitride epitaxial channel region has a third dopant concentration.
The method of claim 7 further comprising forming a I II -nitride epitaxial structure of the first conductivity type coupled to the I II -nitride epitaxial channel region, the I II -nitride epitaxial structure having a dopant concentration greater than greater than the first dopant concentration.
The method of claim 7 wherein the first conductivity type is n type, and the second conductivity type is p type.
The method of claim 7 wherein at least one of the first dopant concentration, the second dopant concentration, or the third dopant concentration is non-uniform.
The method of claim 7 wherein a thickness of the first III- nitride epitaxial layer is between 1 p m and 100 pm. Page 4 of
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN JFET
vertical III-nitride JFET (generic)
Materials described outside the worked examples.
GaN substrate
GaN
III-nitride substrate
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 2-9 illustrate a process for creating a first type of vertical JFET that utilizes etching of an epitaxial layer to form the channel of the vertical JFET. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,324,844Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B shows the vertical JFET turned on, meaning the depletion regions 109 are 20 separated, allowing current to flow in a vertical direction 110 from the …
FIGS. 2-9 illustrate a process for creating a first type of vertical JFET that utilizes etching of an epitaxial layer to form the channel of the vertical JFET. …
FIG. 3 illustrates the formation of a second GaN epitaxial layer 301 above the first GaN epitaxial layer 201. The second GaN epitaxial layer 301, which …
FIG. 4 illustrates the formation of a third GaN epitaxial layer 401 above the second GaN epitaxial layer 301. The third GaN epitaxial layer 401, which …
FIG. 5. An outside angle 504 of greater than 90 degrees can facilitate deposition and/or regrowth of subsequent layers and can help improve 10 KILPATRICK …
FIG. 6 illustrates the formation of a fourth GaN epitaxial layer 601. The fourth GaN epitaxial layer 601, which forms gate portions of the vertical JFET 100, …
FIG. 7 illustrates the formation of a metallic structure 701 below the GaN substrate 200. The metallic structure 701 can be one or more layers of ohmic metal …
FIG. 8 illustrates the formation of additional metallic structures 801 on the fourth GaN epitaxial layer 601. The additional metallic structures 801 can be one …
FIG. 9, these metallic structures provide 25 for electrical connectivity to the drain, source, and gate of the vertical JFET. The various epitaxial layers do …
FIG. 10 is a simplified cross-sectional diagram illustrating the formation of a first GaN epitaxial layer 1 00 1 on a G aN substrate 1 000 to form a drift region …
FIG. 11 illustrates the formation of a second GaN epitaxial layer 1101 above the 20 first GaN epitaxial layer 1001. The second GaN epitaxial layer 1101, which …
FIG. 12 illustrates the removal of at least a portion of the second GaN epitaxial layer 1101 to expose a surface 1201 of the first GaN epitaxial layer 1001. …
FIG. 13 illustrates the formation of a GaN channel region 1301, which is formed in the removed portion(s) of the second GaN epitaxial layer 1101. The GaN …
FIG. 14 illustrates the formation of a GaN epitaxial structure 1401 above the GaN channel region 1301. The GaN epitaxial structure 1401, which eventually can …
FIG. 15 illustrates the formation of a metallic structure 1501 coupled with the GaN substrate 1000. The metallic structure 1501 provides a gate contact for the …
FIG. 16 illustrates the formation of additional metallic structures 1601 on the second GaN epitaxial layer 1101. The additional metallic structures 1601 serve …
FIG. 17, the formation of further metallic structures 1701, 1702 on the additional metallic structures 1601 and the GaN epitaxial structure 1401, respectively …
FIG. 18 is a simplified flowchart illustrating a method of fabricating a vertical JF ET with a regrown gate region according to an embodiment of the present …
FIG. 19 is a simplified flowchart illustrating a method of fabricating a vertical JFET 25 with a regrown channel region according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical JFET, the method comprising: providing a gallium nitride (GaN) substrate; forming an n-type GaN epitaxial layer coupled to the GaN substrate; forming a p-type GaN epitaxial layer coupled to the n-type GaN epitaxial layer, wherein the p-type GaN epitaxial layer is characterized by a p-type dopant concentration; removing at least a portion of the p-type GaN epitaxial layer to expose a portion of the n-type GaN epitaxial layer; forming an n-type GaN channel region coupled to the n-type GaN epitaxial layer and at least a portion of the p-type GaN epitaxial layer; forming an n-type GaN epitaxial structure coupled to the n-type GaN channel region; forming a first metallic structure electrically coupled to the GaN substrate; forming a second metallic structure electrically coupled to the p-type GaN epitaxial layer; and forming a third metallic structure electrically coupled to the n-type GaN epitaxial structure.
The method of claim 1 wherein a thickness of the n-type GaN epitaxial layer is between about 1 m and about 100 pm.
The method of claim 1 wherein the n-type GaN epitaxial layer is characterized by a first n-type dopant concentration, the n-type GaN channel region is characterized by a second n-type dopant concentration, and the n-type GaN epitaxial Page 2 of 5 App l. No. 14/604,600 PATENT Am dt. dated Response to Office Action of structure is characterized by a third n-type dopant concentration greater than the first n-type dopant concentration.
The method of claim 1 wherein the n-type GaN epitaxial layer comprises an n-type dopant including at least one of silicon and oxygen.
The method of claim [[1]]4 wherein at least one of the first n-type dopant concentration, the second n-type dopant concentration, or the third n-type dopant concentration varies as a function of thickness.
A method for fabricating an epitaxial structure, the method comp ri sing: providing a I II-nitride substrate; forming a first I II -nitride epitaxial layer of a first conductivity type coupled to the III -nitride substrate, wherein the first I II -nitride epitaxial layer has a first dopant concentration; forming a second I II -nitride epitaxial layer of a second conductivity type coupled to the first I II -nitride epitaxial layer, wherein the second I II -nitride epitaxial layer has a second dopant concentration; removing at least a portion of the second I II -nitride epitaxial layer to expose a surface of the first I II -nitride epitaxial layer; and forming a I II -nitride epitaxial channel region of the first conductivity type coupled to the surface of the first I II -nitride epitaxial layer, wherein the I II -nitride epitaxial channel region has a third dopant concentration.
The method of claim 7 further comprising forming a I II -nitride epitaxial structure of the first conductivity type coupled to the I II -nitride epitaxial channel region, the I II -nitride epitaxial structure having a dopant concentration greater than greater than the first dopant concentration.
The method of claim 7 wherein the first conductivity type is n type, and the second conductivity type is p type.
The method of claim 7 wherein at least one of the first dopant concentration, the second dopant concentration, or the third dopant concentration is non-uniform.
The method of claim 7 wherein a thickness of the first III- nitride epitaxial layer is between 1 p m and 100 pm. Page 4 of
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN JFET
vertical III-nitride JFET (generic)
Materials described outside the worked examples.
GaN substrate
GaN
III-nitride substrate
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 2-9 illustrate a process for creating a first type of vertical JFET that utilizes etching of an epitaxial layer to form the channel of the vertical JFET. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,324,844Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B shows the vertical JFET turned on, meaning the depletion regions 109 are 20 separated, allowing current to flow in a vertical direction 110 from the …
FIGS. 2-9 illustrate a process for creating a first type of vertical JFET that utilizes etching of an epitaxial layer to form the channel of the vertical JFET. …
FIG. 3 illustrates the formation of a second GaN epitaxial layer 301 above the first GaN epitaxial layer 201. The second GaN epitaxial layer 301, which …
FIG. 4 illustrates the formation of a third GaN epitaxial layer 401 above the second GaN epitaxial layer 301. The third GaN epitaxial layer 401, which …
FIG. 5. An outside angle 504 of greater than 90 degrees can facilitate deposition and/or regrowth of subsequent layers and can help improve 10 KILPATRICK …
FIG. 6 illustrates the formation of a fourth GaN epitaxial layer 601. The fourth GaN epitaxial layer 601, which forms gate portions of the vertical JFET 100, …
FIG. 7 illustrates the formation of a metallic structure 701 below the GaN substrate 200. The metallic structure 701 can be one or more layers of ohmic metal …
FIG. 8 illustrates the formation of additional metallic structures 801 on the fourth GaN epitaxial layer 601. The additional metallic structures 801 can be one …
FIG. 9, these metallic structures provide 25 for electrical connectivity to the drain, source, and gate of the vertical JFET. The various epitaxial layers do …
FIG. 10 is a simplified cross-sectional diagram illustrating the formation of a first GaN epitaxial layer 1 00 1 on a G aN substrate 1 000 to form a drift region …
FIG. 11 illustrates the formation of a second GaN epitaxial layer 1101 above the 20 first GaN epitaxial layer 1001. The second GaN epitaxial layer 1101, which …
FIG. 12 illustrates the removal of at least a portion of the second GaN epitaxial layer 1101 to expose a surface 1201 of the first GaN epitaxial layer 1001. …
FIG. 13 illustrates the formation of a GaN channel region 1301, which is formed in the removed portion(s) of the second GaN epitaxial layer 1101. The GaN …
FIG. 14 illustrates the formation of a GaN epitaxial structure 1401 above the GaN channel region 1301. The GaN epitaxial structure 1401, which eventually can …
FIG. 15 illustrates the formation of a metallic structure 1501 coupled with the GaN substrate 1000. The metallic structure 1501 provides a gate contact for the …
FIG. 16 illustrates the formation of additional metallic structures 1601 on the second GaN epitaxial layer 1101. The additional metallic structures 1601 serve …
FIG. 17, the formation of further metallic structures 1701, 1702 on the additional metallic structures 1601 and the GaN epitaxial structure 1401, respectively …
FIG. 18 is a simplified flowchart illustrating a method of fabricating a vertical JF ET with a regrown gate region according to an embodiment of the present …
FIG. 19 is a simplified flowchart illustrating a method of fabricating a vertical JFET 25 with a regrown channel region according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical JFET, the method comprising: providing a gallium nitride (GaN) substrate; forming an n-type GaN epitaxial layer coupled to the GaN substrate; forming a p-type GaN epitaxial layer coupled to the n-type GaN epitaxial layer, wherein the p-type GaN epitaxial layer is characterized by a p-type dopant concentration; removing at least a portion of the p-type GaN epitaxial layer to expose a portion of the n-type GaN epitaxial layer; forming an n-type GaN channel region coupled to the n-type GaN epitaxial layer and at least a portion of the p-type GaN epitaxial layer; forming an n-type GaN epitaxial structure coupled to the n-type GaN channel region; forming a first metallic structure electrically coupled to the GaN substrate; forming a second metallic structure electrically coupled to the p-type GaN epitaxial layer; and forming a third metallic structure electrically coupled to the n-type GaN epitaxial structure.
The method of claim 1 wherein a thickness of the n-type GaN epitaxial layer is between about 1 m and about 100 pm.
The method of claim 1 wherein the n-type GaN epitaxial layer is characterized by a first n-type dopant concentration, the n-type GaN channel region is characterized by a second n-type dopant concentration, and the n-type GaN epitaxial Page 2 of 5 App l. No. 14/604,600 PATENT Am dt. dated Response to Office Action of structure is characterized by a third n-type dopant concentration greater than the first n-type dopant concentration.
The method of claim 1 wherein the n-type GaN epitaxial layer comprises an n-type dopant including at least one of silicon and oxygen.
The method of claim [[1]]4 wherein at least one of the first n-type dopant concentration, the second n-type dopant concentration, or the third n-type dopant concentration varies as a function of thickness.
A method for fabricating an epitaxial structure, the method comp ri sing: providing a I II-nitride substrate; forming a first I II -nitride epitaxial layer of a first conductivity type coupled to the III -nitride substrate, wherein the first I II -nitride epitaxial layer has a first dopant concentration; forming a second I II -nitride epitaxial layer of a second conductivity type coupled to the first I II -nitride epitaxial layer, wherein the second I II -nitride epitaxial layer has a second dopant concentration; removing at least a portion of the second I II -nitride epitaxial layer to expose a surface of the first I II -nitride epitaxial layer; and forming a I II -nitride epitaxial channel region of the first conductivity type coupled to the surface of the first I II -nitride epitaxial layer, wherein the I II -nitride epitaxial channel region has a third dopant concentration.
The method of claim 7 further comprising forming a I II -nitride epitaxial structure of the first conductivity type coupled to the I II -nitride epitaxial channel region, the I II -nitride epitaxial structure having a dopant concentration greater than greater than the first dopant concentration.
The method of claim 7 wherein the first conductivity type is n type, and the second conductivity type is p type.
The method of claim 7 wherein at least one of the first dopant concentration, the second dopant concentration, or the third dopant concentration is non-uniform.
The method of claim 7 wherein a thickness of the first III- nitride epitaxial layer is between 1 p m and 100 pm. Page 4 of
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN JFET
vertical III-nitride JFET (generic)
Materials described outside the worked examples.
GaN substrate
GaN
III-nitride substrate
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 2-9 illustrate a process for creating a first type of vertical JFET that utilizes etching of an epitaxial layer to form the channel of the vertical JFET. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
vertical III-nitride field effect transistor
first III-nitride epitaxial layer (first conductivity type)
second III-nitride epitaxial layer (second conductivity type)
III-nitride epitaxial channel region (first conductivity type)
III-nitride epitaxial structure (first conductivity type, high dopant concentration)
FIG. 9, these metallic structures provide 25 for electrical connectivity to the drain, source, and gate of the vertical JFET. The various epitaxial layers do …
FIG. 9, these metallic structures provide 25 for electrical connectivity to the drain, source, and gate of the vertical JFET. The various epitaxial layers do …
vertical III-nitride field effect transistor
first III-nitride epitaxial layer (first conductivity type)
second III-nitride epitaxial layer (second conductivity type)
III-nitride epitaxial channel region (first conductivity type)
III-nitride epitaxial structure (first conductivity type, high dopant concentration)
FIG. 9, these metallic structures provide 25 for electrical connectivity to the drain, source, and gate of the vertical JFET. The various epitaxial layers do …
FIG. 9, these metallic structures provide 25 for electrical connectivity to the drain, source, and gate of the vertical JFET. The various epitaxial layers do …
vertical III-nitride field effect transistor
first III-nitride epitaxial layer (first conductivity type)
second III-nitride epitaxial layer (second conductivity type)
III-nitride epitaxial channel region (first conductivity type)
III-nitride epitaxial structure (first conductivity type, high dopant concentration)
FIG. 9, these metallic structures provide 25 for electrical connectivity to the drain, source, and gate of the vertical JFET. The various epitaxial layers do …
FIG. 9, these metallic structures provide 25 for electrical connectivity to the drain, source, and gate of the vertical JFET. The various epitaxial layers do …
vertical III-nitride field effect transistor
first III-nitride epitaxial layer (first conductivity type)
second III-nitride epitaxial layer (second conductivity type)
III-nitride epitaxial channel region (first conductivity type)
III-nitride epitaxial structure (first conductivity type, high dopant concentration)
FIG. 9, these metallic structures provide 25 for electrical connectivity to the drain, source, and gate of the vertical JFET. The various epitaxial layers do …
FIG. 9, these metallic structures provide 25 for electrical connectivity to the drain, source, and gate of the vertical JFET. The various epitaxial layers do …