GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | Matter42 Literature
Patent
Atlas literature
Patent
US 11,810,783 B2
GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Chiaki Sasaoka, Jun Kojima, Shoichi Onda, Masatake Nagaya et al.
DENSO CORPORATION, Kariya (JP), HAMAMATSU PHOTONICS K.K., Hamamatsu (JP), National University Corporation Tokai National Higher Education and Research System, Nagoya (JP)·Nov. 7, 2023·US
Drawings
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1
FIG. 1H is a cross-sectional view illustrating a manufac- turing process of the semiconductor device subsequent to
FIG. 2
FIG. 2 is a map showing irradiation positions of laser irradiation;
FIG. 3
FIG. 3 is an enlarged view of a part of the irradiation position of the laser irradiation shown in
FIG. 4
FIG. 4B is an exaggerated view of a cross section of the other surface of the chip formation wafer after the flattening step;
FIG. 5
FIG. 5B is a diagram showing I-V characteristics of a semiconductor chip constituting a GaN semiconductor device in a comparative example; and
FIG. 6
FIG. 6 is a schematic diagram of an I-V evaluation system for evaluating the I-V characteristics shown in
FIG. 8
FIG. 8. It should be noted that in this disclosure (including the abstract, drawings, description, and claims), the terms “convex” and “concave” are used with …
FIG. 13
FIG. 13, each semiconductor chip 100 is configured by individualizing the chip formation wafer 30 into chip units by a dicing saw, laser dicing, or the 40 like. …
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
According to this, for example, even when the wafer transformation layer 15 is formed in the GaN wafer 1, it becomes easy to remain a thickness equal to or more than a B₂ predetermined thickness as the recycle wafer 40, and the number of times that the recycle wafer can be recycled can be increased. Further, in the first and second embodiments, the step of forming the wafer transformation layer 15 of FIG. 1E may be performed before the step of arranging the support member 20 of FIG. 1D. In this case, the laser beam L may be irradiated from the one surface 10a of the processed wafer 10. Here, when the laser beam L is irradiated from the one surface 10a of the processed wafer 10, the position of the condensing point of the laser beam L may vary depend-ing on the surface electrode, the wiring pattern, or the like formed on the one surface 10a side. Therefore, it may be preferable to irradiate the laser beam from the other surface 10b of the processed wafer 10. While the present disclosure has been described with reference to embodiments thereof, it is to be understood that the disclosure is not limited to the embodiments and con-structions. The present disclosure is intended to cover vari-ous modification and equivalent arrangements. In addition, while the various combinations and configurations, other combinations and configurations, including more, less or only a single element, are also within the spirit and scope of the present disclosure. What is claimed is:
The gallium nitride semiconductor device according to claim 1, wherein: a height of each of the plurality of convex portions from an adjacent concave portion is in a range between 5 µm and 30 µm.
The gallium nitride semiconductor device according to claim 1, wherein: a surface of each of the concave portions includes a surface roughness provided by a nitrogen vacancy and a laser irradiation mark.
The gallium nitride semiconductor device according to claim 1, wherein: the other surface of the chip formation substrate in contact with the metal film is made of n type gallium nitride.
The gallium nitride semiconductor device according to claim 1, wherein: some parts of the metal film entering the concave portions provide wedges having different maximum heights.
The gallium nitride semiconductor device according to claim 1, wherein: a side surface of each convex portion has a surface roughness finer than a predetermined value due to a nitrogen vacancy and a dent. ∗ ∗ ∗ ∗ ∗
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
vertical gallium nitride semiconductor device
metal film (ohmic contact with n-GaN)back surface electrode metal film
GaNback surface electrode contact
GaNchip formation substrate
Materials
Materials described outside the worked examples.
gallium nitride
GaN
Chip Formation Substrate
Back Surface Contact LayerSubstrate Wafer
metal film (ohmic contact with n-GaN)
Back Surface Electrode
Process steps
Additional fabrication and treatment steps described in the patent.
1
Laser Irradiation Slicing
Step 1
Process details
description:Laser irradiation of processed GaN wafer to form transformation layer (nitrogen evaporates as gas, liquid gallium precipitates); wafer divided into chip formation wafer and recycle wafer
transformation layer location:epitaxial growth film and/or GaN wafer
Materials:GaN
Characterization
Measurements and analyses referenced in the patent, with their drawing references.
fet electrical
Fet Electrical
FIG. 5B is a diagram showing I-V characteristics of a semiconductor chip constituting a GaN semiconductor device in a comparative example; and
GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Chiaki Sasaoka, Jun Kojima, Shoichi Onda, Masatake Nagaya et al.
DENSO CORPORATION, Kariya (JP), HAMAMATSU PHOTONICS K.K., Hamamatsu (JP), National University Corporation Tokai National Higher Education and Research System, Nagoya (JP)·Nov. 7, 2023·US
Drawings
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1
FIG. 1H is a cross-sectional view illustrating a manufac- turing process of the semiconductor device subsequent to
FIG. 2
FIG. 2 is a map showing irradiation positions of laser irradiation;
FIG. 3
FIG. 3 is an enlarged view of a part of the irradiation position of the laser irradiation shown in
FIG. 4
FIG. 4B is an exaggerated view of a cross section of the other surface of the chip formation wafer after the flattening step;
FIG. 5
FIG. 5B is a diagram showing I-V characteristics of a semiconductor chip constituting a GaN semiconductor device in a comparative example; and
FIG. 6
FIG. 6 is a schematic diagram of an I-V evaluation system for evaluating the I-V characteristics shown in
FIG. 8
FIG. 8. It should be noted that in this disclosure (including the abstract, drawings, description, and claims), the terms “convex” and “concave” are used with …
FIG. 13
FIG. 13, each semiconductor chip 100 is configured by individualizing the chip formation wafer 30 into chip units by a dicing saw, laser dicing, or the 40 like. …
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
According to this, for example, even when the wafer transformation layer 15 is formed in the GaN wafer 1, it becomes easy to remain a thickness equal to or more than a B₂ predetermined thickness as the recycle wafer 40, and the number of times that the recycle wafer can be recycled can be increased. Further, in the first and second embodiments, the step of forming the wafer transformation layer 15 of FIG. 1E may be performed before the step of arranging the support member 20 of FIG. 1D. In this case, the laser beam L may be irradiated from the one surface 10a of the processed wafer 10. Here, when the laser beam L is irradiated from the one surface 10a of the processed wafer 10, the position of the condensing point of the laser beam L may vary depend-ing on the surface electrode, the wiring pattern, or the like formed on the one surface 10a side. Therefore, it may be preferable to irradiate the laser beam from the other surface 10b of the processed wafer 10. While the present disclosure has been described with reference to embodiments thereof, it is to be understood that the disclosure is not limited to the embodiments and con-structions. The present disclosure is intended to cover vari-ous modification and equivalent arrangements. In addition, while the various combinations and configurations, other combinations and configurations, including more, less or only a single element, are also within the spirit and scope of the present disclosure. What is claimed is:
The gallium nitride semiconductor device according to claim 1, wherein: a height of each of the plurality of convex portions from an adjacent concave portion is in a range between 5 µm and 30 µm.
The gallium nitride semiconductor device according to claim 1, wherein: a surface of each of the concave portions includes a surface roughness provided by a nitrogen vacancy and a laser irradiation mark.
The gallium nitride semiconductor device according to claim 1, wherein: the other surface of the chip formation substrate in contact with the metal film is made of n type gallium nitride.
The gallium nitride semiconductor device according to claim 1, wherein: some parts of the metal film entering the concave portions provide wedges having different maximum heights.
The gallium nitride semiconductor device according to claim 1, wherein: a side surface of each convex portion has a surface roughness finer than a predetermined value due to a nitrogen vacancy and a dent. ∗ ∗ ∗ ∗ ∗
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
vertical gallium nitride semiconductor device
metal film (ohmic contact with n-GaN)back surface electrode metal film
GaNback surface electrode contact
GaNchip formation substrate
Materials
Materials described outside the worked examples.
gallium nitride
GaN
Chip Formation Substrate
Back Surface Contact LayerSubstrate Wafer
metal film (ohmic contact with n-GaN)
Back Surface Electrode
Process steps
Additional fabrication and treatment steps described in the patent.
1
Laser Irradiation Slicing
Step 1
Process details
description:Laser irradiation of processed GaN wafer to form transformation layer (nitrogen evaporates as gas, liquid gallium precipitates); wafer divided into chip formation wafer and recycle wafer
transformation layer location:epitaxial growth film and/or GaN wafer
Materials:GaN
Characterization
Measurements and analyses referenced in the patent, with their drawing references.
fet electrical
Fet Electrical
FIG. 5B is a diagram showing I-V characteristics of a semiconductor chip constituting a GaN semiconductor device in a comparative example; and
GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Chiaki Sasaoka, Jun Kojima, Shoichi Onda, Masatake Nagaya et al.
DENSO CORPORATION, Kariya (JP), HAMAMATSU PHOTONICS K.K., Hamamatsu (JP), National University Corporation Tokai National Higher Education and Research System, Nagoya (JP)·Nov. 7, 2023·US
Drawings
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1
FIG. 1H is a cross-sectional view illustrating a manufac- turing process of the semiconductor device subsequent to
FIG. 2
FIG. 2 is a map showing irradiation positions of laser irradiation;
FIG. 3
FIG. 3 is an enlarged view of a part of the irradiation position of the laser irradiation shown in
FIG. 4
FIG. 4B is an exaggerated view of a cross section of the other surface of the chip formation wafer after the flattening step;
FIG. 5
FIG. 5B is a diagram showing I-V characteristics of a semiconductor chip constituting a GaN semiconductor device in a comparative example; and
FIG. 6
FIG. 6 is a schematic diagram of an I-V evaluation system for evaluating the I-V characteristics shown in
FIG. 8
FIG. 8. It should be noted that in this disclosure (including the abstract, drawings, description, and claims), the terms “convex” and “concave” are used with …
FIG. 13
FIG. 13, each semiconductor chip 100 is configured by individualizing the chip formation wafer 30 into chip units by a dicing saw, laser dicing, or the 40 like. …
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
According to this, for example, even when the wafer transformation layer 15 is formed in the GaN wafer 1, it becomes easy to remain a thickness equal to or more than a B₂ predetermined thickness as the recycle wafer 40, and the number of times that the recycle wafer can be recycled can be increased. Further, in the first and second embodiments, the step of forming the wafer transformation layer 15 of FIG. 1E may be performed before the step of arranging the support member 20 of FIG. 1D. In this case, the laser beam L may be irradiated from the one surface 10a of the processed wafer 10. Here, when the laser beam L is irradiated from the one surface 10a of the processed wafer 10, the position of the condensing point of the laser beam L may vary depend-ing on the surface electrode, the wiring pattern, or the like formed on the one surface 10a side. Therefore, it may be preferable to irradiate the laser beam from the other surface 10b of the processed wafer 10. While the present disclosure has been described with reference to embodiments thereof, it is to be understood that the disclosure is not limited to the embodiments and con-structions. The present disclosure is intended to cover vari-ous modification and equivalent arrangements. In addition, while the various combinations and configurations, other combinations and configurations, including more, less or only a single element, are also within the spirit and scope of the present disclosure. What is claimed is:
The gallium nitride semiconductor device according to claim 1, wherein: a height of each of the plurality of convex portions from an adjacent concave portion is in a range between 5 µm and 30 µm.
The gallium nitride semiconductor device according to claim 1, wherein: a surface of each of the concave portions includes a surface roughness provided by a nitrogen vacancy and a laser irradiation mark.
The gallium nitride semiconductor device according to claim 1, wherein: the other surface of the chip formation substrate in contact with the metal film is made of n type gallium nitride.
The gallium nitride semiconductor device according to claim 1, wherein: some parts of the metal film entering the concave portions provide wedges having different maximum heights.
The gallium nitride semiconductor device according to claim 1, wherein: a side surface of each convex portion has a surface roughness finer than a predetermined value due to a nitrogen vacancy and a dent. ∗ ∗ ∗ ∗ ∗
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
vertical gallium nitride semiconductor device
metal film (ohmic contact with n-GaN)back surface electrode metal film
GaNback surface electrode contact
GaNchip formation substrate
Materials
Materials described outside the worked examples.
gallium nitride
GaN
Chip Formation Substrate
Back Surface Contact LayerSubstrate Wafer
metal film (ohmic contact with n-GaN)
Back Surface Electrode
Process steps
Additional fabrication and treatment steps described in the patent.
1
Laser Irradiation Slicing
Step 1
Process details
description:Laser irradiation of processed GaN wafer to form transformation layer (nitrogen evaporates as gas, liquid gallium precipitates); wafer divided into chip formation wafer and recycle wafer
transformation layer location:epitaxial growth film and/or GaN wafer
Materials:GaN
Characterization
Measurements and analyses referenced in the patent, with their drawing references.
fet electrical
Fet Electrical
FIG. 5B is a diagram showing I-V characteristics of a semiconductor chip constituting a GaN semiconductor device in a comparative example; and
GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Chiaki Sasaoka, Jun Kojima, Shoichi Onda, Masatake Nagaya et al.
DENSO CORPORATION, Kariya (JP), HAMAMATSU PHOTONICS K.K., Hamamatsu (JP), National University Corporation Tokai National Higher Education and Research System, Nagoya (JP)·Nov. 7, 2023·US
Drawings
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1
FIG. 1H is a cross-sectional view illustrating a manufac- turing process of the semiconductor device subsequent to
FIG. 2
FIG. 2 is a map showing irradiation positions of laser irradiation;
FIG. 3
FIG. 3 is an enlarged view of a part of the irradiation position of the laser irradiation shown in
FIG. 4
FIG. 4B is an exaggerated view of a cross section of the other surface of the chip formation wafer after the flattening step;
FIG. 5
FIG. 5B is a diagram showing I-V characteristics of a semiconductor chip constituting a GaN semiconductor device in a comparative example; and
FIG. 6
FIG. 6 is a schematic diagram of an I-V evaluation system for evaluating the I-V characteristics shown in
FIG. 8
FIG. 8. It should be noted that in this disclosure (including the abstract, drawings, description, and claims), the terms “convex” and “concave” are used with …
FIG. 13
FIG. 13, each semiconductor chip 100 is configured by individualizing the chip formation wafer 30 into chip units by a dicing saw, laser dicing, or the 40 like. …
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
According to this, for example, even when the wafer transformation layer 15 is formed in the GaN wafer 1, it becomes easy to remain a thickness equal to or more than a B₂ predetermined thickness as the recycle wafer 40, and the number of times that the recycle wafer can be recycled can be increased. Further, in the first and second embodiments, the step of forming the wafer transformation layer 15 of FIG. 1E may be performed before the step of arranging the support member 20 of FIG. 1D. In this case, the laser beam L may be irradiated from the one surface 10a of the processed wafer 10. Here, when the laser beam L is irradiated from the one surface 10a of the processed wafer 10, the position of the condensing point of the laser beam L may vary depend-ing on the surface electrode, the wiring pattern, or the like formed on the one surface 10a side. Therefore, it may be preferable to irradiate the laser beam from the other surface 10b of the processed wafer 10. While the present disclosure has been described with reference to embodiments thereof, it is to be understood that the disclosure is not limited to the embodiments and con-structions. The present disclosure is intended to cover vari-ous modification and equivalent arrangements. In addition, while the various combinations and configurations, other combinations and configurations, including more, less or only a single element, are also within the spirit and scope of the present disclosure. What is claimed is:
The gallium nitride semiconductor device according to claim 1, wherein: a height of each of the plurality of convex portions from an adjacent concave portion is in a range between 5 µm and 30 µm.
The gallium nitride semiconductor device according to claim 1, wherein: a surface of each of the concave portions includes a surface roughness provided by a nitrogen vacancy and a laser irradiation mark.
The gallium nitride semiconductor device according to claim 1, wherein: the other surface of the chip formation substrate in contact with the metal film is made of n type gallium nitride.
The gallium nitride semiconductor device according to claim 1, wherein: some parts of the metal film entering the concave portions provide wedges having different maximum heights.
The gallium nitride semiconductor device according to claim 1, wherein: a side surface of each convex portion has a surface roughness finer than a predetermined value due to a nitrogen vacancy and a dent. ∗ ∗ ∗ ∗ ∗
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
vertical gallium nitride semiconductor device
metal film (ohmic contact with n-GaN)back surface electrode metal film
GaNback surface electrode contact
GaNchip formation substrate
Materials
Materials described outside the worked examples.
gallium nitride
GaN
Chip Formation Substrate
Back Surface Contact LayerSubstrate Wafer
metal film (ohmic contact with n-GaN)
Back Surface Electrode
Process steps
Additional fabrication and treatment steps described in the patent.
1
Laser Irradiation Slicing
Step 1
Process details
description:Laser irradiation of processed GaN wafer to form transformation layer (nitrogen evaporates as gas, liquid gallium precipitates); wafer divided into chip formation wafer and recycle wafer
transformation layer location:epitaxial growth film and/or GaN wafer
Materials:GaN
Characterization
Measurements and analyses referenced in the patent, with their drawing references.
fet electrical
Fet Electrical
FIG. 5B is a diagram showing I-V characteristics of a semiconductor chip constituting a GaN semiconductor device in a comparative example; and
description:Flattening of upper base surface of trapezoidal convex portions on other surface of chip formation wafer after laser irradiation division, while leaving irregularities; CMP or similar
Materials:GaN
3
Metal Film Deposition
Step 3
Process details
description:Forming metal film as back surface electrode on other surface of chip formation wafer with remaining irregularities (trapezoidal convex portions and concave portions)
Materials:metal film (ohmic contact with n-GaN)
4
Epitaxial Growth
Step 4
Process details
description:Forming epitaxial growth film on one surface of GaN wafer to prepare processed wafer with plurality of chip formation regions
Materials:GaN
fet electrical
Fet Electrical
FIG. 6 is a schematic diagram of an I-V evaluation system for evaluating the I-V characteristics shown in
US 2009/0022193 A12009/0022193 A1 * 1/2009 Hasegawa......... H01L 21/28575examiner
US 2009/0095973 A12009/0095973 A1 4/2009 Tanaka et al.
US 2009/0233394 A12009/0233394 A1 9/2009 Batres et al.
US 2010/0273280 A12010/0273280 A1 10/2010 Batres et al.
US 2011/0169030 A12011/0169030 A1 7/2011 Li
US 2020/0180082 A12020/0180082 A1 6/2020 Tanaka et al.
Cited non-patent literature · 2
U.S. Appl. No. 17/229,137, filed Apr. 13, 2021, Nagaya et al.
Study of GaN light-emitting diodes fabricated by laser lift-off technique. U.S. Appl. No. 17/229,356, filed Apr. 13, 2021, Kojima et al. Chen-Fu Chu et al., “Study of GaN light-emitting diodes fabricated by laser lift-off technique”, Journal of Applied Physics, vol. 95, No. 8, P3916, 2004.
description:Flattening of upper base surface of trapezoidal convex portions on other surface of chip formation wafer after laser irradiation division, while leaving irregularities; CMP or similar
Materials:GaN
3
Metal Film Deposition
Step 3
Process details
description:Forming metal film as back surface electrode on other surface of chip formation wafer with remaining irregularities (trapezoidal convex portions and concave portions)
Materials:metal film (ohmic contact with n-GaN)
4
Epitaxial Growth
Step 4
Process details
description:Forming epitaxial growth film on one surface of GaN wafer to prepare processed wafer with plurality of chip formation regions
Materials:GaN
fet electrical
Fet Electrical
FIG. 6 is a schematic diagram of an I-V evaluation system for evaluating the I-V characteristics shown in
US 2009/0022193 A12009/0022193 A1 * 1/2009 Hasegawa......... H01L 21/28575examiner
US 2009/0095973 A12009/0095973 A1 4/2009 Tanaka et al.
US 2009/0233394 A12009/0233394 A1 9/2009 Batres et al.
US 2010/0273280 A12010/0273280 A1 10/2010 Batres et al.
US 2011/0169030 A12011/0169030 A1 7/2011 Li
US 2020/0180082 A12020/0180082 A1 6/2020 Tanaka et al.
Cited non-patent literature · 2
U.S. Appl. No. 17/229,137, filed Apr. 13, 2021, Nagaya et al.
Study of GaN light-emitting diodes fabricated by laser lift-off technique. U.S. Appl. No. 17/229,356, filed Apr. 13, 2021, Kojima et al. Chen-Fu Chu et al., “Study of GaN light-emitting diodes fabricated by laser lift-off technique”, Journal of Applied Physics, vol. 95, No. 8, P3916, 2004.
description:Flattening of upper base surface of trapezoidal convex portions on other surface of chip formation wafer after laser irradiation division, while leaving irregularities; CMP or similar
Materials:GaN
3
Metal Film Deposition
Step 3
Process details
description:Forming metal film as back surface electrode on other surface of chip formation wafer with remaining irregularities (trapezoidal convex portions and concave portions)
Materials:metal film (ohmic contact with n-GaN)
4
Epitaxial Growth
Step 4
Process details
description:Forming epitaxial growth film on one surface of GaN wafer to prepare processed wafer with plurality of chip formation regions
Materials:GaN
fet electrical
Fet Electrical
FIG. 6 is a schematic diagram of an I-V evaluation system for evaluating the I-V characteristics shown in
US 2009/0022193 A12009/0022193 A1 * 1/2009 Hasegawa......... H01L 21/28575examiner
US 2009/0095973 A12009/0095973 A1 4/2009 Tanaka et al.
US 2009/0233394 A12009/0233394 A1 9/2009 Batres et al.
US 2010/0273280 A12010/0273280 A1 10/2010 Batres et al.
US 2011/0169030 A12011/0169030 A1 7/2011 Li
US 2020/0180082 A12020/0180082 A1 6/2020 Tanaka et al.
Cited non-patent literature · 2
U.S. Appl. No. 17/229,137, filed Apr. 13, 2021, Nagaya et al.
Study of GaN light-emitting diodes fabricated by laser lift-off technique. U.S. Appl. No. 17/229,356, filed Apr. 13, 2021, Kojima et al. Chen-Fu Chu et al., “Study of GaN light-emitting diodes fabricated by laser lift-off technique”, Journal of Applied Physics, vol. 95, No. 8, P3916, 2004.
description:Flattening of upper base surface of trapezoidal convex portions on other surface of chip formation wafer after laser irradiation division, while leaving irregularities; CMP or similar
Materials:GaN
3
Metal Film Deposition
Step 3
Process details
description:Forming metal film as back surface electrode on other surface of chip formation wafer with remaining irregularities (trapezoidal convex portions and concave portions)
Materials:metal film (ohmic contact with n-GaN)
4
Epitaxial Growth
Step 4
Process details
description:Forming epitaxial growth film on one surface of GaN wafer to prepare processed wafer with plurality of chip formation regions
Materials:GaN
fet electrical
Fet Electrical
FIG. 6 is a schematic diagram of an I-V evaluation system for evaluating the I-V characteristics shown in
US 2009/0022193 A12009/0022193 A1 * 1/2009 Hasegawa......... H01L 21/28575examiner
US 2009/0095973 A12009/0095973 A1 4/2009 Tanaka et al.
US 2009/0233394 A12009/0233394 A1 9/2009 Batres et al.
US 2010/0273280 A12010/0273280 A1 10/2010 Batres et al.
US 2011/0169030 A12011/0169030 A1 7/2011 Li
US 2020/0180082 A12020/0180082 A1 6/2020 Tanaka et al.
Cited non-patent literature · 2
U.S. Appl. No. 17/229,137, filed Apr. 13, 2021, Nagaya et al.
Study of GaN light-emitting diodes fabricated by laser lift-off technique. U.S. Appl. No. 17/229,356, filed Apr. 13, 2021, Kojima et al. Chen-Fu Chu et al., “Study of GaN light-emitting diodes fabricated by laser lift-off technique”, Journal of Applied Physics, vol. 95, No. 8, P3916, 2004.