Patent
US 10,811,501InN TUNNEL JUNCTION CONTACTS FOR P-CHANNEL GaN
RADOSAVLJEVIC, Marko, DASGUPTA, Sansaptak, THEN, Han Wui
INTEL CORPORATION·05 April 2018·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,811,501Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example horizontal transistor stack. [0007]
FIG. 2 illustrates an example energy band diagram for certain the semiconductor materials of
FIGS. 3A-3G illustrate a selective epitaxy process to generate the horizontal transistor stack of the example of
FIG. 4 to implement the examples disclosed herein. [0011] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the …
FIG. 5 is a block diagram of an example processor platform capable of executing the instructions of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus comprising: a substrate comprising Gallium Nitride (GaN); a first material over a first region of the substrate, the first material comprising p-type GaN; a second material adjacent to the first material and en over a second region of the substrate, the second material comprising p-type Indium Nitride (InN); and [[an]] a third material adjacent to the second material and over a third region of the substrate, the third material comprising n-type Indium Gallium Nitride (InGaN). Currently amended
The apparatus of claim 1, wherein the substrate comprises a first horizontal surface, a vertical surface ad j acent the first horizontal surface, and a second horizontal surface adjacent the vertical surface and vertically above the first horizontal surface, wherein the first, second, and third materials are over the first horizontal surface and the first material is adj acent the vertical surface of the substrate. Currently amended
The apparatus of claim 1, wherein the first material comprises p- type GaN having a dopant concentration between le1 6/centimeters 3 and le1 7/centimeters 3 Currently amended
The apparatus of claim 1, wherein the second material comprises p- type InN having a dopant concentration between 5e 1 9/centimeters 3 and le2 1/centimeters 3 Currently amended
The apparatus of claim 1, wherein the third material comprises n- type InGaN having a dopant concentration between 5e1 9/centimeters 3 and le2 1/centimeters 3 Currently amended
The apparatus of claim 1, wherein a portion of the first material extends over the second and third regions and under the second and third materials. New
The apparatus of claim 1, wherein the substrate comprises p-type GaN. New
An electronic device comprising: a substrate comprising Gallium Nitride (GaN), the substrate having a first horizontal surface, first and second vertical surfaces to first and second sides of the first horizontal surface, respectively,, and second and third horizontal surfaces adjacent to the first and second vertical surfaces, respectively; a dielectric material on the first horizontal surface; a gate on the dielectric material; first and second materials interfaced with the first and second vertical surfaces, respectively, and the second and third horizontal surfaces, respectively, the first and second materials each comprising p-type GaN; third and fourth materials interfaced with the first and second materials, respectively, the third and fourth materials each comprising p-type Indium Nitride (InN); fifth and sixth materials interfaced with the third and fourth materials, respectively, the fifth and sixth materials each comprising n-type Indium Gallium Nitride (InGaN); a source on the fifth material; and a drain on the sixth material. Currently amended
The electronic device of claim 6, wherein the substrate i s comprises p-type GaN. Currently amended
The electronic device of claim 6, wherein the first and second materials each comprise p-type GaN having a dopant concentration of between 1e 16/centimeters 3 and 1e 17/centimeters 3. Currently amended
The electronic device of claim 6, wherein the third and fourth materials each comprise p-type InN having a dopant concentration of between 5e19/centimeters 3 and 1e2 1/centimeters 3. Currently amended
The electronic device of claim 6, wherein the fifth and sixth materials each comprise the n-type InGaN having a dopant concentration of between 5e 19/centimeters 3 and 1e2 1/centimeters
The electronic device of claim 6, wherein the dielectric material has a permittivity o f greater than 3.9. Currently amended
15-22 Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
p-channel GaN transistor with InN tunnel junction contacts
p-channel GaN MOS-HEMT electronic device
Materials described outside the worked examples.
p-type GaN (substrate)
GaN
p-type InN
InN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an example horizontal transistor stack. [0007]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 0.7 eV | InN |
Optical Band Gap |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,811,501Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example horizontal transistor stack. [0007]
FIG. 2 illustrates an example energy band diagram for certain the semiconductor materials of
FIGS. 3A-3G illustrate a selective epitaxy process to generate the horizontal transistor stack of the example of
FIG. 4 to implement the examples disclosed herein. [0011] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the …
FIG. 5 is a block diagram of an example processor platform capable of executing the instructions of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus comprising: a substrate comprising Gallium Nitride (GaN); a first material over a first region of the substrate, the first material comprising p-type GaN; a second material adjacent to the first material and en over a second region of the substrate, the second material comprising p-type Indium Nitride (InN); and [[an]] a third material adjacent to the second material and over a third region of the substrate, the third material comprising n-type Indium Gallium Nitride (InGaN). Currently amended
The apparatus of claim 1, wherein the substrate comprises a first horizontal surface, a vertical surface ad j acent the first horizontal surface, and a second horizontal surface adjacent the vertical surface and vertically above the first horizontal surface, wherein the first, second, and third materials are over the first horizontal surface and the first material is adj acent the vertical surface of the substrate. Currently amended
The apparatus of claim 1, wherein the first material comprises p- type GaN having a dopant concentration between le1 6/centimeters 3 and le1 7/centimeters 3 Currently amended
The apparatus of claim 1, wherein the second material comprises p- type InN having a dopant concentration between 5e 1 9/centimeters 3 and le2 1/centimeters 3 Currently amended
The apparatus of claim 1, wherein the third material comprises n- type InGaN having a dopant concentration between 5e1 9/centimeters 3 and le2 1/centimeters 3 Currently amended
The apparatus of claim 1, wherein a portion of the first material extends over the second and third regions and under the second and third materials. New
The apparatus of claim 1, wherein the substrate comprises p-type GaN. New
An electronic device comprising: a substrate comprising Gallium Nitride (GaN), the substrate having a first horizontal surface, first and second vertical surfaces to first and second sides of the first horizontal surface, respectively,, and second and third horizontal surfaces adjacent to the first and second vertical surfaces, respectively; a dielectric material on the first horizontal surface; a gate on the dielectric material; first and second materials interfaced with the first and second vertical surfaces, respectively, and the second and third horizontal surfaces, respectively, the first and second materials each comprising p-type GaN; third and fourth materials interfaced with the first and second materials, respectively, the third and fourth materials each comprising p-type Indium Nitride (InN); fifth and sixth materials interfaced with the third and fourth materials, respectively, the fifth and sixth materials each comprising n-type Indium Gallium Nitride (InGaN); a source on the fifth material; and a drain on the sixth material. Currently amended
The electronic device of claim 6, wherein the substrate i s comprises p-type GaN. Currently amended
The electronic device of claim 6, wherein the first and second materials each comprise p-type GaN having a dopant concentration of between 1e 16/centimeters 3 and 1e 17/centimeters 3. Currently amended
The electronic device of claim 6, wherein the third and fourth materials each comprise p-type InN having a dopant concentration of between 5e19/centimeters 3 and 1e2 1/centimeters 3. Currently amended
The electronic device of claim 6, wherein the fifth and sixth materials each comprise the n-type InGaN having a dopant concentration of between 5e 19/centimeters 3 and 1e2 1/centimeters
The electronic device of claim 6, wherein the dielectric material has a permittivity o f greater than 3.9. Currently amended
15-22 Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
p-channel GaN transistor with InN tunnel junction contacts
p-channel GaN MOS-HEMT electronic device
Materials described outside the worked examples.
p-type GaN (substrate)
GaN
p-type InN
InN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an example horizontal transistor stack. [0007]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 0.7 eV | InN |
Optical Band Gap |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,811,501Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example horizontal transistor stack. [0007]
FIG. 2 illustrates an example energy band diagram for certain the semiconductor materials of
FIGS. 3A-3G illustrate a selective epitaxy process to generate the horizontal transistor stack of the example of
FIG. 4 to implement the examples disclosed herein. [0011] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the …
FIG. 5 is a block diagram of an example processor platform capable of executing the instructions of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus comprising: a substrate comprising Gallium Nitride (GaN); a first material over a first region of the substrate, the first material comprising p-type GaN; a second material adjacent to the first material and en over a second region of the substrate, the second material comprising p-type Indium Nitride (InN); and [[an]] a third material adjacent to the second material and over a third region of the substrate, the third material comprising n-type Indium Gallium Nitride (InGaN). Currently amended
The apparatus of claim 1, wherein the substrate comprises a first horizontal surface, a vertical surface ad j acent the first horizontal surface, and a second horizontal surface adjacent the vertical surface and vertically above the first horizontal surface, wherein the first, second, and third materials are over the first horizontal surface and the first material is adj acent the vertical surface of the substrate. Currently amended
The apparatus of claim 1, wherein the first material comprises p- type GaN having a dopant concentration between le1 6/centimeters 3 and le1 7/centimeters 3 Currently amended
The apparatus of claim 1, wherein the second material comprises p- type InN having a dopant concentration between 5e 1 9/centimeters 3 and le2 1/centimeters 3 Currently amended
The apparatus of claim 1, wherein the third material comprises n- type InGaN having a dopant concentration between 5e1 9/centimeters 3 and le2 1/centimeters 3 Currently amended
The apparatus of claim 1, wherein a portion of the first material extends over the second and third regions and under the second and third materials. New
The apparatus of claim 1, wherein the substrate comprises p-type GaN. New
An electronic device comprising: a substrate comprising Gallium Nitride (GaN), the substrate having a first horizontal surface, first and second vertical surfaces to first and second sides of the first horizontal surface, respectively,, and second and third horizontal surfaces adjacent to the first and second vertical surfaces, respectively; a dielectric material on the first horizontal surface; a gate on the dielectric material; first and second materials interfaced with the first and second vertical surfaces, respectively, and the second and third horizontal surfaces, respectively, the first and second materials each comprising p-type GaN; third and fourth materials interfaced with the first and second materials, respectively, the third and fourth materials each comprising p-type Indium Nitride (InN); fifth and sixth materials interfaced with the third and fourth materials, respectively, the fifth and sixth materials each comprising n-type Indium Gallium Nitride (InGaN); a source on the fifth material; and a drain on the sixth material. Currently amended
The electronic device of claim 6, wherein the substrate i s comprises p-type GaN. Currently amended
The electronic device of claim 6, wherein the first and second materials each comprise p-type GaN having a dopant concentration of between 1e 16/centimeters 3 and 1e 17/centimeters 3. Currently amended
The electronic device of claim 6, wherein the third and fourth materials each comprise p-type InN having a dopant concentration of between 5e19/centimeters 3 and 1e2 1/centimeters 3. Currently amended
The electronic device of claim 6, wherein the fifth and sixth materials each comprise the n-type InGaN having a dopant concentration of between 5e 19/centimeters 3 and 1e2 1/centimeters
The electronic device of claim 6, wherein the dielectric material has a permittivity o f greater than 3.9. Currently amended
15-22 Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
p-channel GaN transistor with InN tunnel junction contacts
p-channel GaN MOS-HEMT electronic device
Materials described outside the worked examples.
p-type GaN (substrate)
GaN
p-type InN
InN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an example horizontal transistor stack. [0007]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 0.7 eV | InN |
Optical Band Gap |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,811,501Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example horizontal transistor stack. [0007]
FIG. 2 illustrates an example energy band diagram for certain the semiconductor materials of
FIGS. 3A-3G illustrate a selective epitaxy process to generate the horizontal transistor stack of the example of
FIG. 4 to implement the examples disclosed herein. [0011] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the …
FIG. 5 is a block diagram of an example processor platform capable of executing the instructions of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus comprising: a substrate comprising Gallium Nitride (GaN); a first material over a first region of the substrate, the first material comprising p-type GaN; a second material adjacent to the first material and en over a second region of the substrate, the second material comprising p-type Indium Nitride (InN); and [[an]] a third material adjacent to the second material and over a third region of the substrate, the third material comprising n-type Indium Gallium Nitride (InGaN). Currently amended
The apparatus of claim 1, wherein the substrate comprises a first horizontal surface, a vertical surface ad j acent the first horizontal surface, and a second horizontal surface adjacent the vertical surface and vertically above the first horizontal surface, wherein the first, second, and third materials are over the first horizontal surface and the first material is adj acent the vertical surface of the substrate. Currently amended
The apparatus of claim 1, wherein the first material comprises p- type GaN having a dopant concentration between le1 6/centimeters 3 and le1 7/centimeters 3 Currently amended
The apparatus of claim 1, wherein the second material comprises p- type InN having a dopant concentration between 5e 1 9/centimeters 3 and le2 1/centimeters 3 Currently amended
The apparatus of claim 1, wherein the third material comprises n- type InGaN having a dopant concentration between 5e1 9/centimeters 3 and le2 1/centimeters 3 Currently amended
The apparatus of claim 1, wherein a portion of the first material extends over the second and third regions and under the second and third materials. New
The apparatus of claim 1, wherein the substrate comprises p-type GaN. New
An electronic device comprising: a substrate comprising Gallium Nitride (GaN), the substrate having a first horizontal surface, first and second vertical surfaces to first and second sides of the first horizontal surface, respectively,, and second and third horizontal surfaces adjacent to the first and second vertical surfaces, respectively; a dielectric material on the first horizontal surface; a gate on the dielectric material; first and second materials interfaced with the first and second vertical surfaces, respectively, and the second and third horizontal surfaces, respectively, the first and second materials each comprising p-type GaN; third and fourth materials interfaced with the first and second materials, respectively, the third and fourth materials each comprising p-type Indium Nitride (InN); fifth and sixth materials interfaced with the third and fourth materials, respectively, the fifth and sixth materials each comprising n-type Indium Gallium Nitride (InGaN); a source on the fifth material; and a drain on the sixth material. Currently amended
The electronic device of claim 6, wherein the substrate i s comprises p-type GaN. Currently amended
The electronic device of claim 6, wherein the first and second materials each comprise p-type GaN having a dopant concentration of between 1e 16/centimeters 3 and 1e 17/centimeters 3. Currently amended
The electronic device of claim 6, wherein the third and fourth materials each comprise p-type InN having a dopant concentration of between 5e19/centimeters 3 and 1e2 1/centimeters 3. Currently amended
The electronic device of claim 6, wherein the fifth and sixth materials each comprise the n-type InGaN having a dopant concentration of between 5e 19/centimeters 3 and 1e2 1/centimeters
The electronic device of claim 6, wherein the dielectric material has a permittivity o f greater than 3.9. Currently amended
15-22 Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
p-channel GaN transistor with InN tunnel junction contacts
p-channel GaN MOS-HEMT electronic device
Materials described outside the worked examples.
p-type GaN (substrate)
GaN
p-type InN
InN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an example horizontal transistor stack. [0007]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 0.7 eV | InN |
Optical Band Gap |
Related documents with shared materials, methods, properties, or citations.
n-type InGaN
InGaN
high-k dielectric
FIGS. 3A-3G illustrate a selective epitaxy process to generate the horizontal transistor stack of the example of
FIG. 4 to implement the examples disclosed herein. [0011] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the …
FIG. 4 to implement the examples disclosed herein. [0011] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the …
| 3.4 eV |
GaN |
— | 1.4–2.3 eV | — |
— | 0.5–1.07 eV | — |
Thickness | 10–100 nm | — |
Thickness | 1–5 nm | — |
Temperature | ≤ 400 °C | — |
Thickness | ≤ 10 nm | — |
n-type InGaN
InGaN
high-k dielectric
FIGS. 3A-3G illustrate a selective epitaxy process to generate the horizontal transistor stack of the example of
FIG. 4 to implement the examples disclosed herein. [0011] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the …
FIG. 4 to implement the examples disclosed herein. [0011] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the …
| 3.4 eV |
GaN |
— | 1.4–2.3 eV | — |
— | 0.5–1.07 eV | — |
Thickness | 10–100 nm | — |
Thickness | 1–5 nm | — |
Temperature | ≤ 400 °C | — |
Thickness | ≤ 10 nm | — |
n-type InGaN
InGaN
high-k dielectric
FIGS. 3A-3G illustrate a selective epitaxy process to generate the horizontal transistor stack of the example of
FIG. 4 to implement the examples disclosed herein. [0011] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the …
FIG. 4 to implement the examples disclosed herein. [0011] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the …
| 3.4 eV |
GaN |
— | 1.4–2.3 eV | — |
— | 0.5–1.07 eV | — |
Thickness | 10–100 nm | — |
Thickness | 1–5 nm | — |
Temperature | ≤ 400 °C | — |
Thickness | ≤ 10 nm | — |
n-type InGaN
InGaN
high-k dielectric
FIGS. 3A-3G illustrate a selective epitaxy process to generate the horizontal transistor stack of the example of
FIG. 4 to implement the examples disclosed herein. [0011] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the …
FIG. 4 to implement the examples disclosed herein. [0011] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the …
| 3.4 eV |
GaN |
— | 1.4–2.3 eV | — |
— | 0.5–1.07 eV | — |
Thickness | 10–100 nm | — |
Thickness | 1–5 nm | — |
Temperature | ≤ 400 °C | — |
Thickness | ≤ 10 nm | — |