Patent
US 9,330,918EDGE TERMINATION BY ION IMPLANTATION IN GALLIUM NITRIDE
Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano et al.
AVOGY, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,330,918Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The epitaxial layer doping may range from 10 14 to 10 17 cm⁻³, for example, and is typically n-type due to higher electron mobility for electrons in …
FIG. 2 is a cross sectional illustration of a GaN n+ substrate, including n- GaN epitaxial 15 layer, with a blanket Ohmic contact formed on the substrate. …
FIG. 3. The 7 location of the implant is typically defined using a mask defined by photolithography. The mask material is capable of blocking the implanted …
FIG. 4 is a schematic illustration of GaN device including an implanted isolation region 301 according to one or more embodiments described herein. The implant …
FIG. 5. The insulator material may be SiN X or SiO x, or a number of other acceptable insulating materials. The insulator thickness is chosen to determine the …
FIG. 6. By combining an ion-implanted edge termination layer 5 (301) and i nsulator layer (501), the c omer electrical field between Schottky metal contact …
FIG. 7 illustrates a Schottky 10 metal l ayer (701) that has been deposited over the epitaxial GaN layer. In case of using the Schottky metal for an implant …
FIG. 8, a P I N diode according to one or more embodiments is described. The PIN diode include an n + GaN substrate (800) with a typical doping level of 10 17 …
FIG. 9 is a cross-sectional view of an implant edge termination for vertical junction field effect transistor (FET) according to one or more embodiments of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of making an edge terminated semiconductor device, comprising: providing a GaN substrate having a GaN epitaxial layer grown thereon; exposing a portion of the GaN epitaxial layer to ion implantation to form an implanted region, wherein the energy dose is selected to provide a resistivity of the implanted region that is at least 90 % of maximum achievable resistivity; forming an insulating layer on the implanted region while leaving a portion of the implanted region exposed; and depositing a conductive layer over the exposed portion of the implanted region and a portion of the insulating layer.
The method of claim 1, wherein exposing the GaN epitaxy epitaxial layer to ion implantation comprises multiple implants at different energies and/or dosages selected to create a uniform layer of lattice damage.
The method of claim 1, wherein exposing the GaN epitaxy epitaxial layer to ion implantation comprises exposing the GaN epitaxial layer to one or more implants selected to provide an implant depth of greater than 450 nm.
The method of claim 1, wherein the implant ion is selected from the group consisting of nitrogen, argon, helium, or other elements, and mixtures thereof.
The method of claim 1, wherein the conductive layer comprises a Schottky metal. Page 2 of 4 App l. No. 14/558,393 PATENT Am dt. dated Response to Notice of Allowance of
The method of claim 1, wherein the conductive layer comprises p+ GaN.
The method of claim 1, wherein an overlap of conductive layer over the exposed portion of the implanted region is about 0.5 p m to about 10 pm.
The method of claim 1, wherein the resistivity is greater than 10 10 Ohms/sq.
The method of claim 1, wherein the GaN epitaxial layer is n-doped.
The method of claim 1, wherein the implanted region comprises a distribution of implanted ions.
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
edge terminated GaN semiconductor device
GaN vertical Schottky diode with field plate and ion implanted edge termination
Materials described outside the worked examples.
GaN substrate
GaN
insulating layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. The epitaxial layer doping may range from 10 14 to 10 17 cm⁻³, for example, and is typically n-type due to higher electron mobility for electrons in …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
resistivity of ion-implanted region (claimed minimum) | — | GaN |
resistivity of ion-implanted region (embodiment minimum) | ≥ 10000000000 Ohm/sq |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,330,918Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The epitaxial layer doping may range from 10 14 to 10 17 cm⁻³, for example, and is typically n-type due to higher electron mobility for electrons in …
FIG. 2 is a cross sectional illustration of a GaN n+ substrate, including n- GaN epitaxial 15 layer, with a blanket Ohmic contact formed on the substrate. …
FIG. 3. The 7 location of the implant is typically defined using a mask defined by photolithography. The mask material is capable of blocking the implanted …
FIG. 4 is a schematic illustration of GaN device including an implanted isolation region 301 according to one or more embodiments described herein. The implant …
FIG. 5. The insulator material may be SiN X or SiO x, or a number of other acceptable insulating materials. The insulator thickness is chosen to determine the …
FIG. 6. By combining an ion-implanted edge termination layer 5 (301) and i nsulator layer (501), the c omer electrical field between Schottky metal contact …
FIG. 7 illustrates a Schottky 10 metal l ayer (701) that has been deposited over the epitaxial GaN layer. In case of using the Schottky metal for an implant …
FIG. 8, a P I N diode according to one or more embodiments is described. The PIN diode include an n + GaN substrate (800) with a typical doping level of 10 17 …
FIG. 9 is a cross-sectional view of an implant edge termination for vertical junction field effect transistor (FET) according to one or more embodiments of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of making an edge terminated semiconductor device, comprising: providing a GaN substrate having a GaN epitaxial layer grown thereon; exposing a portion of the GaN epitaxial layer to ion implantation to form an implanted region, wherein the energy dose is selected to provide a resistivity of the implanted region that is at least 90 % of maximum achievable resistivity; forming an insulating layer on the implanted region while leaving a portion of the implanted region exposed; and depositing a conductive layer over the exposed portion of the implanted region and a portion of the insulating layer.
The method of claim 1, wherein exposing the GaN epitaxy epitaxial layer to ion implantation comprises multiple implants at different energies and/or dosages selected to create a uniform layer of lattice damage.
The method of claim 1, wherein exposing the GaN epitaxy epitaxial layer to ion implantation comprises exposing the GaN epitaxial layer to one or more implants selected to provide an implant depth of greater than 450 nm.
The method of claim 1, wherein the implant ion is selected from the group consisting of nitrogen, argon, helium, or other elements, and mixtures thereof.
The method of claim 1, wherein the conductive layer comprises a Schottky metal. Page 2 of 4 App l. No. 14/558,393 PATENT Am dt. dated Response to Notice of Allowance of
The method of claim 1, wherein the conductive layer comprises p+ GaN.
The method of claim 1, wherein an overlap of conductive layer over the exposed portion of the implanted region is about 0.5 p m to about 10 pm.
The method of claim 1, wherein the resistivity is greater than 10 10 Ohms/sq.
The method of claim 1, wherein the GaN epitaxial layer is n-doped.
The method of claim 1, wherein the implanted region comprises a distribution of implanted ions.
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
edge terminated GaN semiconductor device
GaN vertical Schottky diode with field plate and ion implanted edge termination
Materials described outside the worked examples.
GaN substrate
GaN
insulating layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. The epitaxial layer doping may range from 10 14 to 10 17 cm⁻³, for example, and is typically n-type due to higher electron mobility for electrons in …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
resistivity of ion-implanted region (claimed minimum) | — | GaN |
resistivity of ion-implanted region (embodiment minimum) | ≥ 10000000000 Ohm/sq |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,330,918Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The epitaxial layer doping may range from 10 14 to 10 17 cm⁻³, for example, and is typically n-type due to higher electron mobility for electrons in …
FIG. 2 is a cross sectional illustration of a GaN n+ substrate, including n- GaN epitaxial 15 layer, with a blanket Ohmic contact formed on the substrate. …
FIG. 3. The 7 location of the implant is typically defined using a mask defined by photolithography. The mask material is capable of blocking the implanted …
FIG. 4 is a schematic illustration of GaN device including an implanted isolation region 301 according to one or more embodiments described herein. The implant …
FIG. 5. The insulator material may be SiN X or SiO x, or a number of other acceptable insulating materials. The insulator thickness is chosen to determine the …
FIG. 6. By combining an ion-implanted edge termination layer 5 (301) and i nsulator layer (501), the c omer electrical field between Schottky metal contact …
FIG. 7 illustrates a Schottky 10 metal l ayer (701) that has been deposited over the epitaxial GaN layer. In case of using the Schottky metal for an implant …
FIG. 8, a P I N diode according to one or more embodiments is described. The PIN diode include an n + GaN substrate (800) with a typical doping level of 10 17 …
FIG. 9 is a cross-sectional view of an implant edge termination for vertical junction field effect transistor (FET) according to one or more embodiments of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of making an edge terminated semiconductor device, comprising: providing a GaN substrate having a GaN epitaxial layer grown thereon; exposing a portion of the GaN epitaxial layer to ion implantation to form an implanted region, wherein the energy dose is selected to provide a resistivity of the implanted region that is at least 90 % of maximum achievable resistivity; forming an insulating layer on the implanted region while leaving a portion of the implanted region exposed; and depositing a conductive layer over the exposed portion of the implanted region and a portion of the insulating layer.
The method of claim 1, wherein exposing the GaN epitaxy epitaxial layer to ion implantation comprises multiple implants at different energies and/or dosages selected to create a uniform layer of lattice damage.
The method of claim 1, wherein exposing the GaN epitaxy epitaxial layer to ion implantation comprises exposing the GaN epitaxial layer to one or more implants selected to provide an implant depth of greater than 450 nm.
The method of claim 1, wherein the implant ion is selected from the group consisting of nitrogen, argon, helium, or other elements, and mixtures thereof.
The method of claim 1, wherein the conductive layer comprises a Schottky metal. Page 2 of 4 App l. No. 14/558,393 PATENT Am dt. dated Response to Notice of Allowance of
The method of claim 1, wherein the conductive layer comprises p+ GaN.
The method of claim 1, wherein an overlap of conductive layer over the exposed portion of the implanted region is about 0.5 p m to about 10 pm.
The method of claim 1, wherein the resistivity is greater than 10 10 Ohms/sq.
The method of claim 1, wherein the GaN epitaxial layer is n-doped.
The method of claim 1, wherein the implanted region comprises a distribution of implanted ions.
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
edge terminated GaN semiconductor device
GaN vertical Schottky diode with field plate and ion implanted edge termination
Materials described outside the worked examples.
GaN substrate
GaN
insulating layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. The epitaxial layer doping may range from 10 14 to 10 17 cm⁻³, for example, and is typically n-type due to higher electron mobility for electrons in …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
resistivity of ion-implanted region (claimed minimum) | — | GaN |
resistivity of ion-implanted region (embodiment minimum) | ≥ 10000000000 Ohm/sq |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,330,918Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The epitaxial layer doping may range from 10 14 to 10 17 cm⁻³, for example, and is typically n-type due to higher electron mobility for electrons in …
FIG. 2 is a cross sectional illustration of a GaN n+ substrate, including n- GaN epitaxial 15 layer, with a blanket Ohmic contact formed on the substrate. …
FIG. 3. The 7 location of the implant is typically defined using a mask defined by photolithography. The mask material is capable of blocking the implanted …
FIG. 4 is a schematic illustration of GaN device including an implanted isolation region 301 according to one or more embodiments described herein. The implant …
FIG. 5. The insulator material may be SiN X or SiO x, or a number of other acceptable insulating materials. The insulator thickness is chosen to determine the …
FIG. 6. By combining an ion-implanted edge termination layer 5 (301) and i nsulator layer (501), the c omer electrical field between Schottky metal contact …
FIG. 7 illustrates a Schottky 10 metal l ayer (701) that has been deposited over the epitaxial GaN layer. In case of using the Schottky metal for an implant …
FIG. 8, a P I N diode according to one or more embodiments is described. The PIN diode include an n + GaN substrate (800) with a typical doping level of 10 17 …
FIG. 9 is a cross-sectional view of an implant edge termination for vertical junction field effect transistor (FET) according to one or more embodiments of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of making an edge terminated semiconductor device, comprising: providing a GaN substrate having a GaN epitaxial layer grown thereon; exposing a portion of the GaN epitaxial layer to ion implantation to form an implanted region, wherein the energy dose is selected to provide a resistivity of the implanted region that is at least 90 % of maximum achievable resistivity; forming an insulating layer on the implanted region while leaving a portion of the implanted region exposed; and depositing a conductive layer over the exposed portion of the implanted region and a portion of the insulating layer.
The method of claim 1, wherein exposing the GaN epitaxy epitaxial layer to ion implantation comprises multiple implants at different energies and/or dosages selected to create a uniform layer of lattice damage.
The method of claim 1, wherein exposing the GaN epitaxy epitaxial layer to ion implantation comprises exposing the GaN epitaxial layer to one or more implants selected to provide an implant depth of greater than 450 nm.
The method of claim 1, wherein the implant ion is selected from the group consisting of nitrogen, argon, helium, or other elements, and mixtures thereof.
The method of claim 1, wherein the conductive layer comprises a Schottky metal. Page 2 of 4 App l. No. 14/558,393 PATENT Am dt. dated Response to Notice of Allowance of
The method of claim 1, wherein the conductive layer comprises p+ GaN.
The method of claim 1, wherein an overlap of conductive layer over the exposed portion of the implanted region is about 0.5 p m to about 10 pm.
The method of claim 1, wherein the resistivity is greater than 10 10 Ohms/sq.
The method of claim 1, wherein the GaN epitaxial layer is n-doped.
The method of claim 1, wherein the implanted region comprises a distribution of implanted ions.
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
edge terminated GaN semiconductor device
GaN vertical Schottky diode with field plate and ion implanted edge termination
Materials described outside the worked examples.
GaN substrate
GaN
insulating layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. The epitaxial layer doping may range from 10 14 to 10 17 cm⁻³, for example, and is typically n-type due to higher electron mobility for electrons in …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
resistivity of ion-implanted region (claimed minimum) | — | GaN |
resistivity of ion-implanted region (embodiment minimum) | ≥ 10000000000 Ohm/sq |
Related documents with shared materials, methods, properties, or citations.
PIN diode with ion implanted edge termination
vertical junction field effect transistor with ion implanted edge termination
nitrogen implant ion
N
argon implant ion
Ar
helium implant ion
He
Schottky metal conductive layer
nickel Schottky metal
Ni
platinum Schottky metal
Pt
palladium Schottky metal
Pd
gold Schottky metal
Au
FIG. 4 is a schematic illustration of GaN device including an implanted isolation region 301 according to one or more embodiments described herein. The implant …
FIG. 5. The insulator material may be SiN X or SiO x, or a number of other acceptable insulating materials. The insulator thickness is chosen to determine the …
FIG. 6. By combining an ion-implanted edge termination layer 5 (301) and i nsulator layer (501), the c omer electrical field between Schottky metal contact …
FIG. 9 is a cross-sectional view of an implant edge termination for vertical junction field effect transistor (FET) according to one or more embodiments of the …
Thickness | 17–102 cm | — |
Thickness | 17–1020 cm | — |
Thickness | ≥ 450 nm | — |
Thickness | 10–12 cm | — |
Thickness | ≥ 400 nm | — |
PIN diode with ion implanted edge termination
vertical junction field effect transistor with ion implanted edge termination
nitrogen implant ion
N
argon implant ion
Ar
helium implant ion
He
Schottky metal conductive layer
nickel Schottky metal
Ni
platinum Schottky metal
Pt
palladium Schottky metal
Pd
gold Schottky metal
Au
FIG. 4 is a schematic illustration of GaN device including an implanted isolation region 301 according to one or more embodiments described herein. The implant …
FIG. 5. The insulator material may be SiN X or SiO x, or a number of other acceptable insulating materials. The insulator thickness is chosen to determine the …
FIG. 6. By combining an ion-implanted edge termination layer 5 (301) and i nsulator layer (501), the c omer electrical field between Schottky metal contact …
FIG. 9 is a cross-sectional view of an implant edge termination for vertical junction field effect transistor (FET) according to one or more embodiments of the …
Thickness | 17–102 cm | — |
Thickness | 17–1020 cm | — |
Thickness | ≥ 450 nm | — |
Thickness | 10–12 cm | — |
Thickness | ≥ 400 nm | — |
PIN diode with ion implanted edge termination
vertical junction field effect transistor with ion implanted edge termination
nitrogen implant ion
N
argon implant ion
Ar
helium implant ion
He
Schottky metal conductive layer
nickel Schottky metal
Ni
platinum Schottky metal
Pt
palladium Schottky metal
Pd
gold Schottky metal
Au
FIG. 4 is a schematic illustration of GaN device including an implanted isolation region 301 according to one or more embodiments described herein. The implant …
FIG. 5. The insulator material may be SiN X or SiO x, or a number of other acceptable insulating materials. The insulator thickness is chosen to determine the …
FIG. 6. By combining an ion-implanted edge termination layer 5 (301) and i nsulator layer (501), the c omer electrical field between Schottky metal contact …
FIG. 9 is a cross-sectional view of an implant edge termination for vertical junction field effect transistor (FET) according to one or more embodiments of the …
Thickness | 17–102 cm | — |
Thickness | 17–1020 cm | — |
Thickness | ≥ 450 nm | — |
Thickness | 10–12 cm | — |
Thickness | ≥ 400 nm | — |
PIN diode with ion implanted edge termination
vertical junction field effect transistor with ion implanted edge termination
nitrogen implant ion
N
argon implant ion
Ar
helium implant ion
He
Schottky metal conductive layer
nickel Schottky metal
Ni
platinum Schottky metal
Pt
palladium Schottky metal
Pd
gold Schottky metal
Au
FIG. 4 is a schematic illustration of GaN device including an implanted isolation region 301 according to one or more embodiments described herein. The implant …
FIG. 5. The insulator material may be SiN X or SiO x, or a number of other acceptable insulating materials. The insulator thickness is chosen to determine the …
FIG. 6. By combining an ion-implanted edge termination layer 5 (301) and i nsulator layer (501), the c omer electrical field between Schottky metal contact …
FIG. 9 is a cross-sectional view of an implant edge termination for vertical junction field effect transistor (FET) according to one or more embodiments of the …
Thickness | 17–102 cm | — |
Thickness | 17–1020 cm | — |
Thickness | ≥ 450 nm | — |
Thickness | 10–12 cm | — |
Thickness | ≥ 400 nm | — |