Patent
US 9,362,365GRAPHITE AND/OR GRAPHENE SEMICONDUCTOR DEVICES
Arthur Foster Hebard
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,362,365Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 A and 1 B are graphical representations of examples of a Schottky diode including a semimetal stack in accordance with various embodiments of the …
FIG. 2 illustrates an example of an energy diagram of a Schottky barrier in accordance with various embodiments of the present disclosure. [0007]
FIGS. 3-7 illustrate operational curves of various Schottky diodes of
FIG. 4 is a graph illustrating a Richardson activation energy In[ls (T)/T2] versus T' over the temperature range of about 250 K to about 330 K for an …
FIG. 5 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on various embodiments of a …
FIG. 6 is a graph of a 1/C₂-V curve 602 measured for an embodiment of a Schottky diode 100a including a doped semimetal stack 102 and a 1/C₂-V curve 604 …
FIG. 7 illustrates a J-V curve 702 measured for an embodiment of a Schottky diode 100 a that includes a doped semimetal stack 102 and a J-V curve 704 measured …
FIG. 8 is a graphical representation of an example of a Schottky diode including a zero gap semiconductor in accordance with various embodiments of the present …
FIG. 9 illustrates Raman shift spectra for a zero gap semiconductor of
FIGS. 10-12 illustrate operational curves of various Schottky diodes of
FIG. 11(a), the temperature-dependent data curves 1102 for a ZGS Schottky diode 1 00 b with a graphene/GaAs junction show that for both bias directions, a …
FIG. 12 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on a GaAs embodiment (curve …
FIGS. 13-14 are graphical representations of examples of a semimetal- semiconductor field effect transistor (SMESFET) and a zero gap semiconductor field effect …
FIG. 14 is a cross-sectional view of an embodiment of a zero gap semiconductor-semiconductor field effect transistor (ZGSFET) 1300b including a ZGS layer 102d …
FIGS. 15-16 are graphical representations of examples of a high electron mobility transistor (HEMT) in accordance with various embodiments of the present …
FIG. 16 is similar to the embodiment of a ZGSFET 1300b illustrated in
FIGS. 17-20 are flowcharts illustrating the fabrication of the semiconductor devices of
FIG. 18 is a flow chart illustrating an embodiment of a method 1800 of fabricating a SMESFET/ZGSFET 1300 (
FIG. 19 is a flow chart illustrating an embodiment of a method 1900 of fabricating a HEMT 1500 (
FIG. 20, shown is another example of a flow chart illustrating an embodiment of a method 2000 of fabricating a ZGS Schottky diode 1 00b (
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semimetal semiconductor field effect transistor (SMESFET) comprising: a semiconductor layer including a semiconducting material; a semimetal stack including a graphene layer, wherein the semimetal stack is formed on the semiconductor layer, and the semiconductor layer and the semimetal stack form a Schottky barrier; and two electrodes and a counter electrode disposed on a side of the semimetal stack opposite the semiconductor layer and not in contact with the semiconductor layer.
The SMESFET of claim 1, wherein the semimetal stack is doped. The SMESFET of claim 2, wherein the semimetal stack includes intercalated impurity atoms. 4 The SMESFET of claim 2, wherein the semimetal stack includes intercalated bromine atoms.
The SMESFET of claim 1, wherein the semimetal stack only includes a single graphene layer.
The SMESFET of claim 1, wherein the semimetal stack further includes a graphite layer. 2 Serial No.: 14/524,465 Docket No.: 222106-1406
The SMESFET of claim 1, wherein the semiconductor layer includes at least one of the following semiconducting materials: Si, SiC, GaAs, and GaN.
The SMESFET of claim 1, wherein the counter electrode is disposed on the semimetal stack between the two electrodes.
The SMESFET of claim 1, wherein the two electrodes and the counter electrode are disposed on a graphite layer of the semimetal stack.
The SMESFET of claim 1, further comprising an ohmic contact layer disposed on the semiconductor layer, the ohmic contact layer in contact with the semiconductor layer and not in contact with the semimetal stack.
A zero gap semiconductor semiconductor field effect transistor (ZGSFET) comprising: a semiconductor layer including a semiconducting material; a zero gap semiconductor layer including a sheet of graphene, wherein the zero gap semiconductor layer is formed on the semiconductor layer, and the semiconductor layer and the zero gap semiconductor layer form a Schottky barrier; and two electrodes and a counter electrode disposed on a side of the zero gap semiconductor layer opposite the semiconductor layer and not in contact with the semiconductor layer. 3 Serial No.: 14/524,465 Docket No.: 222106-1406
The ZGSFET of claim 13, wherein the zero gap semiconductor layer is doped.
The ZGSFET of claim 13, wherein the zero gap semiconductor layer is doped with an atomically thin dopant.
The ZGSFET of claim 13, wherein the semiconductor following semiconducting materials: Si, SiC, GaAs,
The ZGSFET of claim 13, further comprising semiconductor layer, the ohmic contact layer in contact with the zero gap semiconductor layer.
A zero gap semiconductor semiconductor field effect transistor (ZGSFET), comprising: a semiconductor layer including a semiconducting material; and a zero gap semiconductor layer including a sheet of graphene, wherein the zero gap semiconductor layer is formed on the semiconductor layer, and the semiconductor layer and the zero gap semiconductor layer form a Schottky barrier, wherein the zero gap semiconductor layer is doped with an atomically thin dopant that includes Bis(trifloromethanesulfonyl)am ine.
. canceled
The ZGSFET of claim [[18]] 13, wherein the graphene between the two electrodes.
Layer stacks claimed or described, ordered top of device to substrate.
semimetal semiconductor field effect transistor (SMESFET)
zero gap semiconductor field effect transistor (ZGSFET)
Materials described outside the worked examples.
graphite
graphene
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 is a graph illustrating a Richardson activation energy In[ls (T)/T2] versus T' over the temperature range of about 250 K to about 330 K for an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Maximum operating temperature for Schottky diode with Si semiconductor layer | 400–500 K | Si |
Maximum operating temperature for Schottky diode with GaAs semiconductor layer | 500–600 K |
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DOPED, PASSIVATED GRAPHENE NANOMESH, METHOD OF MAKING THE DOPED, PASSIVATED GRAPHENE NANOMESH, AND SEMICONDUCTOR DEVICE INCLUDING THE DOPED, PASSIVATED GRAPHENE NANOMESH
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US 9,362,365Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 A and 1 B are graphical representations of examples of a Schottky diode including a semimetal stack in accordance with various embodiments of the …
FIG. 2 illustrates an example of an energy diagram of a Schottky barrier in accordance with various embodiments of the present disclosure. [0007]
FIGS. 3-7 illustrate operational curves of various Schottky diodes of
FIG. 4 is a graph illustrating a Richardson activation energy In[ls (T)/T2] versus T' over the temperature range of about 250 K to about 330 K for an …
FIG. 5 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on various embodiments of a …
FIG. 6 is a graph of a 1/C₂-V curve 602 measured for an embodiment of a Schottky diode 100a including a doped semimetal stack 102 and a 1/C₂-V curve 604 …
FIG. 7 illustrates a J-V curve 702 measured for an embodiment of a Schottky diode 100 a that includes a doped semimetal stack 102 and a J-V curve 704 measured …
FIG. 8 is a graphical representation of an example of a Schottky diode including a zero gap semiconductor in accordance with various embodiments of the present …
FIG. 9 illustrates Raman shift spectra for a zero gap semiconductor of
FIGS. 10-12 illustrate operational curves of various Schottky diodes of
FIG. 11(a), the temperature-dependent data curves 1102 for a ZGS Schottky diode 1 00 b with a graphene/GaAs junction show that for both bias directions, a …
FIG. 12 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on a GaAs embodiment (curve …
FIGS. 13-14 are graphical representations of examples of a semimetal- semiconductor field effect transistor (SMESFET) and a zero gap semiconductor field effect …
FIG. 14 is a cross-sectional view of an embodiment of a zero gap semiconductor-semiconductor field effect transistor (ZGSFET) 1300b including a ZGS layer 102d …
FIGS. 15-16 are graphical representations of examples of a high electron mobility transistor (HEMT) in accordance with various embodiments of the present …
FIG. 16 is similar to the embodiment of a ZGSFET 1300b illustrated in
FIGS. 17-20 are flowcharts illustrating the fabrication of the semiconductor devices of
FIG. 18 is a flow chart illustrating an embodiment of a method 1800 of fabricating a SMESFET/ZGSFET 1300 (
FIG. 19 is a flow chart illustrating an embodiment of a method 1900 of fabricating a HEMT 1500 (
FIG. 20, shown is another example of a flow chart illustrating an embodiment of a method 2000 of fabricating a ZGS Schottky diode 1 00b (
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semimetal semiconductor field effect transistor (SMESFET) comprising: a semiconductor layer including a semiconducting material; a semimetal stack including a graphene layer, wherein the semimetal stack is formed on the semiconductor layer, and the semiconductor layer and the semimetal stack form a Schottky barrier; and two electrodes and a counter electrode disposed on a side of the semimetal stack opposite the semiconductor layer and not in contact with the semiconductor layer.
The SMESFET of claim 1, wherein the semimetal stack is doped. The SMESFET of claim 2, wherein the semimetal stack includes intercalated impurity atoms. 4 The SMESFET of claim 2, wherein the semimetal stack includes intercalated bromine atoms.
The SMESFET of claim 1, wherein the semimetal stack only includes a single graphene layer.
The SMESFET of claim 1, wherein the semimetal stack further includes a graphite layer. 2 Serial No.: 14/524,465 Docket No.: 222106-1406
The SMESFET of claim 1, wherein the semiconductor layer includes at least one of the following semiconducting materials: Si, SiC, GaAs, and GaN.
The SMESFET of claim 1, wherein the counter electrode is disposed on the semimetal stack between the two electrodes.
The SMESFET of claim 1, wherein the two electrodes and the counter electrode are disposed on a graphite layer of the semimetal stack.
The SMESFET of claim 1, further comprising an ohmic contact layer disposed on the semiconductor layer, the ohmic contact layer in contact with the semiconductor layer and not in contact with the semimetal stack.
A zero gap semiconductor semiconductor field effect transistor (ZGSFET) comprising: a semiconductor layer including a semiconducting material; a zero gap semiconductor layer including a sheet of graphene, wherein the zero gap semiconductor layer is formed on the semiconductor layer, and the semiconductor layer and the zero gap semiconductor layer form a Schottky barrier; and two electrodes and a counter electrode disposed on a side of the zero gap semiconductor layer opposite the semiconductor layer and not in contact with the semiconductor layer. 3 Serial No.: 14/524,465 Docket No.: 222106-1406
The ZGSFET of claim 13, wherein the zero gap semiconductor layer is doped.
The ZGSFET of claim 13, wherein the zero gap semiconductor layer is doped with an atomically thin dopant.
The ZGSFET of claim 13, wherein the semiconductor following semiconducting materials: Si, SiC, GaAs,
The ZGSFET of claim 13, further comprising semiconductor layer, the ohmic contact layer in contact with the zero gap semiconductor layer.
A zero gap semiconductor semiconductor field effect transistor (ZGSFET), comprising: a semiconductor layer including a semiconducting material; and a zero gap semiconductor layer including a sheet of graphene, wherein the zero gap semiconductor layer is formed on the semiconductor layer, and the semiconductor layer and the zero gap semiconductor layer form a Schottky barrier, wherein the zero gap semiconductor layer is doped with an atomically thin dopant that includes Bis(trifloromethanesulfonyl)am ine.
. canceled
The ZGSFET of claim [[18]] 13, wherein the graphene between the two electrodes.
Layer stacks claimed or described, ordered top of device to substrate.
semimetal semiconductor field effect transistor (SMESFET)
zero gap semiconductor field effect transistor (ZGSFET)
Materials described outside the worked examples.
graphite
graphene
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 is a graph illustrating a Richardson activation energy In[ls (T)/T2] versus T' over the temperature range of about 250 K to about 330 K for an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Maximum operating temperature for Schottky diode with Si semiconductor layer | 400–500 K | Si |
Maximum operating temperature for Schottky diode with GaAs semiconductor layer | 500–600 K |
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DOPED, PASSIVATED GRAPHENE NANOMESH, METHOD OF MAKING THE DOPED, PASSIVATED GRAPHENE NANOMESH, AND SEMICONDUCTOR DEVICE INCLUDING THE DOPED, PASSIVATED GRAPHENE NANOMESH
FLEXIBLE GRAPHENE SWITCHING DEVICE
Patent
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US 9,362,365Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 A and 1 B are graphical representations of examples of a Schottky diode including a semimetal stack in accordance with various embodiments of the …
FIG. 2 illustrates an example of an energy diagram of a Schottky barrier in accordance with various embodiments of the present disclosure. [0007]
FIGS. 3-7 illustrate operational curves of various Schottky diodes of
FIG. 4 is a graph illustrating a Richardson activation energy In[ls (T)/T2] versus T' over the temperature range of about 250 K to about 330 K for an …
FIG. 5 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on various embodiments of a …
FIG. 6 is a graph of a 1/C₂-V curve 602 measured for an embodiment of a Schottky diode 100a including a doped semimetal stack 102 and a 1/C₂-V curve 604 …
FIG. 7 illustrates a J-V curve 702 measured for an embodiment of a Schottky diode 100 a that includes a doped semimetal stack 102 and a J-V curve 704 measured …
FIG. 8 is a graphical representation of an example of a Schottky diode including a zero gap semiconductor in accordance with various embodiments of the present …
FIG. 9 illustrates Raman shift spectra for a zero gap semiconductor of
FIGS. 10-12 illustrate operational curves of various Schottky diodes of
FIG. 11(a), the temperature-dependent data curves 1102 for a ZGS Schottky diode 1 00 b with a graphene/GaAs junction show that for both bias directions, a …
FIG. 12 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on a GaAs embodiment (curve …
FIGS. 13-14 are graphical representations of examples of a semimetal- semiconductor field effect transistor (SMESFET) and a zero gap semiconductor field effect …
FIG. 14 is a cross-sectional view of an embodiment of a zero gap semiconductor-semiconductor field effect transistor (ZGSFET) 1300b including a ZGS layer 102d …
FIGS. 15-16 are graphical representations of examples of a high electron mobility transistor (HEMT) in accordance with various embodiments of the present …
FIG. 16 is similar to the embodiment of a ZGSFET 1300b illustrated in
FIGS. 17-20 are flowcharts illustrating the fabrication of the semiconductor devices of
FIG. 18 is a flow chart illustrating an embodiment of a method 1800 of fabricating a SMESFET/ZGSFET 1300 (
FIG. 19 is a flow chart illustrating an embodiment of a method 1900 of fabricating a HEMT 1500 (
FIG. 20, shown is another example of a flow chart illustrating an embodiment of a method 2000 of fabricating a ZGS Schottky diode 1 00b (
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semimetal semiconductor field effect transistor (SMESFET) comprising: a semiconductor layer including a semiconducting material; a semimetal stack including a graphene layer, wherein the semimetal stack is formed on the semiconductor layer, and the semiconductor layer and the semimetal stack form a Schottky barrier; and two electrodes and a counter electrode disposed on a side of the semimetal stack opposite the semiconductor layer and not in contact with the semiconductor layer.
The SMESFET of claim 1, wherein the semimetal stack is doped. The SMESFET of claim 2, wherein the semimetal stack includes intercalated impurity atoms. 4 The SMESFET of claim 2, wherein the semimetal stack includes intercalated bromine atoms.
The SMESFET of claim 1, wherein the semimetal stack only includes a single graphene layer.
The SMESFET of claim 1, wherein the semimetal stack further includes a graphite layer. 2 Serial No.: 14/524,465 Docket No.: 222106-1406
The SMESFET of claim 1, wherein the semiconductor layer includes at least one of the following semiconducting materials: Si, SiC, GaAs, and GaN.
The SMESFET of claim 1, wherein the counter electrode is disposed on the semimetal stack between the two electrodes.
The SMESFET of claim 1, wherein the two electrodes and the counter electrode are disposed on a graphite layer of the semimetal stack.
The SMESFET of claim 1, further comprising an ohmic contact layer disposed on the semiconductor layer, the ohmic contact layer in contact with the semiconductor layer and not in contact with the semimetal stack.
A zero gap semiconductor semiconductor field effect transistor (ZGSFET) comprising: a semiconductor layer including a semiconducting material; a zero gap semiconductor layer including a sheet of graphene, wherein the zero gap semiconductor layer is formed on the semiconductor layer, and the semiconductor layer and the zero gap semiconductor layer form a Schottky barrier; and two electrodes and a counter electrode disposed on a side of the zero gap semiconductor layer opposite the semiconductor layer and not in contact with the semiconductor layer. 3 Serial No.: 14/524,465 Docket No.: 222106-1406
The ZGSFET of claim 13, wherein the zero gap semiconductor layer is doped.
The ZGSFET of claim 13, wherein the zero gap semiconductor layer is doped with an atomically thin dopant.
The ZGSFET of claim 13, wherein the semiconductor following semiconducting materials: Si, SiC, GaAs,
The ZGSFET of claim 13, further comprising semiconductor layer, the ohmic contact layer in contact with the zero gap semiconductor layer.
A zero gap semiconductor semiconductor field effect transistor (ZGSFET), comprising: a semiconductor layer including a semiconducting material; and a zero gap semiconductor layer including a sheet of graphene, wherein the zero gap semiconductor layer is formed on the semiconductor layer, and the semiconductor layer and the zero gap semiconductor layer form a Schottky barrier, wherein the zero gap semiconductor layer is doped with an atomically thin dopant that includes Bis(trifloromethanesulfonyl)am ine.
. canceled
The ZGSFET of claim [[18]] 13, wherein the graphene between the two electrodes.
Layer stacks claimed or described, ordered top of device to substrate.
semimetal semiconductor field effect transistor (SMESFET)
zero gap semiconductor field effect transistor (ZGSFET)
Materials described outside the worked examples.
graphite
graphene
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 is a graph illustrating a Richardson activation energy In[ls (T)/T2] versus T' over the temperature range of about 250 K to about 330 K for an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Maximum operating temperature for Schottky diode with Si semiconductor layer | 400–500 K | Si |
Maximum operating temperature for Schottky diode with GaAs semiconductor layer | 500–600 K |
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DOPED, PASSIVATED GRAPHENE NANOMESH, METHOD OF MAKING THE DOPED, PASSIVATED GRAPHENE NANOMESH, AND SEMICONDUCTOR DEVICE INCLUDING THE DOPED, PASSIVATED GRAPHENE NANOMESH
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Patent
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US 9,362,365Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 A and 1 B are graphical representations of examples of a Schottky diode including a semimetal stack in accordance with various embodiments of the …
FIG. 2 illustrates an example of an energy diagram of a Schottky barrier in accordance with various embodiments of the present disclosure. [0007]
FIGS. 3-7 illustrate operational curves of various Schottky diodes of
FIG. 4 is a graph illustrating a Richardson activation energy In[ls (T)/T2] versus T' over the temperature range of about 250 K to about 330 K for an …
FIG. 5 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on various embodiments of a …
FIG. 6 is a graph of a 1/C₂-V curve 602 measured for an embodiment of a Schottky diode 100a including a doped semimetal stack 102 and a 1/C₂-V curve 604 …
FIG. 7 illustrates a J-V curve 702 measured for an embodiment of a Schottky diode 100 a that includes a doped semimetal stack 102 and a J-V curve 704 measured …
FIG. 8 is a graphical representation of an example of a Schottky diode including a zero gap semiconductor in accordance with various embodiments of the present …
FIG. 9 illustrates Raman shift spectra for a zero gap semiconductor of
FIGS. 10-12 illustrate operational curves of various Schottky diodes of
FIG. 11(a), the temperature-dependent data curves 1102 for a ZGS Schottky diode 1 00 b with a graphene/GaAs junction show that for both bias directions, a …
FIG. 12 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on a GaAs embodiment (curve …
FIGS. 13-14 are graphical representations of examples of a semimetal- semiconductor field effect transistor (SMESFET) and a zero gap semiconductor field effect …
FIG. 14 is a cross-sectional view of an embodiment of a zero gap semiconductor-semiconductor field effect transistor (ZGSFET) 1300b including a ZGS layer 102d …
FIGS. 15-16 are graphical representations of examples of a high electron mobility transistor (HEMT) in accordance with various embodiments of the present …
FIG. 16 is similar to the embodiment of a ZGSFET 1300b illustrated in
FIGS. 17-20 are flowcharts illustrating the fabrication of the semiconductor devices of
FIG. 18 is a flow chart illustrating an embodiment of a method 1800 of fabricating a SMESFET/ZGSFET 1300 (
FIG. 19 is a flow chart illustrating an embodiment of a method 1900 of fabricating a HEMT 1500 (
FIG. 20, shown is another example of a flow chart illustrating an embodiment of a method 2000 of fabricating a ZGS Schottky diode 1 00b (
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semimetal semiconductor field effect transistor (SMESFET) comprising: a semiconductor layer including a semiconducting material; a semimetal stack including a graphene layer, wherein the semimetal stack is formed on the semiconductor layer, and the semiconductor layer and the semimetal stack form a Schottky barrier; and two electrodes and a counter electrode disposed on a side of the semimetal stack opposite the semiconductor layer and not in contact with the semiconductor layer.
The SMESFET of claim 1, wherein the semimetal stack is doped. The SMESFET of claim 2, wherein the semimetal stack includes intercalated impurity atoms. 4 The SMESFET of claim 2, wherein the semimetal stack includes intercalated bromine atoms.
The SMESFET of claim 1, wherein the semimetal stack only includes a single graphene layer.
The SMESFET of claim 1, wherein the semimetal stack further includes a graphite layer. 2 Serial No.: 14/524,465 Docket No.: 222106-1406
The SMESFET of claim 1, wherein the semiconductor layer includes at least one of the following semiconducting materials: Si, SiC, GaAs, and GaN.
The SMESFET of claim 1, wherein the counter electrode is disposed on the semimetal stack between the two electrodes.
The SMESFET of claim 1, wherein the two electrodes and the counter electrode are disposed on a graphite layer of the semimetal stack.
The SMESFET of claim 1, further comprising an ohmic contact layer disposed on the semiconductor layer, the ohmic contact layer in contact with the semiconductor layer and not in contact with the semimetal stack.
A zero gap semiconductor semiconductor field effect transistor (ZGSFET) comprising: a semiconductor layer including a semiconducting material; a zero gap semiconductor layer including a sheet of graphene, wherein the zero gap semiconductor layer is formed on the semiconductor layer, and the semiconductor layer and the zero gap semiconductor layer form a Schottky barrier; and two electrodes and a counter electrode disposed on a side of the zero gap semiconductor layer opposite the semiconductor layer and not in contact with the semiconductor layer. 3 Serial No.: 14/524,465 Docket No.: 222106-1406
The ZGSFET of claim 13, wherein the zero gap semiconductor layer is doped.
The ZGSFET of claim 13, wherein the zero gap semiconductor layer is doped with an atomically thin dopant.
The ZGSFET of claim 13, wherein the semiconductor following semiconducting materials: Si, SiC, GaAs,
The ZGSFET of claim 13, further comprising semiconductor layer, the ohmic contact layer in contact with the zero gap semiconductor layer.
A zero gap semiconductor semiconductor field effect transistor (ZGSFET), comprising: a semiconductor layer including a semiconducting material; and a zero gap semiconductor layer including a sheet of graphene, wherein the zero gap semiconductor layer is formed on the semiconductor layer, and the semiconductor layer and the zero gap semiconductor layer form a Schottky barrier, wherein the zero gap semiconductor layer is doped with an atomically thin dopant that includes Bis(trifloromethanesulfonyl)am ine.
. canceled
The ZGSFET of claim [[18]] 13, wherein the graphene between the two electrodes.
Layer stacks claimed or described, ordered top of device to substrate.
semimetal semiconductor field effect transistor (SMESFET)
zero gap semiconductor field effect transistor (ZGSFET)
Materials described outside the worked examples.
graphite
graphene
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 is a graph illustrating a Richardson activation energy In[ls (T)/T2] versus T' over the temperature range of about 250 K to about 330 K for an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Maximum operating temperature for Schottky diode with Si semiconductor layer | 400–500 K | Si |
Maximum operating temperature for Schottky diode with GaAs semiconductor layer | 500–600 K |
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DOPED, PASSIVATED GRAPHENE NANOMESH, METHOD OF MAKING THE DOPED, PASSIVATED GRAPHENE NANOMESH, AND SEMICONDUCTOR DEVICE INCLUDING THE DOPED, PASSIVATED GRAPHENE NANOMESH
FLEXIBLE GRAPHENE SWITCHING DEVICE
Schottky diode (HOPG on GaAs)
Schottky diode (HOPG on 4H-SiC)
few-layer graphene
Si
SiC
GaAs
GaN
Bis(trifluoromethanesulfonyl)amine
highly oriented pyrolytic graphite (HOPG)
Gold(III) Chloride
AuCl₃
bromine
Br
4H-SiC
FIG. 5 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on various embodiments of a …
FIG. 6 is a graph of a 1/C₂-V curve 602 measured for an embodiment of a Schottky diode 100a including a doped semimetal stack 102 and a 1/C₂-V curve 604 …
FIG. 9 illustrates Raman shift spectra for a zero gap semiconductor of
FIG. 12 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on a GaAs embodiment (curve …
FIGS. 13-14 are graphical representations of examples of a semimetal- semiconductor field effect transistor (SMESFET) and a zero gap semiconductor field effect …
FIG. 14 is a cross-sectional view of an embodiment of a zero gap semiconductor-semiconductor field effect transistor (ZGSFET) 1300b including a ZGS layer 102d …
FIGS. 15-16 are graphical representations of examples of a high electron mobility transistor (HEMT) in accordance with various embodiments of the present …
Maximum operating temperature for Schottky diode with SiC semiconductor layer | 900–1100 K | SiC |
Maximum operating temperature for Schottky diode with GaN semiconductor layer | 600–1200 K | GaN |
Temperature | 250–330 K | — |
— | 0.4–0.6 eV | — |
— | 0.6–0.9 eV | — |
Duration | 600–36000 s | — |
Thickness | 1400–2000 cm | — |
— | 0.54–0.74 eV | — |
— | 0.74–1.04 eV | — |
— | 0.3–0.4 eV | — |
Pressure | 1e-7 torr | — |
Voltage | ≤ 1 V | — |
Schottky diode (HOPG on GaAs)
Schottky diode (HOPG on 4H-SiC)
few-layer graphene
Si
SiC
GaAs
GaN
Bis(trifluoromethanesulfonyl)amine
highly oriented pyrolytic graphite (HOPG)
Gold(III) Chloride
AuCl₃
bromine
Br
4H-SiC
FIG. 5 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on various embodiments of a …
FIG. 6 is a graph of a 1/C₂-V curve 602 measured for an embodiment of a Schottky diode 100a including a doped semimetal stack 102 and a 1/C₂-V curve 604 …
FIG. 9 illustrates Raman shift spectra for a zero gap semiconductor of
FIG. 12 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on a GaAs embodiment (curve …
FIGS. 13-14 are graphical representations of examples of a semimetal- semiconductor field effect transistor (SMESFET) and a zero gap semiconductor field effect …
FIG. 14 is a cross-sectional view of an embodiment of a zero gap semiconductor-semiconductor field effect transistor (ZGSFET) 1300b including a ZGS layer 102d …
FIGS. 15-16 are graphical representations of examples of a high electron mobility transistor (HEMT) in accordance with various embodiments of the present …
Maximum operating temperature for Schottky diode with SiC semiconductor layer | 900–1100 K | SiC |
Maximum operating temperature for Schottky diode with GaN semiconductor layer | 600–1200 K | GaN |
Temperature | 250–330 K | — |
— | 0.4–0.6 eV | — |
— | 0.6–0.9 eV | — |
Duration | 600–36000 s | — |
Thickness | 1400–2000 cm | — |
— | 0.54–0.74 eV | — |
— | 0.74–1.04 eV | — |
— | 0.3–0.4 eV | — |
Pressure | 1e-7 torr | — |
Voltage | ≤ 1 V | — |
Schottky diode (HOPG on GaAs)
Schottky diode (HOPG on 4H-SiC)
few-layer graphene
Si
SiC
GaAs
GaN
Bis(trifluoromethanesulfonyl)amine
highly oriented pyrolytic graphite (HOPG)
Gold(III) Chloride
AuCl₃
bromine
Br
4H-SiC
FIG. 5 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on various embodiments of a …
FIG. 6 is a graph of a 1/C₂-V curve 602 measured for an embodiment of a Schottky diode 100a including a doped semimetal stack 102 and a 1/C₂-V curve 604 …
FIG. 9 illustrates Raman shift spectra for a zero gap semiconductor of
FIG. 12 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on a GaAs embodiment (curve …
FIGS. 13-14 are graphical representations of examples of a semimetal- semiconductor field effect transistor (SMESFET) and a zero gap semiconductor field effect …
FIG. 14 is a cross-sectional view of an embodiment of a zero gap semiconductor-semiconductor field effect transistor (ZGSFET) 1300b including a ZGS layer 102d …
FIGS. 15-16 are graphical representations of examples of a high electron mobility transistor (HEMT) in accordance with various embodiments of the present …
Maximum operating temperature for Schottky diode with SiC semiconductor layer | 900–1100 K | SiC |
Maximum operating temperature for Schottky diode with GaN semiconductor layer | 600–1200 K | GaN |
Temperature | 250–330 K | — |
— | 0.4–0.6 eV | — |
— | 0.6–0.9 eV | — |
Duration | 600–36000 s | — |
Thickness | 1400–2000 cm | — |
— | 0.54–0.74 eV | — |
— | 0.74–1.04 eV | — |
— | 0.3–0.4 eV | — |
Pressure | 1e-7 torr | — |
Voltage | ≤ 1 V | — |
Schottky diode (HOPG on GaAs)
Schottky diode (HOPG on 4H-SiC)
few-layer graphene
Si
SiC
GaAs
GaN
Bis(trifluoromethanesulfonyl)amine
highly oriented pyrolytic graphite (HOPG)
Gold(III) Chloride
AuCl₃
bromine
Br
4H-SiC
FIG. 5 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on various embodiments of a …
FIG. 6 is a graph of a 1/C₂-V curve 602 measured for an embodiment of a Schottky diode 100a including a doped semimetal stack 102 and a 1/C₂-V curve 604 …
FIG. 9 illustrates Raman shift spectra for a zero gap semiconductor of
FIG. 12 is a graph of an inverse square of capacitance per unit area versus an a pplied reverse bias voltage (1/C 2-V) as measured on a GaAs embodiment (curve …
FIGS. 13-14 are graphical representations of examples of a semimetal- semiconductor field effect transistor (SMESFET) and a zero gap semiconductor field effect …
FIG. 14 is a cross-sectional view of an embodiment of a zero gap semiconductor-semiconductor field effect transistor (ZGSFET) 1300b including a ZGS layer 102d …
FIGS. 15-16 are graphical representations of examples of a high electron mobility transistor (HEMT) in accordance with various embodiments of the present …
Maximum operating temperature for Schottky diode with SiC semiconductor layer | 900–1100 K | SiC |
Maximum operating temperature for Schottky diode with GaN semiconductor layer | 600–1200 K | GaN |
Temperature | 250–330 K | — |
— | 0.4–0.6 eV | — |
— | 0.6–0.9 eV | — |
Duration | 600–36000 s | — |
Thickness | 1400–2000 cm | — |
— | 0.54–0.74 eV | — |
— | 0.74–1.04 eV | — |
— | 0.3–0.4 eV | — |
Pressure | 1e-7 torr | — |
Voltage | ≤ 1 V | — |