Patent
US 9,978,858GALLIUM NITRIDE MATERIAL DEVICES AND ASSOCIATED METHODS
Jerry Wayne Johnson
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,978,858Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a cross-section of a gallium nitride material transistor building block structure according to one embodiment of the invention. 10
FIG. 2 is a cross-section of a gallium nitride material transistor including a source field plate as described in Example 1.
FIG. 3 shows a gallium nitride material transistor die as described in Example 1
FIG. 4 is an I -V curve for a gallium nitride material transistor as described in 20 Example 1.
FIG. 5 is a simulation of electric fields in the gate drain region for a gallium nitride material transistor without a source field plate under conditions V g s …
FIG. 6 is a simulation of electric fields in the gate drain region for a gallium 25 nitride material transistor without a source field plate under conditions V …
FIG. 7 is a graph of simulated values of the peak electric fields for a gallium nitride material transistor with and without the source field plate under …
FIG. 8 is a graph of pulsed I -V measurements for a gallium nitride material transistor with and without the source field plate in which the transistors were …
FIG. 9 is a graph that compares C gd and MSG versus drain bias at 2.14 GHz for a gallium nitride material transistor with and without a source field plate as …
FIG. 10 shows the f T performance versus gate bias for a 2 mm device with a source field plate operating at a drain bias of 28 V. At an I DQ of 27.5 mA/mm, the …
FIG. 11 demonstrates the disparity in the 10 performance of P s at and SVG 15433473.02-15-2017.IZ₇EVSCERXEAPX4.SPEC.25.10.895.1172.984.1204.svg 0.107 0.297 …
FIG. 12 shows a pulsed RF power sweep at a bias condition of V d = 60 V and I dq 10 = 1 A for a 36 mm gallium nitride material transistor with a source field …
FIG. 13. The device 15 demonstrated 65.5 W (1.8W/mm) of Ps at, a 'rmax of 65 % and 16 dB of small signal gain. The linear performance of the transistor is …
FIG. 14 shows the backed-off performance of the 20 device. At a back-off of 8 dB the device delivers ~2 0.5 W with ~ 35 % of drain efficiency and-17.5 dB of gain …
FIG. 15 is a graph of I ds versus time which shows the drain current drift of devices operated at 45 V and a junction temperature of 200 * C with the median 20 …
FIG. 16. However, it should be understood that the source field plate is not connected to a conductive region at the backside of the device in all embodiments …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-23. Canceled
Canceled
A method, comprising: forming a gallium nitride material region over a su bstrate-forming a source electrode, at least in part, over the gallium nitride material region; forming a gate electrode, at least in part, over the gallium nitride material region; forming a drain electrode, at least in part, over the gallium nitride material region; formnina passivationtlayerover the g all imnitr ide materiat SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.1.10.1669.1252.1792.1300.svg 0.16 0.41 Chemistry Black and white tb etwee nthe source electrode and the g ate electrode. and between the g ate electrode and the drain electrode, the g ate electrode extendin g over a portion of the passivation la y er a distance directly on the p assivation la y er in a direction of the drain electrode gaterthantadistancg ina directionof the source electrode. forming a source field plate comprising a conductive material that is electrically connected to the source electrode, formin g a via which extends throu g h the g allium nitride material and the substrate to a b ack side of the sutrate; formin g a conductive material in the via and which electrically connects the source field plate to a conductive re z ion at the backside of the substrate: and formin g a barrier la y er on sidewal ls of the via so as to se p arate the conductive material from the SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.1.22.778.2632.932.2680.svg 0.16 0.513 Chemistry Black and white nitride m ate rialt SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.1.22.1270.2632.1394.2680.svg 0.16 0.413 Chemistry Black and white and thesubs trat e, wherein the barrier la y er p revents chemical reactions between the conductive material and the substrate. SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.2.3.1481.332.1984.380.svg 0.16 1.677 Chemistry Black and white Attorney Docket No. 1 012-1842/2006P₈₀₁₂ 5 US OI whe rein the banrier layer comprises oneor more of and plati num. Currently amended
The method of claim 24, wherein the source field plate extends over the gate electrode. New
The method of claim 24, further comprising: forming a n encapsulation layer over at least the gate electrode and the passivation layer. New
The method of claim 24, wherein the source field plate is for m ed on a dielectric layer. New
The method of claim 24, wherein the source field plate is formed on the passivation layer. New
The method of claim 24, further comprising: forming a gate electrode via i n the passivation layer in which the gate electrode is formed. 42. The method of claim 41, wherein a cross-sectional area at a top of the gate electrode via is greater than a cross-sectional area at a bottom of the gate electrode via. New
The method of claim 24, further comprising: forming a compositionally-graded transition layer between the substrate and the gallium nitride material region. New
The method of claim 24, wherein the barrier layer comprises more than one of titanium, tungsten, nickel and platinum alloyed to fo rm a single composition. New
The method of claim 24, wherein the barrier layer comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different layers. New
The method of claim 24, wherein the barrier layer comprises a titanium-tungsten alloy. New
25-35. Canceled
Canceled
A method of manufacturing a transistor unit cell, the method comprising: forming a gallium nitride material region over a substrate; forming a plurality of transistor building block structures, each transistor building block structure comprising: a source electrode, at least in part, over the gallium nitride material region; a gate electrode, at least in part, over the gallium nitride material region; a drain electrode, at least in part, over the gallium nitride material region; a passivation l ayer over the galliu m nitride material region between the source electrode and the gate electrode, and between the gate electrode and the drain electrode, the gate electrode extending over a portion of the passivation layer a distance directly on the passivation layer in a direction of the drain electrode greater th SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.4.7.1365.804.1378.830.svg 0.087 0.043 Chemistry Black and white an a distance in a direction of the source electrode; a source field plate comprising a conductive material that is electrically connected to the sourc e electrode; a v i a which extends through the gallium nitri de material and the s ubstrate to a backside of the substrate; a conductive material in the via and which electrically connects the source field plate to a conductive region at the backside of the substrate; a nd a barrier layer on sidewal ls of the via so as to separate the conductive material from the gallium nitride material region and the substrate, the barrier layer preventing chemical reactions between the conductive material and the substrate, the barrier layer comprising one or more of titanium, tungsten, nickel and platinum; connecting the source electrodes in the transistor building block st n ctures to a common source pad; connecting the gate electrodes in the transistor building block structures to a common gate pad; and connecting the drain electrodes in the transistor building block st n ctures to a common drain pad. New
The method of claim 47, wherein the barrier layer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum alloyed to form a single composition. New
The method of claim 47, wherein the b arrier l ayer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different la y ers. New
50. The method of claim 47, wherein the barrier layer in each transistor building block structure comprises a titanium-tungsten alloy. New
A method of manufacturing a power transistor, comprising: forming a gallium nitride material region over a substrate; forming a plurality of transistor unit cells arranged in parallel, each transistor unit cell comprising a plurality of transistor building block structures, each tra n sistor building block structure comprising: a source electrode, at least in part, over the gallium nitride material region; a gate electrode, at least in part, over the gallium nitride material region; a drain electrode, at least in part, over the gallium nitride material re gion; a passivation layer over the gallium nitride material region between the source electrode and the gate electrode, and between the gate electrode and the drain electrode, the gate electrode extending over a portion of the passivation layer a distance directly on the passi v ation layer in a direction of the drain electrode greater than a distance in a direction of the source electrode; a source field plate comprising a conductive material that is electrically connected to the source electrode; a via which extends through the gallium nitride material and the substrate to a backside of the substrate; a conductive material in the via and which electrically connects the source field plate to a conductive region at the backside of the substrate; and a barrier l ayer on sidewalls of the via so as to separate the conductive material from the gallium nitride material region and the substrate, the barrier layer preventing chemical reactions between the conductive material and the substrate, the barrier l ayer comprising one or more of titanium, tungsten, nickel and platinum, wherein the source electrodes in the transistor building block structures are connected to a common source pad in the respective transistor unit cells, wherein the gate electrodes in the transistor building block st n ctures are connected to a common gate pad in the respective transistor unit cells, wherein the drain electrodes in the transistor building block structures are connected to a common drain pad in the respective transistor unit cells; connecting the source pads in the transistor unit cells to a source bus; connecting the drain pads in the transistor unit cells to a drain bus; and connecting the gate pads in the transistor unit cells to a gate bus. Attorney Docket No. 1012- 1842/2006P₈₀₁₂₅ US OI New
The method of claim 51, wherein the barrier layer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum alloyed to form a single composition. New
The method of claim 51, wherein the barrier layer in each transistor building block structure comprises a titanium-tungsten alloy. New
5 3. The method of claim 5 1, wherein the b arrier l ayer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different la y ers. New
Embodiments described in the patent, grouped by the materials and process steps they use.
1 material
A 0.7 micron gallium nitride material transistor with a source field plate. Performance data includes fT vs. Vg at Vd=28V, pulsed Psat and drain efficiency versus drain bias for a 36 mm device, pulsed and CW RF power sweeps at Vd=60V and Idq=1A, backed-off performance under two-carrier WCDMA signal at Vd=48V and Idq=1A, and drain current drift data at 45V and junction temperature of 200°C.
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride transistor with source field plate and via
Materials described outside the worked examples.
titanium
Ti
tungsten
W
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A is a cross-section of a gallium nitride material transistor building block structure according to one embodiment of the invention. 10
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–1 µm | — |
— | 180–500 W |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,978,858Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a cross-section of a gallium nitride material transistor building block structure according to one embodiment of the invention. 10
FIG. 2 is a cross-section of a gallium nitride material transistor including a source field plate as described in Example 1.
FIG. 3 shows a gallium nitride material transistor die as described in Example 1
FIG. 4 is an I -V curve for a gallium nitride material transistor as described in 20 Example 1.
FIG. 5 is a simulation of electric fields in the gate drain region for a gallium nitride material transistor without a source field plate under conditions V g s …
FIG. 6 is a simulation of electric fields in the gate drain region for a gallium 25 nitride material transistor without a source field plate under conditions V …
FIG. 7 is a graph of simulated values of the peak electric fields for a gallium nitride material transistor with and without the source field plate under …
FIG. 8 is a graph of pulsed I -V measurements for a gallium nitride material transistor with and without the source field plate in which the transistors were …
FIG. 9 is a graph that compares C gd and MSG versus drain bias at 2.14 GHz for a gallium nitride material transistor with and without a source field plate as …
FIG. 10 shows the f T performance versus gate bias for a 2 mm device with a source field plate operating at a drain bias of 28 V. At an I DQ of 27.5 mA/mm, the …
FIG. 11 demonstrates the disparity in the 10 performance of P s at and SVG 15433473.02-15-2017.IZ₇EVSCERXEAPX4.SPEC.25.10.895.1172.984.1204.svg 0.107 0.297 …
FIG. 12 shows a pulsed RF power sweep at a bias condition of V d = 60 V and I dq 10 = 1 A for a 36 mm gallium nitride material transistor with a source field …
FIG. 13. The device 15 demonstrated 65.5 W (1.8W/mm) of Ps at, a 'rmax of 65 % and 16 dB of small signal gain. The linear performance of the transistor is …
FIG. 14 shows the backed-off performance of the 20 device. At a back-off of 8 dB the device delivers ~2 0.5 W with ~ 35 % of drain efficiency and-17.5 dB of gain …
FIG. 15 is a graph of I ds versus time which shows the drain current drift of devices operated at 45 V and a junction temperature of 200 * C with the median 20 …
FIG. 16. However, it should be understood that the source field plate is not connected to a conductive region at the backside of the device in all embodiments …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-23. Canceled
Canceled
A method, comprising: forming a gallium nitride material region over a su bstrate-forming a source electrode, at least in part, over the gallium nitride material region; forming a gate electrode, at least in part, over the gallium nitride material region; forming a drain electrode, at least in part, over the gallium nitride material region; formnina passivationtlayerover the g all imnitr ide materiat SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.1.10.1669.1252.1792.1300.svg 0.16 0.41 Chemistry Black and white tb etwee nthe source electrode and the g ate electrode. and between the g ate electrode and the drain electrode, the g ate electrode extendin g over a portion of the passivation la y er a distance directly on the p assivation la y er in a direction of the drain electrode gaterthantadistancg ina directionof the source electrode. forming a source field plate comprising a conductive material that is electrically connected to the source electrode, formin g a via which extends throu g h the g allium nitride material and the substrate to a b ack side of the sutrate; formin g a conductive material in the via and which electrically connects the source field plate to a conductive re z ion at the backside of the substrate: and formin g a barrier la y er on sidewal ls of the via so as to se p arate the conductive material from the SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.1.22.778.2632.932.2680.svg 0.16 0.513 Chemistry Black and white nitride m ate rialt SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.1.22.1270.2632.1394.2680.svg 0.16 0.413 Chemistry Black and white and thesubs trat e, wherein the barrier la y er p revents chemical reactions between the conductive material and the substrate. SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.2.3.1481.332.1984.380.svg 0.16 1.677 Chemistry Black and white Attorney Docket No. 1 012-1842/2006P₈₀₁₂ 5 US OI whe rein the banrier layer comprises oneor more of and plati num. Currently amended
The method of claim 24, wherein the source field plate extends over the gate electrode. New
The method of claim 24, further comprising: forming a n encapsulation layer over at least the gate electrode and the passivation layer. New
The method of claim 24, wherein the source field plate is for m ed on a dielectric layer. New
The method of claim 24, wherein the source field plate is formed on the passivation layer. New
The method of claim 24, further comprising: forming a gate electrode via i n the passivation layer in which the gate electrode is formed. 42. The method of claim 41, wherein a cross-sectional area at a top of the gate electrode via is greater than a cross-sectional area at a bottom of the gate electrode via. New
The method of claim 24, further comprising: forming a compositionally-graded transition layer between the substrate and the gallium nitride material region. New
The method of claim 24, wherein the barrier layer comprises more than one of titanium, tungsten, nickel and platinum alloyed to fo rm a single composition. New
The method of claim 24, wherein the barrier layer comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different layers. New
The method of claim 24, wherein the barrier layer comprises a titanium-tungsten alloy. New
25-35. Canceled
Canceled
A method of manufacturing a transistor unit cell, the method comprising: forming a gallium nitride material region over a substrate; forming a plurality of transistor building block structures, each transistor building block structure comprising: a source electrode, at least in part, over the gallium nitride material region; a gate electrode, at least in part, over the gallium nitride material region; a drain electrode, at least in part, over the gallium nitride material region; a passivation l ayer over the galliu m nitride material region between the source electrode and the gate electrode, and between the gate electrode and the drain electrode, the gate electrode extending over a portion of the passivation layer a distance directly on the passivation layer in a direction of the drain electrode greater th SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.4.7.1365.804.1378.830.svg 0.087 0.043 Chemistry Black and white an a distance in a direction of the source electrode; a source field plate comprising a conductive material that is electrically connected to the sourc e electrode; a v i a which extends through the gallium nitri de material and the s ubstrate to a backside of the substrate; a conductive material in the via and which electrically connects the source field plate to a conductive region at the backside of the substrate; a nd a barrier layer on sidewal ls of the via so as to separate the conductive material from the gallium nitride material region and the substrate, the barrier layer preventing chemical reactions between the conductive material and the substrate, the barrier layer comprising one or more of titanium, tungsten, nickel and platinum; connecting the source electrodes in the transistor building block st n ctures to a common source pad; connecting the gate electrodes in the transistor building block structures to a common gate pad; and connecting the drain electrodes in the transistor building block st n ctures to a common drain pad. New
The method of claim 47, wherein the barrier layer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum alloyed to form a single composition. New
The method of claim 47, wherein the b arrier l ayer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different la y ers. New
50. The method of claim 47, wherein the barrier layer in each transistor building block structure comprises a titanium-tungsten alloy. New
A method of manufacturing a power transistor, comprising: forming a gallium nitride material region over a substrate; forming a plurality of transistor unit cells arranged in parallel, each transistor unit cell comprising a plurality of transistor building block structures, each tra n sistor building block structure comprising: a source electrode, at least in part, over the gallium nitride material region; a gate electrode, at least in part, over the gallium nitride material region; a drain electrode, at least in part, over the gallium nitride material re gion; a passivation layer over the gallium nitride material region between the source electrode and the gate electrode, and between the gate electrode and the drain electrode, the gate electrode extending over a portion of the passivation layer a distance directly on the passi v ation layer in a direction of the drain electrode greater than a distance in a direction of the source electrode; a source field plate comprising a conductive material that is electrically connected to the source electrode; a via which extends through the gallium nitride material and the substrate to a backside of the substrate; a conductive material in the via and which electrically connects the source field plate to a conductive region at the backside of the substrate; and a barrier l ayer on sidewalls of the via so as to separate the conductive material from the gallium nitride material region and the substrate, the barrier layer preventing chemical reactions between the conductive material and the substrate, the barrier l ayer comprising one or more of titanium, tungsten, nickel and platinum, wherein the source electrodes in the transistor building block structures are connected to a common source pad in the respective transistor unit cells, wherein the gate electrodes in the transistor building block st n ctures are connected to a common gate pad in the respective transistor unit cells, wherein the drain electrodes in the transistor building block structures are connected to a common drain pad in the respective transistor unit cells; connecting the source pads in the transistor unit cells to a source bus; connecting the drain pads in the transistor unit cells to a drain bus; and connecting the gate pads in the transistor unit cells to a gate bus. Attorney Docket No. 1012- 1842/2006P₈₀₁₂₅ US OI New
The method of claim 51, wherein the barrier layer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum alloyed to form a single composition. New
The method of claim 51, wherein the barrier layer in each transistor building block structure comprises a titanium-tungsten alloy. New
5 3. The method of claim 5 1, wherein the b arrier l ayer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different la y ers. New
Embodiments described in the patent, grouped by the materials and process steps they use.
1 material
A 0.7 micron gallium nitride material transistor with a source field plate. Performance data includes fT vs. Vg at Vd=28V, pulsed Psat and drain efficiency versus drain bias for a 36 mm device, pulsed and CW RF power sweeps at Vd=60V and Idq=1A, backed-off performance under two-carrier WCDMA signal at Vd=48V and Idq=1A, and drain current drift data at 45V and junction temperature of 200°C.
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride transistor with source field plate and via
Materials described outside the worked examples.
titanium
Ti
tungsten
W
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A is a cross-section of a gallium nitride material transistor building block structure according to one embodiment of the invention. 10
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–1 µm | — |
— | 180–500 W |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,978,858Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a cross-section of a gallium nitride material transistor building block structure according to one embodiment of the invention. 10
FIG. 2 is a cross-section of a gallium nitride material transistor including a source field plate as described in Example 1.
FIG. 3 shows a gallium nitride material transistor die as described in Example 1
FIG. 4 is an I -V curve for a gallium nitride material transistor as described in 20 Example 1.
FIG. 5 is a simulation of electric fields in the gate drain region for a gallium nitride material transistor without a source field plate under conditions V g s …
FIG. 6 is a simulation of electric fields in the gate drain region for a gallium 25 nitride material transistor without a source field plate under conditions V …
FIG. 7 is a graph of simulated values of the peak electric fields for a gallium nitride material transistor with and without the source field plate under …
FIG. 8 is a graph of pulsed I -V measurements for a gallium nitride material transistor with and without the source field plate in which the transistors were …
FIG. 9 is a graph that compares C gd and MSG versus drain bias at 2.14 GHz for a gallium nitride material transistor with and without a source field plate as …
FIG. 10 shows the f T performance versus gate bias for a 2 mm device with a source field plate operating at a drain bias of 28 V. At an I DQ of 27.5 mA/mm, the …
FIG. 11 demonstrates the disparity in the 10 performance of P s at and SVG 15433473.02-15-2017.IZ₇EVSCERXEAPX4.SPEC.25.10.895.1172.984.1204.svg 0.107 0.297 …
FIG. 12 shows a pulsed RF power sweep at a bias condition of V d = 60 V and I dq 10 = 1 A for a 36 mm gallium nitride material transistor with a source field …
FIG. 13. The device 15 demonstrated 65.5 W (1.8W/mm) of Ps at, a 'rmax of 65 % and 16 dB of small signal gain. The linear performance of the transistor is …
FIG. 14 shows the backed-off performance of the 20 device. At a back-off of 8 dB the device delivers ~2 0.5 W with ~ 35 % of drain efficiency and-17.5 dB of gain …
FIG. 15 is a graph of I ds versus time which shows the drain current drift of devices operated at 45 V and a junction temperature of 200 * C with the median 20 …
FIG. 16. However, it should be understood that the source field plate is not connected to a conductive region at the backside of the device in all embodiments …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-23. Canceled
Canceled
A method, comprising: forming a gallium nitride material region over a su bstrate-forming a source electrode, at least in part, over the gallium nitride material region; forming a gate electrode, at least in part, over the gallium nitride material region; forming a drain electrode, at least in part, over the gallium nitride material region; formnina passivationtlayerover the g all imnitr ide materiat SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.1.10.1669.1252.1792.1300.svg 0.16 0.41 Chemistry Black and white tb etwee nthe source electrode and the g ate electrode. and between the g ate electrode and the drain electrode, the g ate electrode extendin g over a portion of the passivation la y er a distance directly on the p assivation la y er in a direction of the drain electrode gaterthantadistancg ina directionof the source electrode. forming a source field plate comprising a conductive material that is electrically connected to the source electrode, formin g a via which extends throu g h the g allium nitride material and the substrate to a b ack side of the sutrate; formin g a conductive material in the via and which electrically connects the source field plate to a conductive re z ion at the backside of the substrate: and formin g a barrier la y er on sidewal ls of the via so as to se p arate the conductive material from the SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.1.22.778.2632.932.2680.svg 0.16 0.513 Chemistry Black and white nitride m ate rialt SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.1.22.1270.2632.1394.2680.svg 0.16 0.413 Chemistry Black and white and thesubs trat e, wherein the barrier la y er p revents chemical reactions between the conductive material and the substrate. SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.2.3.1481.332.1984.380.svg 0.16 1.677 Chemistry Black and white Attorney Docket No. 1 012-1842/2006P₈₀₁₂ 5 US OI whe rein the banrier layer comprises oneor more of and plati num. Currently amended
The method of claim 24, wherein the source field plate extends over the gate electrode. New
The method of claim 24, further comprising: forming a n encapsulation layer over at least the gate electrode and the passivation layer. New
The method of claim 24, wherein the source field plate is for m ed on a dielectric layer. New
The method of claim 24, wherein the source field plate is formed on the passivation layer. New
The method of claim 24, further comprising: forming a gate electrode via i n the passivation layer in which the gate electrode is formed. 42. The method of claim 41, wherein a cross-sectional area at a top of the gate electrode via is greater than a cross-sectional area at a bottom of the gate electrode via. New
The method of claim 24, further comprising: forming a compositionally-graded transition layer between the substrate and the gallium nitride material region. New
The method of claim 24, wherein the barrier layer comprises more than one of titanium, tungsten, nickel and platinum alloyed to fo rm a single composition. New
The method of claim 24, wherein the barrier layer comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different layers. New
The method of claim 24, wherein the barrier layer comprises a titanium-tungsten alloy. New
25-35. Canceled
Canceled
A method of manufacturing a transistor unit cell, the method comprising: forming a gallium nitride material region over a substrate; forming a plurality of transistor building block structures, each transistor building block structure comprising: a source electrode, at least in part, over the gallium nitride material region; a gate electrode, at least in part, over the gallium nitride material region; a drain electrode, at least in part, over the gallium nitride material region; a passivation l ayer over the galliu m nitride material region between the source electrode and the gate electrode, and between the gate electrode and the drain electrode, the gate electrode extending over a portion of the passivation layer a distance directly on the passivation layer in a direction of the drain electrode greater th SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.4.7.1365.804.1378.830.svg 0.087 0.043 Chemistry Black and white an a distance in a direction of the source electrode; a source field plate comprising a conductive material that is electrically connected to the sourc e electrode; a v i a which extends through the gallium nitri de material and the s ubstrate to a backside of the substrate; a conductive material in the via and which electrically connects the source field plate to a conductive region at the backside of the substrate; a nd a barrier layer on sidewal ls of the via so as to separate the conductive material from the gallium nitride material region and the substrate, the barrier layer preventing chemical reactions between the conductive material and the substrate, the barrier layer comprising one or more of titanium, tungsten, nickel and platinum; connecting the source electrodes in the transistor building block st n ctures to a common source pad; connecting the gate electrodes in the transistor building block structures to a common gate pad; and connecting the drain electrodes in the transistor building block st n ctures to a common drain pad. New
The method of claim 47, wherein the barrier layer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum alloyed to form a single composition. New
The method of claim 47, wherein the b arrier l ayer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different la y ers. New
50. The method of claim 47, wherein the barrier layer in each transistor building block structure comprises a titanium-tungsten alloy. New
A method of manufacturing a power transistor, comprising: forming a gallium nitride material region over a substrate; forming a plurality of transistor unit cells arranged in parallel, each transistor unit cell comprising a plurality of transistor building block structures, each tra n sistor building block structure comprising: a source electrode, at least in part, over the gallium nitride material region; a gate electrode, at least in part, over the gallium nitride material region; a drain electrode, at least in part, over the gallium nitride material re gion; a passivation layer over the gallium nitride material region between the source electrode and the gate electrode, and between the gate electrode and the drain electrode, the gate electrode extending over a portion of the passivation layer a distance directly on the passi v ation layer in a direction of the drain electrode greater than a distance in a direction of the source electrode; a source field plate comprising a conductive material that is electrically connected to the source electrode; a via which extends through the gallium nitride material and the substrate to a backside of the substrate; a conductive material in the via and which electrically connects the source field plate to a conductive region at the backside of the substrate; and a barrier l ayer on sidewalls of the via so as to separate the conductive material from the gallium nitride material region and the substrate, the barrier layer preventing chemical reactions between the conductive material and the substrate, the barrier l ayer comprising one or more of titanium, tungsten, nickel and platinum, wherein the source electrodes in the transistor building block structures are connected to a common source pad in the respective transistor unit cells, wherein the gate electrodes in the transistor building block st n ctures are connected to a common gate pad in the respective transistor unit cells, wherein the drain electrodes in the transistor building block structures are connected to a common drain pad in the respective transistor unit cells; connecting the source pads in the transistor unit cells to a source bus; connecting the drain pads in the transistor unit cells to a drain bus; and connecting the gate pads in the transistor unit cells to a gate bus. Attorney Docket No. 1012- 1842/2006P₈₀₁₂₅ US OI New
The method of claim 51, wherein the barrier layer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum alloyed to form a single composition. New
The method of claim 51, wherein the barrier layer in each transistor building block structure comprises a titanium-tungsten alloy. New
5 3. The method of claim 5 1, wherein the b arrier l ayer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different la y ers. New
Embodiments described in the patent, grouped by the materials and process steps they use.
1 material
A 0.7 micron gallium nitride material transistor with a source field plate. Performance data includes fT vs. Vg at Vd=28V, pulsed Psat and drain efficiency versus drain bias for a 36 mm device, pulsed and CW RF power sweeps at Vd=60V and Idq=1A, backed-off performance under two-carrier WCDMA signal at Vd=48V and Idq=1A, and drain current drift data at 45V and junction temperature of 200°C.
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride transistor with source field plate and via
Materials described outside the worked examples.
titanium
Ti
tungsten
W
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A is a cross-section of a gallium nitride material transistor building block structure according to one embodiment of the invention. 10
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–1 µm | — |
— | 180–500 W |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,978,858Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a cross-section of a gallium nitride material transistor building block structure according to one embodiment of the invention. 10
FIG. 2 is a cross-section of a gallium nitride material transistor including a source field plate as described in Example 1.
FIG. 3 shows a gallium nitride material transistor die as described in Example 1
FIG. 4 is an I -V curve for a gallium nitride material transistor as described in 20 Example 1.
FIG. 5 is a simulation of electric fields in the gate drain region for a gallium nitride material transistor without a source field plate under conditions V g s …
FIG. 6 is a simulation of electric fields in the gate drain region for a gallium 25 nitride material transistor without a source field plate under conditions V …
FIG. 7 is a graph of simulated values of the peak electric fields for a gallium nitride material transistor with and without the source field plate under …
FIG. 8 is a graph of pulsed I -V measurements for a gallium nitride material transistor with and without the source field plate in which the transistors were …
FIG. 9 is a graph that compares C gd and MSG versus drain bias at 2.14 GHz for a gallium nitride material transistor with and without a source field plate as …
FIG. 10 shows the f T performance versus gate bias for a 2 mm device with a source field plate operating at a drain bias of 28 V. At an I DQ of 27.5 mA/mm, the …
FIG. 11 demonstrates the disparity in the 10 performance of P s at and SVG 15433473.02-15-2017.IZ₇EVSCERXEAPX4.SPEC.25.10.895.1172.984.1204.svg 0.107 0.297 …
FIG. 12 shows a pulsed RF power sweep at a bias condition of V d = 60 V and I dq 10 = 1 A for a 36 mm gallium nitride material transistor with a source field …
FIG. 13. The device 15 demonstrated 65.5 W (1.8W/mm) of Ps at, a 'rmax of 65 % and 16 dB of small signal gain. The linear performance of the transistor is …
FIG. 14 shows the backed-off performance of the 20 device. At a back-off of 8 dB the device delivers ~2 0.5 W with ~ 35 % of drain efficiency and-17.5 dB of gain …
FIG. 15 is a graph of I ds versus time which shows the drain current drift of devices operated at 45 V and a junction temperature of 200 * C with the median 20 …
FIG. 16. However, it should be understood that the source field plate is not connected to a conductive region at the backside of the device in all embodiments …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-23. Canceled
Canceled
A method, comprising: forming a gallium nitride material region over a su bstrate-forming a source electrode, at least in part, over the gallium nitride material region; forming a gate electrode, at least in part, over the gallium nitride material region; forming a drain electrode, at least in part, over the gallium nitride material region; formnina passivationtlayerover the g all imnitr ide materiat SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.1.10.1669.1252.1792.1300.svg 0.16 0.41 Chemistry Black and white tb etwee nthe source electrode and the g ate electrode. and between the g ate electrode and the drain electrode, the g ate electrode extendin g over a portion of the passivation la y er a distance directly on the p assivation la y er in a direction of the drain electrode gaterthantadistancg ina directionof the source electrode. forming a source field plate comprising a conductive material that is electrically connected to the source electrode, formin g a via which extends throu g h the g allium nitride material and the substrate to a b ack side of the sutrate; formin g a conductive material in the via and which electrically connects the source field plate to a conductive re z ion at the backside of the substrate: and formin g a barrier la y er on sidewal ls of the via so as to se p arate the conductive material from the SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.1.22.778.2632.932.2680.svg 0.16 0.513 Chemistry Black and white nitride m ate rialt SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.1.22.1270.2632.1394.2680.svg 0.16 0.413 Chemistry Black and white and thesubs trat e, wherein the barrier la y er p revents chemical reactions between the conductive material and the substrate. SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.2.3.1481.332.1984.380.svg 0.16 1.677 Chemistry Black and white Attorney Docket No. 1 012-1842/2006P₈₀₁₂ 5 US OI whe rein the banrier layer comprises oneor more of and plati num. Currently amended
The method of claim 24, wherein the source field plate extends over the gate electrode. New
The method of claim 24, further comprising: forming a n encapsulation layer over at least the gate electrode and the passivation layer. New
The method of claim 24, wherein the source field plate is for m ed on a dielectric layer. New
The method of claim 24, wherein the source field plate is formed on the passivation layer. New
The method of claim 24, further comprising: forming a gate electrode via i n the passivation layer in which the gate electrode is formed. 42. The method of claim 41, wherein a cross-sectional area at a top of the gate electrode via is greater than a cross-sectional area at a bottom of the gate electrode via. New
The method of claim 24, further comprising: forming a compositionally-graded transition layer between the substrate and the gallium nitride material region. New
The method of claim 24, wherein the barrier layer comprises more than one of titanium, tungsten, nickel and platinum alloyed to fo rm a single composition. New
The method of claim 24, wherein the barrier layer comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different layers. New
The method of claim 24, wherein the barrier layer comprises a titanium-tungsten alloy. New
25-35. Canceled
Canceled
A method of manufacturing a transistor unit cell, the method comprising: forming a gallium nitride material region over a substrate; forming a plurality of transistor building block structures, each transistor building block structure comprising: a source electrode, at least in part, over the gallium nitride material region; a gate electrode, at least in part, over the gallium nitride material region; a drain electrode, at least in part, over the gallium nitride material region; a passivation l ayer over the galliu m nitride material region between the source electrode and the gate electrode, and between the gate electrode and the drain electrode, the gate electrode extending over a portion of the passivation layer a distance directly on the passivation layer in a direction of the drain electrode greater th SVG 15433473.12-28-2017.JBS₈LQ03PXXIFW1.CLM.4.7.1365.804.1378.830.svg 0.087 0.043 Chemistry Black and white an a distance in a direction of the source electrode; a source field plate comprising a conductive material that is electrically connected to the sourc e electrode; a v i a which extends through the gallium nitri de material and the s ubstrate to a backside of the substrate; a conductive material in the via and which electrically connects the source field plate to a conductive region at the backside of the substrate; a nd a barrier layer on sidewal ls of the via so as to separate the conductive material from the gallium nitride material region and the substrate, the barrier layer preventing chemical reactions between the conductive material and the substrate, the barrier layer comprising one or more of titanium, tungsten, nickel and platinum; connecting the source electrodes in the transistor building block st n ctures to a common source pad; connecting the gate electrodes in the transistor building block structures to a common gate pad; and connecting the drain electrodes in the transistor building block st n ctures to a common drain pad. New
The method of claim 47, wherein the barrier layer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum alloyed to form a single composition. New
The method of claim 47, wherein the b arrier l ayer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different la y ers. New
50. The method of claim 47, wherein the barrier layer in each transistor building block structure comprises a titanium-tungsten alloy. New
A method of manufacturing a power transistor, comprising: forming a gallium nitride material region over a substrate; forming a plurality of transistor unit cells arranged in parallel, each transistor unit cell comprising a plurality of transistor building block structures, each tra n sistor building block structure comprising: a source electrode, at least in part, over the gallium nitride material region; a gate electrode, at least in part, over the gallium nitride material region; a drain electrode, at least in part, over the gallium nitride material re gion; a passivation layer over the gallium nitride material region between the source electrode and the gate electrode, and between the gate electrode and the drain electrode, the gate electrode extending over a portion of the passivation layer a distance directly on the passi v ation layer in a direction of the drain electrode greater than a distance in a direction of the source electrode; a source field plate comprising a conductive material that is electrically connected to the source electrode; a via which extends through the gallium nitride material and the substrate to a backside of the substrate; a conductive material in the via and which electrically connects the source field plate to a conductive region at the backside of the substrate; and a barrier l ayer on sidewalls of the via so as to separate the conductive material from the gallium nitride material region and the substrate, the barrier layer preventing chemical reactions between the conductive material and the substrate, the barrier l ayer comprising one or more of titanium, tungsten, nickel and platinum, wherein the source electrodes in the transistor building block structures are connected to a common source pad in the respective transistor unit cells, wherein the gate electrodes in the transistor building block st n ctures are connected to a common gate pad in the respective transistor unit cells, wherein the drain electrodes in the transistor building block structures are connected to a common drain pad in the respective transistor unit cells; connecting the source pads in the transistor unit cells to a source bus; connecting the drain pads in the transistor unit cells to a drain bus; and connecting the gate pads in the transistor unit cells to a gate bus. Attorney Docket No. 1012- 1842/2006P₈₀₁₂₅ US OI New
The method of claim 51, wherein the barrier layer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum alloyed to form a single composition. New
The method of claim 51, wherein the barrier layer in each transistor building block structure comprises a titanium-tungsten alloy. New
5 3. The method of claim 5 1, wherein the b arrier l ayer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different la y ers. New
Embodiments described in the patent, grouped by the materials and process steps they use.
1 material
A 0.7 micron gallium nitride material transistor with a source field plate. Performance data includes fT vs. Vg at Vd=28V, pulsed Psat and drain efficiency versus drain bias for a 36 mm device, pulsed and CW RF power sweeps at Vd=60V and Idq=1A, backed-off performance under two-carrier WCDMA signal at Vd=48V and Idq=1A, and drain current drift data at 45V and junction temperature of 200°C.
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride transistor with source field plate and via
Materials described outside the worked examples.
titanium
Ti
tungsten
W
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A is a cross-section of a gallium nitride material transistor building block structure according to one embodiment of the invention. 10
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–1 µm | — |
— | 180–500 W |
Related documents with shared materials, methods, properties, or citations.
transistor unit cell with multiple building block structures
power transistor with multiple unit cells arranged in parallel
gallium nitride material transistor with source field plate (Example 1)
nickel
Ni
platinum
Pt
titanium-tungsten alloy
TiW
FIG. 2 is a cross-section of a gallium nitride material transistor including a source field plate as described in Example 1.
FIG. 3 shows a gallium nitride material transistor die as described in Example 1
FIG. 4 is an I -V curve for a gallium nitride material transistor as described in 20 Example 1.
FIG. 5 is a simulation of electric fields in the gate drain region for a gallium nitride material transistor without a source field plate under conditions V g s …
FIG. 6 is a simulation of electric fields in the gate drain region for a gallium 25 nitride material transistor without a source field plate under conditions V …
FIG. 7 is a graph of simulated values of the peak electric fields for a gallium nitride material transistor with and without the source field plate under …
FIG. 7 is a graph of simulated values of the peak electric fields for a gallium nitride material transistor with and without the source field plate under …
FIG. 8 is a graph of pulsed I -V measurements for a gallium nitride material transistor with and without the source field plate in which the transistors were …
FIG. 8 is a graph of pulsed I -V measurements for a gallium nitride material transistor with and without the source field plate in which the transistors were …
FIG. 9 is a graph that compares C gd and MSG versus drain bias at 2.14 GHz for a gallium nitride material transistor with and without a source field plate as …
FIG. 10 shows the f T performance versus gate bias for a 2 mm device with a source field plate operating at a drain bias of 28 V. At an I DQ of 27.5 mA/mm, the …
FIG. 10 shows the f T performance versus gate bias for a 2 mm device with a source field plate operating at a drain bias of 28 V. At an I DQ of 27.5 mA/mm, the …
FIG. 11 demonstrates the disparity in the 10 performance of P s at and SVG 15433473.02-15-2017.IZ₇EVSCERXEAPX4.SPEC.25.10.895.1172.984.1204.svg 0.107 0.297 …
FIG. 11 demonstrates the disparity in the 10 performance of P s at and SVG 15433473.02-15-2017.IZ₇EVSCERXEAPX4.SPEC.25.10.895.1172.984.1204.svg 0.107 0.297 …
FIG. 12 shows a pulsed RF power sweep at a bias condition of V d = 60 V and I dq 10 = 1 A for a 36 mm gallium nitride material transistor with a source field …
FIG. 13. The device 15 demonstrated 65.5 W (1.8W/mm) of Ps at, a 'rmax of 65 % and 16 dB of small signal gain. The linear performance of the transistor is …
FIG. 13. The device 15 demonstrated 65.5 W (1.8W/mm) of Ps at, a 'rmax of 65 % and 16 dB of small signal gain. The linear performance of the transistor is …
FIG. 14 shows the backed-off performance of the 20 device. At a back-off of 8 dB the device delivers ~2 0.5 W with ~ 35 % of drain efficiency and-17.5 dB of gain …
FIG. 14 shows the backed-off performance of the 20 device. At a back-off of 8 dB the device delivers ~2 0.5 W with ~ 35 % of drain efficiency and-17.5 dB of gain …
FIG. 15 is a graph of I ds versus time which shows the drain current drift of devices operated at 45 V and a junction temperature of 200 * C with the median 20 …
FIG. 15 is a graph of I ds versus time which shows the drain current drift of devices operated at 45 V and a junction temperature of 200 * C with the median 20 …
FIG. 16. However, it should be understood that the source field plate is not connected to a conductive region at the backside of the device in all embodiments …
| — |
Thickness | 125–800 µm | — |
Thickness | 400–800 µm | — |
Thickness | 200–800 µm | — |
Thickness | 10–100 Å | — |
Thickness | 100–10000 nm | — |
Thickness | 0.05–10 µm | — |
Thickness | ≤ 125 µm | — |
Thickness | ≤ 150 µm | — |
Thickness | ≥ 0.1 µm | — |
Thickness | ≥ 0.5 µm | — |
Thickness | ≥ 0.75 µm | — |
Thickness | ≥ 1 µm | — |
Thickness | ≥ 2 µm | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 125 µm | — |
Voltage | ≥ 120 V | — |
— | ≥ 10 W | — |
Duration | ≥ 1 hours | — |
transistor unit cell with multiple building block structures
power transistor with multiple unit cells arranged in parallel
gallium nitride material transistor with source field plate (Example 1)
nickel
Ni
platinum
Pt
titanium-tungsten alloy
TiW
FIG. 2 is a cross-section of a gallium nitride material transistor including a source field plate as described in Example 1.
FIG. 3 shows a gallium nitride material transistor die as described in Example 1
FIG. 4 is an I -V curve for a gallium nitride material transistor as described in 20 Example 1.
FIG. 5 is a simulation of electric fields in the gate drain region for a gallium nitride material transistor without a source field plate under conditions V g s …
FIG. 6 is a simulation of electric fields in the gate drain region for a gallium 25 nitride material transistor without a source field plate under conditions V …
FIG. 7 is a graph of simulated values of the peak electric fields for a gallium nitride material transistor with and without the source field plate under …
FIG. 7 is a graph of simulated values of the peak electric fields for a gallium nitride material transistor with and without the source field plate under …
FIG. 8 is a graph of pulsed I -V measurements for a gallium nitride material transistor with and without the source field plate in which the transistors were …
FIG. 8 is a graph of pulsed I -V measurements for a gallium nitride material transistor with and without the source field plate in which the transistors were …
FIG. 9 is a graph that compares C gd and MSG versus drain bias at 2.14 GHz for a gallium nitride material transistor with and without a source field plate as …
FIG. 10 shows the f T performance versus gate bias for a 2 mm device with a source field plate operating at a drain bias of 28 V. At an I DQ of 27.5 mA/mm, the …
FIG. 10 shows the f T performance versus gate bias for a 2 mm device with a source field plate operating at a drain bias of 28 V. At an I DQ of 27.5 mA/mm, the …
FIG. 11 demonstrates the disparity in the 10 performance of P s at and SVG 15433473.02-15-2017.IZ₇EVSCERXEAPX4.SPEC.25.10.895.1172.984.1204.svg 0.107 0.297 …
FIG. 11 demonstrates the disparity in the 10 performance of P s at and SVG 15433473.02-15-2017.IZ₇EVSCERXEAPX4.SPEC.25.10.895.1172.984.1204.svg 0.107 0.297 …
FIG. 12 shows a pulsed RF power sweep at a bias condition of V d = 60 V and I dq 10 = 1 A for a 36 mm gallium nitride material transistor with a source field …
FIG. 13. The device 15 demonstrated 65.5 W (1.8W/mm) of Ps at, a 'rmax of 65 % and 16 dB of small signal gain. The linear performance of the transistor is …
FIG. 13. The device 15 demonstrated 65.5 W (1.8W/mm) of Ps at, a 'rmax of 65 % and 16 dB of small signal gain. The linear performance of the transistor is …
FIG. 14 shows the backed-off performance of the 20 device. At a back-off of 8 dB the device delivers ~2 0.5 W with ~ 35 % of drain efficiency and-17.5 dB of gain …
FIG. 14 shows the backed-off performance of the 20 device. At a back-off of 8 dB the device delivers ~2 0.5 W with ~ 35 % of drain efficiency and-17.5 dB of gain …
FIG. 15 is a graph of I ds versus time which shows the drain current drift of devices operated at 45 V and a junction temperature of 200 * C with the median 20 …
FIG. 15 is a graph of I ds versus time which shows the drain current drift of devices operated at 45 V and a junction temperature of 200 * C with the median 20 …
FIG. 16. However, it should be understood that the source field plate is not connected to a conductive region at the backside of the device in all embodiments …
| — |
Thickness | 125–800 µm | — |
Thickness | 400–800 µm | — |
Thickness | 200–800 µm | — |
Thickness | 10–100 Å | — |
Thickness | 100–10000 nm | — |
Thickness | 0.05–10 µm | — |
Thickness | ≤ 125 µm | — |
Thickness | ≤ 150 µm | — |
Thickness | ≥ 0.1 µm | — |
Thickness | ≥ 0.5 µm | — |
Thickness | ≥ 0.75 µm | — |
Thickness | ≥ 1 µm | — |
Thickness | ≥ 2 µm | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 125 µm | — |
Voltage | ≥ 120 V | — |
— | ≥ 10 W | — |
Duration | ≥ 1 hours | — |
transistor unit cell with multiple building block structures
power transistor with multiple unit cells arranged in parallel
gallium nitride material transistor with source field plate (Example 1)
nickel
Ni
platinum
Pt
titanium-tungsten alloy
TiW
FIG. 2 is a cross-section of a gallium nitride material transistor including a source field plate as described in Example 1.
FIG. 3 shows a gallium nitride material transistor die as described in Example 1
FIG. 4 is an I -V curve for a gallium nitride material transistor as described in 20 Example 1.
FIG. 5 is a simulation of electric fields in the gate drain region for a gallium nitride material transistor without a source field plate under conditions V g s …
FIG. 6 is a simulation of electric fields in the gate drain region for a gallium 25 nitride material transistor without a source field plate under conditions V …
FIG. 7 is a graph of simulated values of the peak electric fields for a gallium nitride material transistor with and without the source field plate under …
FIG. 7 is a graph of simulated values of the peak electric fields for a gallium nitride material transistor with and without the source field plate under …
FIG. 8 is a graph of pulsed I -V measurements for a gallium nitride material transistor with and without the source field plate in which the transistors were …
FIG. 8 is a graph of pulsed I -V measurements for a gallium nitride material transistor with and without the source field plate in which the transistors were …
FIG. 9 is a graph that compares C gd and MSG versus drain bias at 2.14 GHz for a gallium nitride material transistor with and without a source field plate as …
FIG. 10 shows the f T performance versus gate bias for a 2 mm device with a source field plate operating at a drain bias of 28 V. At an I DQ of 27.5 mA/mm, the …
FIG. 10 shows the f T performance versus gate bias for a 2 mm device with a source field plate operating at a drain bias of 28 V. At an I DQ of 27.5 mA/mm, the …
FIG. 11 demonstrates the disparity in the 10 performance of P s at and SVG 15433473.02-15-2017.IZ₇EVSCERXEAPX4.SPEC.25.10.895.1172.984.1204.svg 0.107 0.297 …
FIG. 11 demonstrates the disparity in the 10 performance of P s at and SVG 15433473.02-15-2017.IZ₇EVSCERXEAPX4.SPEC.25.10.895.1172.984.1204.svg 0.107 0.297 …
FIG. 12 shows a pulsed RF power sweep at a bias condition of V d = 60 V and I dq 10 = 1 A for a 36 mm gallium nitride material transistor with a source field …
FIG. 13. The device 15 demonstrated 65.5 W (1.8W/mm) of Ps at, a 'rmax of 65 % and 16 dB of small signal gain. The linear performance of the transistor is …
FIG. 13. The device 15 demonstrated 65.5 W (1.8W/mm) of Ps at, a 'rmax of 65 % and 16 dB of small signal gain. The linear performance of the transistor is …
FIG. 14 shows the backed-off performance of the 20 device. At a back-off of 8 dB the device delivers ~2 0.5 W with ~ 35 % of drain efficiency and-17.5 dB of gain …
FIG. 14 shows the backed-off performance of the 20 device. At a back-off of 8 dB the device delivers ~2 0.5 W with ~ 35 % of drain efficiency and-17.5 dB of gain …
FIG. 15 is a graph of I ds versus time which shows the drain current drift of devices operated at 45 V and a junction temperature of 200 * C with the median 20 …
FIG. 15 is a graph of I ds versus time which shows the drain current drift of devices operated at 45 V and a junction temperature of 200 * C with the median 20 …
FIG. 16. However, it should be understood that the source field plate is not connected to a conductive region at the backside of the device in all embodiments …
| — |
Thickness | 125–800 µm | — |
Thickness | 400–800 µm | — |
Thickness | 200–800 µm | — |
Thickness | 10–100 Å | — |
Thickness | 100–10000 nm | — |
Thickness | 0.05–10 µm | — |
Thickness | ≤ 125 µm | — |
Thickness | ≤ 150 µm | — |
Thickness | ≥ 0.1 µm | — |
Thickness | ≥ 0.5 µm | — |
Thickness | ≥ 0.75 µm | — |
Thickness | ≥ 1 µm | — |
Thickness | ≥ 2 µm | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 125 µm | — |
Voltage | ≥ 120 V | — |
— | ≥ 10 W | — |
Duration | ≥ 1 hours | — |
transistor unit cell with multiple building block structures
power transistor with multiple unit cells arranged in parallel
gallium nitride material transistor with source field plate (Example 1)
nickel
Ni
platinum
Pt
titanium-tungsten alloy
TiW
FIG. 2 is a cross-section of a gallium nitride material transistor including a source field plate as described in Example 1.
FIG. 3 shows a gallium nitride material transistor die as described in Example 1
FIG. 4 is an I -V curve for a gallium nitride material transistor as described in 20 Example 1.
FIG. 5 is a simulation of electric fields in the gate drain region for a gallium nitride material transistor without a source field plate under conditions V g s …
FIG. 6 is a simulation of electric fields in the gate drain region for a gallium 25 nitride material transistor without a source field plate under conditions V …
FIG. 7 is a graph of simulated values of the peak electric fields for a gallium nitride material transistor with and without the source field plate under …
FIG. 7 is a graph of simulated values of the peak electric fields for a gallium nitride material transistor with and without the source field plate under …
FIG. 8 is a graph of pulsed I -V measurements for a gallium nitride material transistor with and without the source field plate in which the transistors were …
FIG. 8 is a graph of pulsed I -V measurements for a gallium nitride material transistor with and without the source field plate in which the transistors were …
FIG. 9 is a graph that compares C gd and MSG versus drain bias at 2.14 GHz for a gallium nitride material transistor with and without a source field plate as …
FIG. 10 shows the f T performance versus gate bias for a 2 mm device with a source field plate operating at a drain bias of 28 V. At an I DQ of 27.5 mA/mm, the …
FIG. 10 shows the f T performance versus gate bias for a 2 mm device with a source field plate operating at a drain bias of 28 V. At an I DQ of 27.5 mA/mm, the …
FIG. 11 demonstrates the disparity in the 10 performance of P s at and SVG 15433473.02-15-2017.IZ₇EVSCERXEAPX4.SPEC.25.10.895.1172.984.1204.svg 0.107 0.297 …
FIG. 11 demonstrates the disparity in the 10 performance of P s at and SVG 15433473.02-15-2017.IZ₇EVSCERXEAPX4.SPEC.25.10.895.1172.984.1204.svg 0.107 0.297 …
FIG. 12 shows a pulsed RF power sweep at a bias condition of V d = 60 V and I dq 10 = 1 A for a 36 mm gallium nitride material transistor with a source field …
FIG. 13. The device 15 demonstrated 65.5 W (1.8W/mm) of Ps at, a 'rmax of 65 % and 16 dB of small signal gain. The linear performance of the transistor is …
FIG. 13. The device 15 demonstrated 65.5 W (1.8W/mm) of Ps at, a 'rmax of 65 % and 16 dB of small signal gain. The linear performance of the transistor is …
FIG. 14 shows the backed-off performance of the 20 device. At a back-off of 8 dB the device delivers ~2 0.5 W with ~ 35 % of drain efficiency and-17.5 dB of gain …
FIG. 14 shows the backed-off performance of the 20 device. At a back-off of 8 dB the device delivers ~2 0.5 W with ~ 35 % of drain efficiency and-17.5 dB of gain …
FIG. 15 is a graph of I ds versus time which shows the drain current drift of devices operated at 45 V and a junction temperature of 200 * C with the median 20 …
FIG. 15 is a graph of I ds versus time which shows the drain current drift of devices operated at 45 V and a junction temperature of 200 * C with the median 20 …
FIG. 16. However, it should be understood that the source field plate is not connected to a conductive region at the backside of the device in all embodiments …
| — |
Thickness | 125–800 µm | — |
Thickness | 400–800 µm | — |
Thickness | 200–800 µm | — |
Thickness | 10–100 Å | — |
Thickness | 100–10000 nm | — |
Thickness | 0.05–10 µm | — |
Thickness | ≤ 125 µm | — |
Thickness | ≤ 150 µm | — |
Thickness | ≥ 0.1 µm | — |
Thickness | ≥ 0.5 µm | — |
Thickness | ≥ 0.75 µm | — |
Thickness | ≥ 1 µm | — |
Thickness | ≥ 2 µm | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 125 µm | — |
Voltage | ≥ 120 V | — |
— | ≥ 10 W | — |
Duration | ≥ 1 hours | — |