Patent
Atlas literature
Patent
US 12,080,786 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1a, 2, 3a, 3b, 4a, 4b, 4c, 5a, 5b, 6a, 6b, 7a, 7b, 8a, 8b, 9a, 9b, and 10 are decomposition schematic diagrams 40 illustrating a semiconductor structure …
FIG. 2, before the channel layer 23 is grown, a nucleation layer 21 and a buffer layer 22 may also be sequentially grown on the substrate 1. Taking a GaN-based …
FIG. 3a, preparing a p-type GaN-based semiconductor layer 5 above the semiconductor layer 3, an upper surface of the p-type GaN-based semicon- ductor layer 5 …
FIG. 4a, etching the p-type GaN- based semiconductor layer 5 selectively, and reserving only a portion of the p-type GaN-based semiconductor layer …
FIG. 5a, preparing a gate electrode 51, a source electrode 6, and a drain electrode 7. The gate electrode 51 is prepared on the p-type semicon- ductor layer 5, …
FIG. 6a, in order to further improve the performance of the 5 semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
FIGS. 7a and 7b, 15 the p-type GaN-based semiconductor layer 5 is prepared above the barrier layer 24. Then, as shown in
FIGS. 8a and 8b, the p-type GaN-based semiconductor layer 5 is selec- tively etched, and only the p-type GaN-based semiconductor layer 5 in the gate region is …
FIG. 9a, in order to further improve the performance of the semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
FIG. 10, when the semiconductor structure includes the groove 4, the barrier layer 24 may also adopt a sandwich structure. The sandwich structure includes a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: 15 a substrate; a channel layer, a barrier layer and a semiconductor layer sequentially superimposed on the substrate, wherein the semiconductor layer is made of a GaN-based mate-rial and an upper surface of the semiconductor layer is Ga-face; and a p-type GaN-based semiconductor layer, with N-face as an upper surface, formed in a gate region of the semiconductor layer, wherein the barrier layer comprises a first outer interlayer AlGaN, an intermediate layer GaN and a second outer interlayer AlGaN that are sequentially stacked on a surface of the channel layer.
The semiconductor structure according to claim 1, further comprising: 30 a gate electrode disposed on the p-type GaN-based semiconductor layer; a source electrode disposed in a source region of the barrier layer; and a drain electrode disposed in a drain region of the barrier layer.
The semiconductor structure according to claim 1, further comprising: a nucleation layer between the channel layer and the substrate; and 40 a buffer layer between the nucleation layer and the chan-nel layer.
The semiconductor structure according to claim 1, wherein the p-type GaN-based semiconductor layer com-prises a multilayer structure or a superlattice structure com-prising one or more materials of p-type AlGaN, p-type GaN, and p-type InGaN.
The semiconductor structure according to claim 1, further comprising a groove disposed in the gate region of the semiconductor layer, wherein the groove penetrates the semiconductor layer and stops on the barrier layer or par-tially penetrates the barrier layer and stops in the barrier layer.
The semiconductor structure according to claim 1, wherein the semiconductor structure further comprises a polarity reversal layer Al₂O₃ disposed between the semicon-ductor layer and the p-type GaN-based semiconductor layer with the N-face as the upper surface, and the p-type GaN-based semiconductor layer with the N-face as the upper surface is formed by reversing a p-type Ga-face GaN-based material by the polarity reversal layer Al₂O3.
The semiconductor structure according to claim 1, wherein the semiconductor layer comprises a first portion located outside the gate region and a second portion B₂ located within the gate region, and a thickness of the first portion is less than a thickness of the second portion.
A manufacturing method for a semiconductor structure, comprising: preparing a channel layer, a barrier layer and a semicon-ductor layer sequentially superimposed on a substrate, wherein the semiconductor layer is made of a GaN-based material and an upper surface of the semicon-ductor layer is Ga-face; and preparing a p-type GaN-based semiconductor layer with N-face as an upper surface above the semiconductor layer, wherein the barrier layer comprises a first outer interlayer AlGaN, an intermediate layer GaN and a second outer interlayer AlGaN that are sequentially stacked on a surface of the channel layer.
The manufacturing method for the semiconductor structure according to claim 9, wherein the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, comprises: preparing a p-type Ga-face GaN-based material above the semiconductor layer, and doping a polarity reversal element in the p-type Ga-face GaN-based material to reverse the p-type Ga-face GaN-based material to the p-type GaN-based semiconductor layer with the N-face as the upper surface.
The manufacturing method for the semiconductor structure according to claim 9, wherein the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, comprises: preparing a p-type Ga-face GaN-based material above the semiconductor layer; and reversing the p-type Ga-face GaN-based material by a polarity reversal layer to the p-type GaN-based semiconductor layer with the N-face as the upper surface.
The manufacturing method for the semiconductor structure according to claim 9, wherein the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, comprises: bonding the p-type GaN-based semiconductor layer with the N-face as the upper surface to the semiconductor layer directly.
The manufacturing method for the semiconductor structure according to claim 9, further comprising: etching the p-type GaN-based semiconductor layer selec-tively, and reserving only a portion of the p-type GaN-based semiconductor layer corresponding to a gate region.
The manufacturing method for the semiconductor structure according to claim 9, further comprising: preparing a gate electrode on the p-type GaN-based semiconductor layer, preparing a source electrode in a source region of the barrier layer, and preparing a drain electrode in a drain region of the barrier layer.
The manufacturing method for the semiconductor structure according to claim 9, further comprising: forming a nucleation layer and a buffer layer on the substrate sequentially before forming the channel layer.
The manufacturing method for the semiconductor structure according to claim 9, before the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, further comprising: 11 12 preparing a groove in a gate region of the semiconductor layer, wherein the groove penetrates the semiconductor layer and stops on the barrier layer or partially pen-etrates the barrier layer and stops in the barrier layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
p-GaN gate HEMT (enhancement-mode GaN transistor)
Materials described outside the worked examples.
GaN-based semiconductor layer (Ga-face)
AlGaN (first outer interlayer/second outer interlayer)
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 6a, in order to further improve the performance of the 5 semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 40 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 11
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Patent
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US 12,080,786 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1a, 2, 3a, 3b, 4a, 4b, 4c, 5a, 5b, 6a, 6b, 7a, 7b, 8a, 8b, 9a, 9b, and 10 are decomposition schematic diagrams 40 illustrating a semiconductor structure …
FIG. 2, before the channel layer 23 is grown, a nucleation layer 21 and a buffer layer 22 may also be sequentially grown on the substrate 1. Taking a GaN-based …
FIG. 3a, preparing a p-type GaN-based semiconductor layer 5 above the semiconductor layer 3, an upper surface of the p-type GaN-based semicon- ductor layer 5 …
FIG. 4a, etching the p-type GaN- based semiconductor layer 5 selectively, and reserving only a portion of the p-type GaN-based semiconductor layer …
FIG. 5a, preparing a gate electrode 51, a source electrode 6, and a drain electrode 7. The gate electrode 51 is prepared on the p-type semicon- ductor layer 5, …
FIG. 6a, in order to further improve the performance of the 5 semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
FIGS. 7a and 7b, 15 the p-type GaN-based semiconductor layer 5 is prepared above the barrier layer 24. Then, as shown in
FIGS. 8a and 8b, the p-type GaN-based semiconductor layer 5 is selec- tively etched, and only the p-type GaN-based semiconductor layer 5 in the gate region is …
FIG. 9a, in order to further improve the performance of the semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
FIG. 10, when the semiconductor structure includes the groove 4, the barrier layer 24 may also adopt a sandwich structure. The sandwich structure includes a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: 15 a substrate; a channel layer, a barrier layer and a semiconductor layer sequentially superimposed on the substrate, wherein the semiconductor layer is made of a GaN-based mate-rial and an upper surface of the semiconductor layer is Ga-face; and a p-type GaN-based semiconductor layer, with N-face as an upper surface, formed in a gate region of the semiconductor layer, wherein the barrier layer comprises a first outer interlayer AlGaN, an intermediate layer GaN and a second outer interlayer AlGaN that are sequentially stacked on a surface of the channel layer.
The semiconductor structure according to claim 1, further comprising: 30 a gate electrode disposed on the p-type GaN-based semiconductor layer; a source electrode disposed in a source region of the barrier layer; and a drain electrode disposed in a drain region of the barrier layer.
The semiconductor structure according to claim 1, further comprising: a nucleation layer between the channel layer and the substrate; and 40 a buffer layer between the nucleation layer and the chan-nel layer.
The semiconductor structure according to claim 1, wherein the p-type GaN-based semiconductor layer com-prises a multilayer structure or a superlattice structure com-prising one or more materials of p-type AlGaN, p-type GaN, and p-type InGaN.
The semiconductor structure according to claim 1, further comprising a groove disposed in the gate region of the semiconductor layer, wherein the groove penetrates the semiconductor layer and stops on the barrier layer or par-tially penetrates the barrier layer and stops in the barrier layer.
The semiconductor structure according to claim 1, wherein the semiconductor structure further comprises a polarity reversal layer Al₂O₃ disposed between the semicon-ductor layer and the p-type GaN-based semiconductor layer with the N-face as the upper surface, and the p-type GaN-based semiconductor layer with the N-face as the upper surface is formed by reversing a p-type Ga-face GaN-based material by the polarity reversal layer Al₂O3.
The semiconductor structure according to claim 1, wherein the semiconductor layer comprises a first portion located outside the gate region and a second portion B₂ located within the gate region, and a thickness of the first portion is less than a thickness of the second portion.
A manufacturing method for a semiconductor structure, comprising: preparing a channel layer, a barrier layer and a semicon-ductor layer sequentially superimposed on a substrate, wherein the semiconductor layer is made of a GaN-based material and an upper surface of the semicon-ductor layer is Ga-face; and preparing a p-type GaN-based semiconductor layer with N-face as an upper surface above the semiconductor layer, wherein the barrier layer comprises a first outer interlayer AlGaN, an intermediate layer GaN and a second outer interlayer AlGaN that are sequentially stacked on a surface of the channel layer.
The manufacturing method for the semiconductor structure according to claim 9, wherein the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, comprises: preparing a p-type Ga-face GaN-based material above the semiconductor layer, and doping a polarity reversal element in the p-type Ga-face GaN-based material to reverse the p-type Ga-face GaN-based material to the p-type GaN-based semiconductor layer with the N-face as the upper surface.
The manufacturing method for the semiconductor structure according to claim 9, wherein the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, comprises: preparing a p-type Ga-face GaN-based material above the semiconductor layer; and reversing the p-type Ga-face GaN-based material by a polarity reversal layer to the p-type GaN-based semiconductor layer with the N-face as the upper surface.
The manufacturing method for the semiconductor structure according to claim 9, wherein the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, comprises: bonding the p-type GaN-based semiconductor layer with the N-face as the upper surface to the semiconductor layer directly.
The manufacturing method for the semiconductor structure according to claim 9, further comprising: etching the p-type GaN-based semiconductor layer selec-tively, and reserving only a portion of the p-type GaN-based semiconductor layer corresponding to a gate region.
The manufacturing method for the semiconductor structure according to claim 9, further comprising: preparing a gate electrode on the p-type GaN-based semiconductor layer, preparing a source electrode in a source region of the barrier layer, and preparing a drain electrode in a drain region of the barrier layer.
The manufacturing method for the semiconductor structure according to claim 9, further comprising: forming a nucleation layer and a buffer layer on the substrate sequentially before forming the channel layer.
The manufacturing method for the semiconductor structure according to claim 9, before the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, further comprising: 11 12 preparing a groove in a gate region of the semiconductor layer, wherein the groove penetrates the semiconductor layer and stops on the barrier layer or partially pen-etrates the barrier layer and stops in the barrier layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
p-GaN gate HEMT (enhancement-mode GaN transistor)
Materials described outside the worked examples.
GaN-based semiconductor layer (Ga-face)
AlGaN (first outer interlayer/second outer interlayer)
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 6a, in order to further improve the performance of the 5 semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 40 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 11
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,080,786 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1a, 2, 3a, 3b, 4a, 4b, 4c, 5a, 5b, 6a, 6b, 7a, 7b, 8a, 8b, 9a, 9b, and 10 are decomposition schematic diagrams 40 illustrating a semiconductor structure …
FIG. 2, before the channel layer 23 is grown, a nucleation layer 21 and a buffer layer 22 may also be sequentially grown on the substrate 1. Taking a GaN-based …
FIG. 3a, preparing a p-type GaN-based semiconductor layer 5 above the semiconductor layer 3, an upper surface of the p-type GaN-based semicon- ductor layer 5 …
FIG. 4a, etching the p-type GaN- based semiconductor layer 5 selectively, and reserving only a portion of the p-type GaN-based semiconductor layer …
FIG. 5a, preparing a gate electrode 51, a source electrode 6, and a drain electrode 7. The gate electrode 51 is prepared on the p-type semicon- ductor layer 5, …
FIG. 6a, in order to further improve the performance of the 5 semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
FIGS. 7a and 7b, 15 the p-type GaN-based semiconductor layer 5 is prepared above the barrier layer 24. Then, as shown in
FIGS. 8a and 8b, the p-type GaN-based semiconductor layer 5 is selec- tively etched, and only the p-type GaN-based semiconductor layer 5 in the gate region is …
FIG. 9a, in order to further improve the performance of the semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
FIG. 10, when the semiconductor structure includes the groove 4, the barrier layer 24 may also adopt a sandwich structure. The sandwich structure includes a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: 15 a substrate; a channel layer, a barrier layer and a semiconductor layer sequentially superimposed on the substrate, wherein the semiconductor layer is made of a GaN-based mate-rial and an upper surface of the semiconductor layer is Ga-face; and a p-type GaN-based semiconductor layer, with N-face as an upper surface, formed in a gate region of the semiconductor layer, wherein the barrier layer comprises a first outer interlayer AlGaN, an intermediate layer GaN and a second outer interlayer AlGaN that are sequentially stacked on a surface of the channel layer.
The semiconductor structure according to claim 1, further comprising: 30 a gate electrode disposed on the p-type GaN-based semiconductor layer; a source electrode disposed in a source region of the barrier layer; and a drain electrode disposed in a drain region of the barrier layer.
The semiconductor structure according to claim 1, further comprising: a nucleation layer between the channel layer and the substrate; and 40 a buffer layer between the nucleation layer and the chan-nel layer.
The semiconductor structure according to claim 1, wherein the p-type GaN-based semiconductor layer com-prises a multilayer structure or a superlattice structure com-prising one or more materials of p-type AlGaN, p-type GaN, and p-type InGaN.
The semiconductor structure according to claim 1, further comprising a groove disposed in the gate region of the semiconductor layer, wherein the groove penetrates the semiconductor layer and stops on the barrier layer or par-tially penetrates the barrier layer and stops in the barrier layer.
The semiconductor structure according to claim 1, wherein the semiconductor structure further comprises a polarity reversal layer Al₂O₃ disposed between the semicon-ductor layer and the p-type GaN-based semiconductor layer with the N-face as the upper surface, and the p-type GaN-based semiconductor layer with the N-face as the upper surface is formed by reversing a p-type Ga-face GaN-based material by the polarity reversal layer Al₂O3.
The semiconductor structure according to claim 1, wherein the semiconductor layer comprises a first portion located outside the gate region and a second portion B₂ located within the gate region, and a thickness of the first portion is less than a thickness of the second portion.
A manufacturing method for a semiconductor structure, comprising: preparing a channel layer, a barrier layer and a semicon-ductor layer sequentially superimposed on a substrate, wherein the semiconductor layer is made of a GaN-based material and an upper surface of the semicon-ductor layer is Ga-face; and preparing a p-type GaN-based semiconductor layer with N-face as an upper surface above the semiconductor layer, wherein the barrier layer comprises a first outer interlayer AlGaN, an intermediate layer GaN and a second outer interlayer AlGaN that are sequentially stacked on a surface of the channel layer.
The manufacturing method for the semiconductor structure according to claim 9, wherein the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, comprises: preparing a p-type Ga-face GaN-based material above the semiconductor layer, and doping a polarity reversal element in the p-type Ga-face GaN-based material to reverse the p-type Ga-face GaN-based material to the p-type GaN-based semiconductor layer with the N-face as the upper surface.
The manufacturing method for the semiconductor structure according to claim 9, wherein the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, comprises: preparing a p-type Ga-face GaN-based material above the semiconductor layer; and reversing the p-type Ga-face GaN-based material by a polarity reversal layer to the p-type GaN-based semiconductor layer with the N-face as the upper surface.
The manufacturing method for the semiconductor structure according to claim 9, wherein the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, comprises: bonding the p-type GaN-based semiconductor layer with the N-face as the upper surface to the semiconductor layer directly.
The manufacturing method for the semiconductor structure according to claim 9, further comprising: etching the p-type GaN-based semiconductor layer selec-tively, and reserving only a portion of the p-type GaN-based semiconductor layer corresponding to a gate region.
The manufacturing method for the semiconductor structure according to claim 9, further comprising: preparing a gate electrode on the p-type GaN-based semiconductor layer, preparing a source electrode in a source region of the barrier layer, and preparing a drain electrode in a drain region of the barrier layer.
The manufacturing method for the semiconductor structure according to claim 9, further comprising: forming a nucleation layer and a buffer layer on the substrate sequentially before forming the channel layer.
The manufacturing method for the semiconductor structure according to claim 9, before the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, further comprising: 11 12 preparing a groove in a gate region of the semiconductor layer, wherein the groove penetrates the semiconductor layer and stops on the barrier layer or partially pen-etrates the barrier layer and stops in the barrier layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
p-GaN gate HEMT (enhancement-mode GaN transistor)
Materials described outside the worked examples.
GaN-based semiconductor layer (Ga-face)
AlGaN (first outer interlayer/second outer interlayer)
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 6a, in order to further improve the performance of the 5 semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 40 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 11
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,080,786 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1a, 2, 3a, 3b, 4a, 4b, 4c, 5a, 5b, 6a, 6b, 7a, 7b, 8a, 8b, 9a, 9b, and 10 are decomposition schematic diagrams 40 illustrating a semiconductor structure …
FIG. 2, before the channel layer 23 is grown, a nucleation layer 21 and a buffer layer 22 may also be sequentially grown on the substrate 1. Taking a GaN-based …
FIG. 3a, preparing a p-type GaN-based semiconductor layer 5 above the semiconductor layer 3, an upper surface of the p-type GaN-based semicon- ductor layer 5 …
FIG. 4a, etching the p-type GaN- based semiconductor layer 5 selectively, and reserving only a portion of the p-type GaN-based semiconductor layer …
FIG. 5a, preparing a gate electrode 51, a source electrode 6, and a drain electrode 7. The gate electrode 51 is prepared on the p-type semicon- ductor layer 5, …
FIG. 6a, in order to further improve the performance of the 5 semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
FIGS. 7a and 7b, 15 the p-type GaN-based semiconductor layer 5 is prepared above the barrier layer 24. Then, as shown in
FIGS. 8a and 8b, the p-type GaN-based semiconductor layer 5 is selec- tively etched, and only the p-type GaN-based semiconductor layer 5 in the gate region is …
FIG. 9a, in order to further improve the performance of the semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
FIG. 10, when the semiconductor structure includes the groove 4, the barrier layer 24 may also adopt a sandwich structure. The sandwich structure includes a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: 15 a substrate; a channel layer, a barrier layer and a semiconductor layer sequentially superimposed on the substrate, wherein the semiconductor layer is made of a GaN-based mate-rial and an upper surface of the semiconductor layer is Ga-face; and a p-type GaN-based semiconductor layer, with N-face as an upper surface, formed in a gate region of the semiconductor layer, wherein the barrier layer comprises a first outer interlayer AlGaN, an intermediate layer GaN and a second outer interlayer AlGaN that are sequentially stacked on a surface of the channel layer.
The semiconductor structure according to claim 1, further comprising: 30 a gate electrode disposed on the p-type GaN-based semiconductor layer; a source electrode disposed in a source region of the barrier layer; and a drain electrode disposed in a drain region of the barrier layer.
The semiconductor structure according to claim 1, further comprising: a nucleation layer between the channel layer and the substrate; and 40 a buffer layer between the nucleation layer and the chan-nel layer.
The semiconductor structure according to claim 1, wherein the p-type GaN-based semiconductor layer com-prises a multilayer structure or a superlattice structure com-prising one or more materials of p-type AlGaN, p-type GaN, and p-type InGaN.
The semiconductor structure according to claim 1, further comprising a groove disposed in the gate region of the semiconductor layer, wherein the groove penetrates the semiconductor layer and stops on the barrier layer or par-tially penetrates the barrier layer and stops in the barrier layer.
The semiconductor structure according to claim 1, wherein the semiconductor structure further comprises a polarity reversal layer Al₂O₃ disposed between the semicon-ductor layer and the p-type GaN-based semiconductor layer with the N-face as the upper surface, and the p-type GaN-based semiconductor layer with the N-face as the upper surface is formed by reversing a p-type Ga-face GaN-based material by the polarity reversal layer Al₂O3.
The semiconductor structure according to claim 1, wherein the semiconductor layer comprises a first portion located outside the gate region and a second portion B₂ located within the gate region, and a thickness of the first portion is less than a thickness of the second portion.
A manufacturing method for a semiconductor structure, comprising: preparing a channel layer, a barrier layer and a semicon-ductor layer sequentially superimposed on a substrate, wherein the semiconductor layer is made of a GaN-based material and an upper surface of the semicon-ductor layer is Ga-face; and preparing a p-type GaN-based semiconductor layer with N-face as an upper surface above the semiconductor layer, wherein the barrier layer comprises a first outer interlayer AlGaN, an intermediate layer GaN and a second outer interlayer AlGaN that are sequentially stacked on a surface of the channel layer.
The manufacturing method for the semiconductor structure according to claim 9, wherein the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, comprises: preparing a p-type Ga-face GaN-based material above the semiconductor layer, and doping a polarity reversal element in the p-type Ga-face GaN-based material to reverse the p-type Ga-face GaN-based material to the p-type GaN-based semiconductor layer with the N-face as the upper surface.
The manufacturing method for the semiconductor structure according to claim 9, wherein the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, comprises: preparing a p-type Ga-face GaN-based material above the semiconductor layer; and reversing the p-type Ga-face GaN-based material by a polarity reversal layer to the p-type GaN-based semiconductor layer with the N-face as the upper surface.
The manufacturing method for the semiconductor structure according to claim 9, wherein the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, comprises: bonding the p-type GaN-based semiconductor layer with the N-face as the upper surface to the semiconductor layer directly.
The manufacturing method for the semiconductor structure according to claim 9, further comprising: etching the p-type GaN-based semiconductor layer selec-tively, and reserving only a portion of the p-type GaN-based semiconductor layer corresponding to a gate region.
The manufacturing method for the semiconductor structure according to claim 9, further comprising: preparing a gate electrode on the p-type GaN-based semiconductor layer, preparing a source electrode in a source region of the barrier layer, and preparing a drain electrode in a drain region of the barrier layer.
The manufacturing method for the semiconductor structure according to claim 9, further comprising: forming a nucleation layer and a buffer layer on the substrate sequentially before forming the channel layer.
The manufacturing method for the semiconductor structure according to claim 9, before the preparing the p-type GaN-based semiconductor layer with the N-face as the upper surface above the semiconductor layer, further comprising: 11 12 preparing a groove in a gate region of the semiconductor layer, wherein the groove penetrates the semiconductor layer and stops on the barrier layer or partially pen-etrates the barrier layer and stops in the barrier layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
p-GaN gate HEMT (enhancement-mode GaN transistor)
Materials described outside the worked examples.
GaN-based semiconductor layer (Ga-face)
AlGaN (first outer interlayer/second outer interlayer)
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 6a, in order to further improve the performance of the 5 semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 40 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 11
Related documents with shared materials, methods, properties, or citations.
GaN (intermediate layer of barrier)
GaN
p-type GaN-based semiconductor layer (N-face)
p-type InGaN
InGaN
polarity reversal layer Al₂O₃
Al₂O₃
Mg (polarity reversal dopant)
Mg
substrate
FIG. 9a, in order to further improve the performance of the semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
| — |
Cited non-patent literature · 2
GaN (intermediate layer of barrier)
GaN
p-type GaN-based semiconductor layer (N-face)
p-type InGaN
InGaN
polarity reversal layer Al₂O₃
Al₂O₃
Mg (polarity reversal dopant)
Mg
substrate
FIG. 9a, in order to further improve the performance of the semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
| — |
Cited non-patent literature · 2
GaN (intermediate layer of barrier)
GaN
p-type GaN-based semiconductor layer (N-face)
p-type InGaN
InGaN
polarity reversal layer Al₂O₃
Al₂O₃
Mg (polarity reversal dopant)
Mg
substrate
FIG. 9a, in order to further improve the performance of the semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
| — |
Cited non-patent literature · 2
GaN (intermediate layer of barrier)
GaN
p-type GaN-based semiconductor layer (N-face)
p-type InGaN
InGaN
polarity reversal layer Al₂O₃
Al₂O₃
Mg (polarity reversal dopant)
Mg
substrate
FIG. 9a, in order to further improve the performance of the semiconductor structure and further reduce the two-dimen- sional electron gas density in the …
| — |
Cited non-patent literature · 2
