Patent
Atlas literature
Patent
US 12,266,523 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic cross-sectional diagram 40 of a semiconductor structure in accordance with embodi- ments; and
FIGS. 2-10 illustrate a process for making a semiconduc- tor structure, in accordance with embodiments.
FIG. 3, a masking layer such as a silicon nitride masking layer 110 is formed on the top surface of the silicon substrate 20. The silicon nitride masking layer …
FIG. 4, the silicon nitride masking layer 110 is patterned using conventional patterning techniques. For example, a mask defining areas of the silicon nitride …
FIG. 5, an etching step is performed on the substrate 20 partially covered by the patterned silicon nitride layer 110. The etching process removes portions of …
FIG. 6, a thermal oxidation step is performed on the substrate 20 masked by portions 120 and 122 of silicon nitride layer 110. The thermal oxidation step …
FIG. 7, the silicon nitride layer 110 is stripped from the surface of silicon substrate 20 by etching. The silicon nitride masking layer is removed via …
FIG. 8, an epitaxial growth step is performed. In particular, the gallium nitride layer 22 or other III-nitride material layer is formed on the top surface of …
FIG. 9, devices 30 and 32 are fabricated in device areas 50, and interconnects 40, 42 and 44 are fabri- cated in interconnect areas 52. The devices 30 and 32 …
FIG. 10, the silicon substrate 20 is reduced in thickness by thinning of the back side. The GaN on silicon wafers are mounted front side down onto a carrier …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for making a semiconductor structure, com-prising: forming a trench in an interconnect area of a substrate between a first device area in the semiconductor struc-ture and a second device area in the semiconductor structure; forming a low dielectric constant material region in the trench, a dielectric constant of the low dielectric con-stant material region being lower than a dielectric constant of the substrate; forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench; forming a first device in the III-nitride material layer in the first device area; forming a second device in the III-nitride material layer in the second device area; and forming an interconnect over the low dielectric constant material region, the interconnect comprising a continu-ous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.
The method according to claim 1, wherein forming the low dielectric constant material region in the trench com-prises oxidizing the substrate in the trench.
The method according to claim 1, wherein: the substrate comprises a silicon substrate; and forming the low dielectric constant material region in the trench comprises oxidizing the silicon substrate in the trench to form a silicon dioxide region in the trench.
The method according to claim 1, wherein forming the interconnect comprises forming a mask layer on the substrate and patterning the mask layer by removing at least a portion of the mask layer in the interconnect area.
The method according to claim 1, wherein forming the III-nitride material layer comprises epitaxial growth of a gallium nitride layer over the substrate and over the low dielectric constant material region in the trench.
The method according to claim 1, further comprising thinning a back side of the substrate.
The method according to claim 1, further comprising forming a metal layer on a back side of the substrate.
The method according to claim 1, wherein the first device comprises a transistor and the second device com-prises a diode.
The method according to claim 1, wherein the III-nitride material layer comprises: single crystal gallium nitride over the substrate in the first device area and in the second device area; and polycrystalline gallium nitride over the low dielectric constant material region.
The method according to claim 1, further comprising forming at least one of a diffusion barrier layer, a nucleation layer, or a buffer layer over the substrate in the first device area.
The method according to claim 1, wherein the low dielectric constant material region reduces parasitic capaci-B₂ tance between the interconnect and a layer on a back side of the substrate, as compared to a semiconductor structure in which the low dielectric constant material region is not in the substrate.
A method for making a semiconductor structure, comprising: forming a trench in a substrate between a first device area in the semiconductor structure and a second device area in the semiconductor structure; oxidizing the substrate in the trench; forming a III-nitride material layer over the substrate and over an oxide region in the trench; forming a first device in the first device area; forming a second device in the second device area; and forming an interconnect over the oxide region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the oxide region, and to the second device area.
The method as defined in claim 17, further comprising planarizing the substrate and the oxide region before form-ing the III-nitride material layer.
The method according to claim 17, wherein: the substrate comprises a silicon substrate; and oxidizing the substrate in the trench comprises oxidizing the silicon substrate in the trench to form a silicon dioxide region in the trench.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-silicon semiconductor structure with low-k interconnect region
transistor (first device)
Materials described outside the worked examples.
low dielectric constant material
III-nitride material layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 10, the silicon substrate 20 is reduced in thickness by thinning of the back side. The GaN on silicon wafers are mounted front side down onto a carrier …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
dielectric constant of silicon | 11.65 | Si |
dielectric constant of silicon dioxide |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 51
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,266,523 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic cross-sectional diagram 40 of a semiconductor structure in accordance with embodi- ments; and
FIGS. 2-10 illustrate a process for making a semiconduc- tor structure, in accordance with embodiments.
FIG. 3, a masking layer such as a silicon nitride masking layer 110 is formed on the top surface of the silicon substrate 20. The silicon nitride masking layer …
FIG. 4, the silicon nitride masking layer 110 is patterned using conventional patterning techniques. For example, a mask defining areas of the silicon nitride …
FIG. 5, an etching step is performed on the substrate 20 partially covered by the patterned silicon nitride layer 110. The etching process removes portions of …
FIG. 6, a thermal oxidation step is performed on the substrate 20 masked by portions 120 and 122 of silicon nitride layer 110. The thermal oxidation step …
FIG. 7, the silicon nitride layer 110 is stripped from the surface of silicon substrate 20 by etching. The silicon nitride masking layer is removed via …
FIG. 8, an epitaxial growth step is performed. In particular, the gallium nitride layer 22 or other III-nitride material layer is formed on the top surface of …
FIG. 9, devices 30 and 32 are fabricated in device areas 50, and interconnects 40, 42 and 44 are fabri- cated in interconnect areas 52. The devices 30 and 32 …
FIG. 10, the silicon substrate 20 is reduced in thickness by thinning of the back side. The GaN on silicon wafers are mounted front side down onto a carrier …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for making a semiconductor structure, com-prising: forming a trench in an interconnect area of a substrate between a first device area in the semiconductor struc-ture and a second device area in the semiconductor structure; forming a low dielectric constant material region in the trench, a dielectric constant of the low dielectric con-stant material region being lower than a dielectric constant of the substrate; forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench; forming a first device in the III-nitride material layer in the first device area; forming a second device in the III-nitride material layer in the second device area; and forming an interconnect over the low dielectric constant material region, the interconnect comprising a continu-ous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.
The method according to claim 1, wherein forming the low dielectric constant material region in the trench com-prises oxidizing the substrate in the trench.
The method according to claim 1, wherein: the substrate comprises a silicon substrate; and forming the low dielectric constant material region in the trench comprises oxidizing the silicon substrate in the trench to form a silicon dioxide region in the trench.
The method according to claim 1, wherein forming the interconnect comprises forming a mask layer on the substrate and patterning the mask layer by removing at least a portion of the mask layer in the interconnect area.
The method according to claim 1, wherein forming the III-nitride material layer comprises epitaxial growth of a gallium nitride layer over the substrate and over the low dielectric constant material region in the trench.
The method according to claim 1, further comprising thinning a back side of the substrate.
The method according to claim 1, further comprising forming a metal layer on a back side of the substrate.
The method according to claim 1, wherein the first device comprises a transistor and the second device com-prises a diode.
The method according to claim 1, wherein the III-nitride material layer comprises: single crystal gallium nitride over the substrate in the first device area and in the second device area; and polycrystalline gallium nitride over the low dielectric constant material region.
The method according to claim 1, further comprising forming at least one of a diffusion barrier layer, a nucleation layer, or a buffer layer over the substrate in the first device area.
The method according to claim 1, wherein the low dielectric constant material region reduces parasitic capaci-B₂ tance between the interconnect and a layer on a back side of the substrate, as compared to a semiconductor structure in which the low dielectric constant material region is not in the substrate.
A method for making a semiconductor structure, comprising: forming a trench in a substrate between a first device area in the semiconductor structure and a second device area in the semiconductor structure; oxidizing the substrate in the trench; forming a III-nitride material layer over the substrate and over an oxide region in the trench; forming a first device in the first device area; forming a second device in the second device area; and forming an interconnect over the oxide region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the oxide region, and to the second device area.
The method as defined in claim 17, further comprising planarizing the substrate and the oxide region before form-ing the III-nitride material layer.
The method according to claim 17, wherein: the substrate comprises a silicon substrate; and oxidizing the substrate in the trench comprises oxidizing the silicon substrate in the trench to form a silicon dioxide region in the trench.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-silicon semiconductor structure with low-k interconnect region
transistor (first device)
Materials described outside the worked examples.
low dielectric constant material
III-nitride material layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 10, the silicon substrate 20 is reduced in thickness by thinning of the back side. The GaN on silicon wafers are mounted front side down onto a carrier …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
dielectric constant of silicon | 11.65 | Si |
dielectric constant of silicon dioxide |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 51
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,266,523 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic cross-sectional diagram 40 of a semiconductor structure in accordance with embodi- ments; and
FIGS. 2-10 illustrate a process for making a semiconduc- tor structure, in accordance with embodiments.
FIG. 3, a masking layer such as a silicon nitride masking layer 110 is formed on the top surface of the silicon substrate 20. The silicon nitride masking layer …
FIG. 4, the silicon nitride masking layer 110 is patterned using conventional patterning techniques. For example, a mask defining areas of the silicon nitride …
FIG. 5, an etching step is performed on the substrate 20 partially covered by the patterned silicon nitride layer 110. The etching process removes portions of …
FIG. 6, a thermal oxidation step is performed on the substrate 20 masked by portions 120 and 122 of silicon nitride layer 110. The thermal oxidation step …
FIG. 7, the silicon nitride layer 110 is stripped from the surface of silicon substrate 20 by etching. The silicon nitride masking layer is removed via …
FIG. 8, an epitaxial growth step is performed. In particular, the gallium nitride layer 22 or other III-nitride material layer is formed on the top surface of …
FIG. 9, devices 30 and 32 are fabricated in device areas 50, and interconnects 40, 42 and 44 are fabri- cated in interconnect areas 52. The devices 30 and 32 …
FIG. 10, the silicon substrate 20 is reduced in thickness by thinning of the back side. The GaN on silicon wafers are mounted front side down onto a carrier …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for making a semiconductor structure, com-prising: forming a trench in an interconnect area of a substrate between a first device area in the semiconductor struc-ture and a second device area in the semiconductor structure; forming a low dielectric constant material region in the trench, a dielectric constant of the low dielectric con-stant material region being lower than a dielectric constant of the substrate; forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench; forming a first device in the III-nitride material layer in the first device area; forming a second device in the III-nitride material layer in the second device area; and forming an interconnect over the low dielectric constant material region, the interconnect comprising a continu-ous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.
The method according to claim 1, wherein forming the low dielectric constant material region in the trench com-prises oxidizing the substrate in the trench.
The method according to claim 1, wherein: the substrate comprises a silicon substrate; and forming the low dielectric constant material region in the trench comprises oxidizing the silicon substrate in the trench to form a silicon dioxide region in the trench.
The method according to claim 1, wherein forming the interconnect comprises forming a mask layer on the substrate and patterning the mask layer by removing at least a portion of the mask layer in the interconnect area.
The method according to claim 1, wherein forming the III-nitride material layer comprises epitaxial growth of a gallium nitride layer over the substrate and over the low dielectric constant material region in the trench.
The method according to claim 1, further comprising thinning a back side of the substrate.
The method according to claim 1, further comprising forming a metal layer on a back side of the substrate.
The method according to claim 1, wherein the first device comprises a transistor and the second device com-prises a diode.
The method according to claim 1, wherein the III-nitride material layer comprises: single crystal gallium nitride over the substrate in the first device area and in the second device area; and polycrystalline gallium nitride over the low dielectric constant material region.
The method according to claim 1, further comprising forming at least one of a diffusion barrier layer, a nucleation layer, or a buffer layer over the substrate in the first device area.
The method according to claim 1, wherein the low dielectric constant material region reduces parasitic capaci-B₂ tance between the interconnect and a layer on a back side of the substrate, as compared to a semiconductor structure in which the low dielectric constant material region is not in the substrate.
A method for making a semiconductor structure, comprising: forming a trench in a substrate between a first device area in the semiconductor structure and a second device area in the semiconductor structure; oxidizing the substrate in the trench; forming a III-nitride material layer over the substrate and over an oxide region in the trench; forming a first device in the first device area; forming a second device in the second device area; and forming an interconnect over the oxide region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the oxide region, and to the second device area.
The method as defined in claim 17, further comprising planarizing the substrate and the oxide region before form-ing the III-nitride material layer.
The method according to claim 17, wherein: the substrate comprises a silicon substrate; and oxidizing the substrate in the trench comprises oxidizing the silicon substrate in the trench to form a silicon dioxide region in the trench.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-silicon semiconductor structure with low-k interconnect region
transistor (first device)
Materials described outside the worked examples.
low dielectric constant material
III-nitride material layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 10, the silicon substrate 20 is reduced in thickness by thinning of the back side. The GaN on silicon wafers are mounted front side down onto a carrier …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
dielectric constant of silicon | 11.65 | Si |
dielectric constant of silicon dioxide |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 51
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,266,523 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic cross-sectional diagram 40 of a semiconductor structure in accordance with embodi- ments; and
FIGS. 2-10 illustrate a process for making a semiconduc- tor structure, in accordance with embodiments.
FIG. 3, a masking layer such as a silicon nitride masking layer 110 is formed on the top surface of the silicon substrate 20. The silicon nitride masking layer …
FIG. 4, the silicon nitride masking layer 110 is patterned using conventional patterning techniques. For example, a mask defining areas of the silicon nitride …
FIG. 5, an etching step is performed on the substrate 20 partially covered by the patterned silicon nitride layer 110. The etching process removes portions of …
FIG. 6, a thermal oxidation step is performed on the substrate 20 masked by portions 120 and 122 of silicon nitride layer 110. The thermal oxidation step …
FIG. 7, the silicon nitride layer 110 is stripped from the surface of silicon substrate 20 by etching. The silicon nitride masking layer is removed via …
FIG. 8, an epitaxial growth step is performed. In particular, the gallium nitride layer 22 or other III-nitride material layer is formed on the top surface of …
FIG. 9, devices 30 and 32 are fabricated in device areas 50, and interconnects 40, 42 and 44 are fabri- cated in interconnect areas 52. The devices 30 and 32 …
FIG. 10, the silicon substrate 20 is reduced in thickness by thinning of the back side. The GaN on silicon wafers are mounted front side down onto a carrier …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for making a semiconductor structure, com-prising: forming a trench in an interconnect area of a substrate between a first device area in the semiconductor struc-ture and a second device area in the semiconductor structure; forming a low dielectric constant material region in the trench, a dielectric constant of the low dielectric con-stant material region being lower than a dielectric constant of the substrate; forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench; forming a first device in the III-nitride material layer in the first device area; forming a second device in the III-nitride material layer in the second device area; and forming an interconnect over the low dielectric constant material region, the interconnect comprising a continu-ous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.
The method according to claim 1, wherein forming the low dielectric constant material region in the trench com-prises oxidizing the substrate in the trench.
The method according to claim 1, wherein: the substrate comprises a silicon substrate; and forming the low dielectric constant material region in the trench comprises oxidizing the silicon substrate in the trench to form a silicon dioxide region in the trench.
The method according to claim 1, wherein forming the interconnect comprises forming a mask layer on the substrate and patterning the mask layer by removing at least a portion of the mask layer in the interconnect area.
The method according to claim 1, wherein forming the III-nitride material layer comprises epitaxial growth of a gallium nitride layer over the substrate and over the low dielectric constant material region in the trench.
The method according to claim 1, further comprising thinning a back side of the substrate.
The method according to claim 1, further comprising forming a metal layer on a back side of the substrate.
The method according to claim 1, wherein the first device comprises a transistor and the second device com-prises a diode.
The method according to claim 1, wherein the III-nitride material layer comprises: single crystal gallium nitride over the substrate in the first device area and in the second device area; and polycrystalline gallium nitride over the low dielectric constant material region.
The method according to claim 1, further comprising forming at least one of a diffusion barrier layer, a nucleation layer, or a buffer layer over the substrate in the first device area.
The method according to claim 1, wherein the low dielectric constant material region reduces parasitic capaci-B₂ tance between the interconnect and a layer on a back side of the substrate, as compared to a semiconductor structure in which the low dielectric constant material region is not in the substrate.
A method for making a semiconductor structure, comprising: forming a trench in a substrate between a first device area in the semiconductor structure and a second device area in the semiconductor structure; oxidizing the substrate in the trench; forming a III-nitride material layer over the substrate and over an oxide region in the trench; forming a first device in the first device area; forming a second device in the second device area; and forming an interconnect over the oxide region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the oxide region, and to the second device area.
The method as defined in claim 17, further comprising planarizing the substrate and the oxide region before form-ing the III-nitride material layer.
The method according to claim 17, wherein: the substrate comprises a silicon substrate; and oxidizing the substrate in the trench comprises oxidizing the silicon substrate in the trench to form a silicon dioxide region in the trench.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-silicon semiconductor structure with low-k interconnect region
transistor (first device)
Materials described outside the worked examples.
low dielectric constant material
III-nitride material layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 10, the silicon substrate 20 is reduced in thickness by thinning of the back side. The GaN on silicon wafers are mounted front side down onto a carrier …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
dielectric constant of silicon | 11.65 | Si |
dielectric constant of silicon dioxide |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 51
Related documents with shared materials, methods, properties, or citations.
diode (second device)
continuous conductive metal interconnect
silicon substrate
Si
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
single crystal gallium nitride
GaN
metal layer (ground plane)
| 3.9 |
SiO₂ |
Thickness | 500–1000 um | — |
Thickness | 2000–4000 Å | — |
Thickness | 0.8–6 um | — |
Thickness | 50–100 um | — |
Thickness | 1–6 um | — |
Thickness | ≤ 150 µm | — |
Thickness | ≤ 1 µm | — |
Cited non-patent literature · 4
diode (second device)
continuous conductive metal interconnect
silicon substrate
Si
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
single crystal gallium nitride
GaN
metal layer (ground plane)
| 3.9 |
SiO₂ |
Thickness | 500–1000 um | — |
Thickness | 2000–4000 Å | — |
Thickness | 0.8–6 um | — |
Thickness | 50–100 um | — |
Thickness | 1–6 um | — |
Thickness | ≤ 150 µm | — |
Thickness | ≤ 1 µm | — |
Cited non-patent literature · 4
diode (second device)
continuous conductive metal interconnect
silicon substrate
Si
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
single crystal gallium nitride
GaN
metal layer (ground plane)
| 3.9 |
SiO₂ |
Thickness | 500–1000 um | — |
Thickness | 2000–4000 Å | — |
Thickness | 0.8–6 um | — |
Thickness | 50–100 um | — |
Thickness | 1–6 um | — |
Thickness | ≤ 150 µm | — |
Thickness | ≤ 1 µm | — |
Cited non-patent literature · 4
diode (second device)
continuous conductive metal interconnect
silicon substrate
Si
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
single crystal gallium nitride
GaN
metal layer (ground plane)
| 3.9 |
SiO₂ |
Thickness | 500–1000 um | — |
Thickness | 2000–4000 Å | — |
Thickness | 0.8–6 um | — |
Thickness | 50–100 um | — |
Thickness | 1–6 um | — |
Thickness | ≤ 150 µm | — |
Thickness | ≤ 1 µm | — |
Cited non-patent literature · 4
