Patent
US 10,468,454GAN STACK ACOUSTIC REFLECTOR AND METHOD FOR PRODUCING THE SAME
Humberto CAMPANELLA-PINEDA
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 10,468,454Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 C schematically illustrates a top view showing the cut lines for FIG s. I A and 1B; [0016] FIG s. 2 through 13 schematically illustrate cross-sectional …
FIG. 2, an SOI wafer 200 is provided with a top Si layer 201 (device layer) having a [100], [111], or [110] crystal orientation (rotated 45 0 for a p-channel …
FIG. 3, a CMOS device 301, e.g., a field-effect transistor (F ET), is formed over a portion of the top Si layer 201. The CMOS device 301 may be a FET, a CMOS …
FIG. 4. The protect layer 401 may be formed from one or more layers, such as SiN or SiO 2; or it could be formed from a material such as Si or spin on glass, …
FIG. 5, a region 501 is opened over the [111] crystal orientation Si handle wafer 205 for the subsequent formation of a GaN stack (not shown for illustrative …
FIG. 6. The GaN stack 601 may be formed, e.g., of a buffer layer 603 including a GaN or AlGaN, a GaN channel layer 605, an AlGaN/AlN barrier 607, and a SiN …
FIG. 7, a GaN HEMT PA 701 including a gate electrode 703 and S/D electrodes 705 is formed on the GaN channel layer 605 and the AlGaN/A lN barrier 607 of the …
FIG. 8, an optional protect layer 801 is formed e.g., of one or more layers similar to the protect layer 401, over the GaN H EMT 701. A thin-film acoustic filter …
FIG. 9. [0043] Referring to
FIG. 10, the protective layer 901 is removed and a Si sacrificial (SAC) layer 1001 is formed, e.g., by chemical vapor deposition (CVD), plasma enhanced chemical …
FIG. 11, a thin-film encapsulation layer 1101 is formed, e.g., of oxide/nitride by deposition and optional planarization, over the [111] crystal orientation Si …
FIG. 12. Referring to FIG s. 14A, 14B, and 14C, a contact 1401 is formed, e.g., of Al, on the Mo or W layer 809 (top electrode) of the thin-film acoustic filter …
FIG. 13. A pad (not shown for illustrative convenience) may also be opened through the sealing layer 1301 and the encapsulation layer 1101 and an Al contact …
FIG. 14C schematically illustrates a top view showing the cut lines for FIG s. 14A and 14B, in accordance with an exemplary embodiment. Specifically,
FIG. 15 schematically illustrates a cross-sectional view of a resultant thin- film piezoelectric Lamb acoustic wave filter, a GaN-channel/buffer Bragg reflector, …
FIG. 16 schematically illustrates a cross-sectional view of a thin-film piezoelectric B AW filter, a GaN-channel/buffer Bragg reflector, an AlGaN/A lN barrier seed …
FIG. 17 schematically illustrates a cross-sectional view of a thin-film piezoelectric Lamb acoustic wave filter, GaN-channel/buffer Bragg reflector, and a …
FIG. 18 schematically illustrates a cross-sectional view of a thin-film piezoelectric B AW filter, a Si O 2/GaN-channel/buffer Bragg reflector, and a …
FIG. 19 schematically illustrates a cross-sectional view of a thin-film piezoelectric B AW filter, a SiN/GaN-channel/buffer Bragg reflector, and a monolithically …
FIG. 20 schematically illustrates a cross-sectional view of a thin-film piezoelectric Lamb acoustic wave filter, a SiN/Si₀ 2 barrier seed layer, and a …
FIG. 21C schematically illustrates a top view showing the cut lines for FIG s. 21A and 21B, in accordance with an exemplary embodiment. Referring to FIG s. …
FIG. 22C schematically illustrates a top view showing the cut lines for FIG s. 22A and 22B, in accordance with an exemplary embodiment. The resultant device of …
FIG. 23C schematically illustrates a top view showing the cut lines for FIG s. 23A and 23B, in accordance with an exemplary embodiment. The resultant device of …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: providing a silicon on insulator (SOI) wafer comprising a [l 1] crystal orientation silicon (Si) handle wafer, a buried oxide (BOX) layer, and a top Si layer; forming a complimentary metal-oxide semiconductor (CMOS) device over the top Si layer of the SO I wafer; [[and]] forming a Bragg reflector over the [1 I I] crystal orientation Si handle wafer, the Bragg reflector comprising a gallium nitride (GaN) stack with alternating layers of high/low acoustic impedance; forming a sacrificial (SAC) layer over and around the thin-film acoustic filter; forming an encapsulation layer over the SOI wafer; forming a via through the encapsulation layer on opposite sides of the thin-film acoustic filter; removing the SAC layer throu g h the via, a cavity formed over and around the thin-film acoustic filter; forming a sealing layer over the encapsulation layer; and forming a metal contact through the sealing layer and the encapsulation layer down to a portion of the thin-film acoustic filter. Currently amended
The method according to claim 1, comprising forming GaN stack by: forming a buffer layer over the [1 1] crystal orientation Si handle wafer; forming a GaN channel layer over the buffer layer; forming an AlGaN/A l N barrier layer over the GaN channel layer; and forming a silicon nitride (S i N) or silicon dioxide (SiO 2) passivation layer over the AlGaN/A l N barrier layer. Original
The method according to claim 1, further comprising forming a GaN high- electron-mobility transistor power amplifier (GaN H EMT PA) in and over respective portions of the GaN stack. Original
The method according to claim I, comprising forming the GaN stack by: forming a buffer layer over the [l II] crystal orientation Si handle wafer; forming a GaN channel layer over the buffer layer; and forming an aluminum gallium nitride (A I GaN)/aluminum nitride (A L N) barrier layer over the GaN channel layer. Original
The method according to claim 2, further comprising forming a thin-film acoustic filter over the GaN stack by: forming a first molybdenum (Mo) or tungsten (W) layer over the A I GaN/AIN barrier layer; forming an aluminum nitride (A I N), scandium aluminum nitride (ScA l N), zinc oxide (ZnO), lithium niobate (LiNbO 3), lithium tantalite (LiTaO 3), lead zirconate titanate (PZT), or polyvinylidene fluoride (PVDF) layer over the first Mo or W layer; forming a second Mo or W layer over the A l N, S cAl N, ZnO, LiNb O 3, LiTa G 3, PZT, or PVDF layer; forming a via through the first Mo or W layer and the GaN stack on opposite sides of the thin-film acoustic filter; and forming a cavity under the thin-film acoustic filter in the [111] crystal orientation Si handle wafer through the vias. Original
The method according to claim 2, further comprising forming a thin-film acoustic filter over the GaN stack by: forming an A I N, ScA L N, ZnO, LiNbO 3, L iTaO 3, PZT, or PVDF layer over the A l GaN/A iN barrier layer; forming a Mo or W layer over the A I N, S cAI N, ZnO, L i NbO 3, LiTaO 3, PZT, or PVDF layer; patterning the second Mo or W layer down to the A I N, S cAI N, ZnO, LiNb O 3, LiTa O 3, PZT, or PVDF layer; forming a via through the GaN stack on opposite sides of the thin-film acoustic filter; and forming a cavity under the thin-film acoustic filter in the [111] crystal orientation Si handle through the vias. Original
Canceled
A device comprising: a silicon on insulator (SOI) wafer, the SOI wafer comprising a [111] crystal orientation silicon (Si) handle wafer, a buried oxide (BOX) layer, and a top Si layer a complimentary metal-oxide-semiconductor (CMOS) device over the top Si layer; [[and]] a Bragg reflector over the [111] crystal orientation Si handle, the Bragg Reflector comprising a gallium nitride (GaN) stack with alternating layers of high/low acoustic impedance; and a GaN high-electron-mobility transistor power amplifier (GaN H EMT PA) in and over respective portions of the GaN stack. Currently amended
The device according to claim 10, wherein the GaN stack comprises: a buffer layer over the [111] crystal orientation Si handle wafer; a GaN channel layer over the buffer layer; and an aluminum gallium nitride (A l GaN)/aluminum nitride (A l N) barrier layer over the GaN channel layer. Original
The device according to claim 10, wherein the GaN stack comprises: a buffer layer over the [111] crystal orientation Si handle wafer; a GaN channel layer over the buffer layer; an A l GaN/A l N barrier layer over the GaN channel layer; and a silicon nitride (SiN) or silicon dioxide (SiO 2) passivation layer over the AlGaN/A l N barrier layer. Original
Canceled
The device according to claim [[10]] 12, further comprising: an encapsulation layer over the [111] crystal orientation Si handle wafer with a cavity over and around the thin-film acoustic filter; a sealing layer over the encapsulation layer; and a metal contact through the sealing layer and the encapsulation layer down to a portion of the thin-film acoustic filter. Currently amended
A device comprising: a silicon on insulator (SOI) wafer, the SOI wafer comprising a [111] crystal orientation silicon (Si) handle wafer, a buried oxide (BOX) layer, and a top Si layer; a complimentary metal-oxide-semiconductor (CMOS) device over the top Si; a gallium nitride (GaN) stack over the [111] crystal orientation Si handle; a GaN high-electron-mobility transistor power amplifier (GaN H EMT PA) in and over the GaN stack; a thin-film Lamb acoustic wave filter over the GaN stack; a via through the first Mo or W layer on opposite sides of the thin-film Lamb acoustic wave filter; and a cavity under the thin-film Lamb acoustic filter in a passivation layer of the GaN stack. Original
The device according to claim 19, wherein the GaN stack comprises: a buffer layer over the [111] crystal orientation Si handle wafer; a GaN channel layer over the buffer layer; an A l GaN/A l N barrier layer over the GaN channel layer; and the passivation layer of silicon nitride (SiN) or silicon dioxide (SiO 2) over the AlGaN/A lN barrier layer. Original
Layer stacks claimed or described, ordered top of device to substrate.
SOI wafer with GaN stack Bragg reflector and CMOS
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
silicon (Si) [111] crystal orientation handle wafer
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2, an SOI wafer 200 is provided with a top Si layer 201 (device layer) having a [100], [111], or [110] crystal orientation (rotated 45 0 for a p-channel …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN stack buffer layer thickness | 1.5 micrometer | GaN/AlGaN buffer layer |
GaN channel layer thickness |
Related documents with shared materials, methods, properties, or citations.
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Atlas literature
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US 10,468,454Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 C schematically illustrates a top view showing the cut lines for FIG s. I A and 1B; [0016] FIG s. 2 through 13 schematically illustrate cross-sectional …
FIG. 2, an SOI wafer 200 is provided with a top Si layer 201 (device layer) having a [100], [111], or [110] crystal orientation (rotated 45 0 for a p-channel …
FIG. 3, a CMOS device 301, e.g., a field-effect transistor (F ET), is formed over a portion of the top Si layer 201. The CMOS device 301 may be a FET, a CMOS …
FIG. 4. The protect layer 401 may be formed from one or more layers, such as SiN or SiO 2; or it could be formed from a material such as Si or spin on glass, …
FIG. 5, a region 501 is opened over the [111] crystal orientation Si handle wafer 205 for the subsequent formation of a GaN stack (not shown for illustrative …
FIG. 6. The GaN stack 601 may be formed, e.g., of a buffer layer 603 including a GaN or AlGaN, a GaN channel layer 605, an AlGaN/AlN barrier 607, and a SiN …
FIG. 7, a GaN HEMT PA 701 including a gate electrode 703 and S/D electrodes 705 is formed on the GaN channel layer 605 and the AlGaN/A lN barrier 607 of the …
FIG. 8, an optional protect layer 801 is formed e.g., of one or more layers similar to the protect layer 401, over the GaN H EMT 701. A thin-film acoustic filter …
FIG. 9. [0043] Referring to
FIG. 10, the protective layer 901 is removed and a Si sacrificial (SAC) layer 1001 is formed, e.g., by chemical vapor deposition (CVD), plasma enhanced chemical …
FIG. 11, a thin-film encapsulation layer 1101 is formed, e.g., of oxide/nitride by deposition and optional planarization, over the [111] crystal orientation Si …
FIG. 12. Referring to FIG s. 14A, 14B, and 14C, a contact 1401 is formed, e.g., of Al, on the Mo or W layer 809 (top electrode) of the thin-film acoustic filter …
FIG. 13. A pad (not shown for illustrative convenience) may also be opened through the sealing layer 1301 and the encapsulation layer 1101 and an Al contact …
FIG. 14C schematically illustrates a top view showing the cut lines for FIG s. 14A and 14B, in accordance with an exemplary embodiment. Specifically,
FIG. 15 schematically illustrates a cross-sectional view of a resultant thin- film piezoelectric Lamb acoustic wave filter, a GaN-channel/buffer Bragg reflector, …
FIG. 16 schematically illustrates a cross-sectional view of a thin-film piezoelectric B AW filter, a GaN-channel/buffer Bragg reflector, an AlGaN/A lN barrier seed …
FIG. 17 schematically illustrates a cross-sectional view of a thin-film piezoelectric Lamb acoustic wave filter, GaN-channel/buffer Bragg reflector, and a …
FIG. 18 schematically illustrates a cross-sectional view of a thin-film piezoelectric B AW filter, a Si O 2/GaN-channel/buffer Bragg reflector, and a …
FIG. 19 schematically illustrates a cross-sectional view of a thin-film piezoelectric B AW filter, a SiN/GaN-channel/buffer Bragg reflector, and a monolithically …
FIG. 20 schematically illustrates a cross-sectional view of a thin-film piezoelectric Lamb acoustic wave filter, a SiN/Si₀ 2 barrier seed layer, and a …
FIG. 21C schematically illustrates a top view showing the cut lines for FIG s. 21A and 21B, in accordance with an exemplary embodiment. Referring to FIG s. …
FIG. 22C schematically illustrates a top view showing the cut lines for FIG s. 22A and 22B, in accordance with an exemplary embodiment. The resultant device of …
FIG. 23C schematically illustrates a top view showing the cut lines for FIG s. 23A and 23B, in accordance with an exemplary embodiment. The resultant device of …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: providing a silicon on insulator (SOI) wafer comprising a [l 1] crystal orientation silicon (Si) handle wafer, a buried oxide (BOX) layer, and a top Si layer; forming a complimentary metal-oxide semiconductor (CMOS) device over the top Si layer of the SO I wafer; [[and]] forming a Bragg reflector over the [1 I I] crystal orientation Si handle wafer, the Bragg reflector comprising a gallium nitride (GaN) stack with alternating layers of high/low acoustic impedance; forming a sacrificial (SAC) layer over and around the thin-film acoustic filter; forming an encapsulation layer over the SOI wafer; forming a via through the encapsulation layer on opposite sides of the thin-film acoustic filter; removing the SAC layer throu g h the via, a cavity formed over and around the thin-film acoustic filter; forming a sealing layer over the encapsulation layer; and forming a metal contact through the sealing layer and the encapsulation layer down to a portion of the thin-film acoustic filter. Currently amended
The method according to claim 1, comprising forming GaN stack by: forming a buffer layer over the [1 1] crystal orientation Si handle wafer; forming a GaN channel layer over the buffer layer; forming an AlGaN/A l N barrier layer over the GaN channel layer; and forming a silicon nitride (S i N) or silicon dioxide (SiO 2) passivation layer over the AlGaN/A l N barrier layer. Original
The method according to claim 1, further comprising forming a GaN high- electron-mobility transistor power amplifier (GaN H EMT PA) in and over respective portions of the GaN stack. Original
The method according to claim I, comprising forming the GaN stack by: forming a buffer layer over the [l II] crystal orientation Si handle wafer; forming a GaN channel layer over the buffer layer; and forming an aluminum gallium nitride (A I GaN)/aluminum nitride (A L N) barrier layer over the GaN channel layer. Original
The method according to claim 2, further comprising forming a thin-film acoustic filter over the GaN stack by: forming a first molybdenum (Mo) or tungsten (W) layer over the A I GaN/AIN barrier layer; forming an aluminum nitride (A I N), scandium aluminum nitride (ScA l N), zinc oxide (ZnO), lithium niobate (LiNbO 3), lithium tantalite (LiTaO 3), lead zirconate titanate (PZT), or polyvinylidene fluoride (PVDF) layer over the first Mo or W layer; forming a second Mo or W layer over the A l N, S cAl N, ZnO, LiNb O 3, LiTa G 3, PZT, or PVDF layer; forming a via through the first Mo or W layer and the GaN stack on opposite sides of the thin-film acoustic filter; and forming a cavity under the thin-film acoustic filter in the [111] crystal orientation Si handle wafer through the vias. Original
The method according to claim 2, further comprising forming a thin-film acoustic filter over the GaN stack by: forming an A I N, ScA L N, ZnO, LiNbO 3, L iTaO 3, PZT, or PVDF layer over the A l GaN/A iN barrier layer; forming a Mo or W layer over the A I N, S cAI N, ZnO, L i NbO 3, LiTaO 3, PZT, or PVDF layer; patterning the second Mo or W layer down to the A I N, S cAI N, ZnO, LiNb O 3, LiTa O 3, PZT, or PVDF layer; forming a via through the GaN stack on opposite sides of the thin-film acoustic filter; and forming a cavity under the thin-film acoustic filter in the [111] crystal orientation Si handle through the vias. Original
Canceled
A device comprising: a silicon on insulator (SOI) wafer, the SOI wafer comprising a [111] crystal orientation silicon (Si) handle wafer, a buried oxide (BOX) layer, and a top Si layer a complimentary metal-oxide-semiconductor (CMOS) device over the top Si layer; [[and]] a Bragg reflector over the [111] crystal orientation Si handle, the Bragg Reflector comprising a gallium nitride (GaN) stack with alternating layers of high/low acoustic impedance; and a GaN high-electron-mobility transistor power amplifier (GaN H EMT PA) in and over respective portions of the GaN stack. Currently amended
The device according to claim 10, wherein the GaN stack comprises: a buffer layer over the [111] crystal orientation Si handle wafer; a GaN channel layer over the buffer layer; and an aluminum gallium nitride (A l GaN)/aluminum nitride (A l N) barrier layer over the GaN channel layer. Original
The device according to claim 10, wherein the GaN stack comprises: a buffer layer over the [111] crystal orientation Si handle wafer; a GaN channel layer over the buffer layer; an A l GaN/A l N barrier layer over the GaN channel layer; and a silicon nitride (SiN) or silicon dioxide (SiO 2) passivation layer over the AlGaN/A l N barrier layer. Original
Canceled
The device according to claim [[10]] 12, further comprising: an encapsulation layer over the [111] crystal orientation Si handle wafer with a cavity over and around the thin-film acoustic filter; a sealing layer over the encapsulation layer; and a metal contact through the sealing layer and the encapsulation layer down to a portion of the thin-film acoustic filter. Currently amended
A device comprising: a silicon on insulator (SOI) wafer, the SOI wafer comprising a [111] crystal orientation silicon (Si) handle wafer, a buried oxide (BOX) layer, and a top Si layer; a complimentary metal-oxide-semiconductor (CMOS) device over the top Si; a gallium nitride (GaN) stack over the [111] crystal orientation Si handle; a GaN high-electron-mobility transistor power amplifier (GaN H EMT PA) in and over the GaN stack; a thin-film Lamb acoustic wave filter over the GaN stack; a via through the first Mo or W layer on opposite sides of the thin-film Lamb acoustic wave filter; and a cavity under the thin-film Lamb acoustic filter in a passivation layer of the GaN stack. Original
The device according to claim 19, wherein the GaN stack comprises: a buffer layer over the [111] crystal orientation Si handle wafer; a GaN channel layer over the buffer layer; an A l GaN/A l N barrier layer over the GaN channel layer; and the passivation layer of silicon nitride (SiN) or silicon dioxide (SiO 2) over the AlGaN/A lN barrier layer. Original
Layer stacks claimed or described, ordered top of device to substrate.
SOI wafer with GaN stack Bragg reflector and CMOS
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
silicon (Si) [111] crystal orientation handle wafer
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2, an SOI wafer 200 is provided with a top Si layer 201 (device layer) having a [100], [111], or [110] crystal orientation (rotated 45 0 for a p-channel …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN stack buffer layer thickness | 1.5 micrometer | GaN/AlGaN buffer layer |
GaN channel layer thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,468,454Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 C schematically illustrates a top view showing the cut lines for FIG s. I A and 1B; [0016] FIG s. 2 through 13 schematically illustrate cross-sectional …
FIG. 2, an SOI wafer 200 is provided with a top Si layer 201 (device layer) having a [100], [111], or [110] crystal orientation (rotated 45 0 for a p-channel …
FIG. 3, a CMOS device 301, e.g., a field-effect transistor (F ET), is formed over a portion of the top Si layer 201. The CMOS device 301 may be a FET, a CMOS …
FIG. 4. The protect layer 401 may be formed from one or more layers, such as SiN or SiO 2; or it could be formed from a material such as Si or spin on glass, …
FIG. 5, a region 501 is opened over the [111] crystal orientation Si handle wafer 205 for the subsequent formation of a GaN stack (not shown for illustrative …
FIG. 6. The GaN stack 601 may be formed, e.g., of a buffer layer 603 including a GaN or AlGaN, a GaN channel layer 605, an AlGaN/AlN barrier 607, and a SiN …
FIG. 7, a GaN HEMT PA 701 including a gate electrode 703 and S/D electrodes 705 is formed on the GaN channel layer 605 and the AlGaN/A lN barrier 607 of the …
FIG. 8, an optional protect layer 801 is formed e.g., of one or more layers similar to the protect layer 401, over the GaN H EMT 701. A thin-film acoustic filter …
FIG. 9. [0043] Referring to
FIG. 10, the protective layer 901 is removed and a Si sacrificial (SAC) layer 1001 is formed, e.g., by chemical vapor deposition (CVD), plasma enhanced chemical …
FIG. 11, a thin-film encapsulation layer 1101 is formed, e.g., of oxide/nitride by deposition and optional planarization, over the [111] crystal orientation Si …
FIG. 12. Referring to FIG s. 14A, 14B, and 14C, a contact 1401 is formed, e.g., of Al, on the Mo or W layer 809 (top electrode) of the thin-film acoustic filter …
FIG. 13. A pad (not shown for illustrative convenience) may also be opened through the sealing layer 1301 and the encapsulation layer 1101 and an Al contact …
FIG. 14C schematically illustrates a top view showing the cut lines for FIG s. 14A and 14B, in accordance with an exemplary embodiment. Specifically,
FIG. 15 schematically illustrates a cross-sectional view of a resultant thin- film piezoelectric Lamb acoustic wave filter, a GaN-channel/buffer Bragg reflector, …
FIG. 16 schematically illustrates a cross-sectional view of a thin-film piezoelectric B AW filter, a GaN-channel/buffer Bragg reflector, an AlGaN/A lN barrier seed …
FIG. 17 schematically illustrates a cross-sectional view of a thin-film piezoelectric Lamb acoustic wave filter, GaN-channel/buffer Bragg reflector, and a …
FIG. 18 schematically illustrates a cross-sectional view of a thin-film piezoelectric B AW filter, a Si O 2/GaN-channel/buffer Bragg reflector, and a …
FIG. 19 schematically illustrates a cross-sectional view of a thin-film piezoelectric B AW filter, a SiN/GaN-channel/buffer Bragg reflector, and a monolithically …
FIG. 20 schematically illustrates a cross-sectional view of a thin-film piezoelectric Lamb acoustic wave filter, a SiN/Si₀ 2 barrier seed layer, and a …
FIG. 21C schematically illustrates a top view showing the cut lines for FIG s. 21A and 21B, in accordance with an exemplary embodiment. Referring to FIG s. …
FIG. 22C schematically illustrates a top view showing the cut lines for FIG s. 22A and 22B, in accordance with an exemplary embodiment. The resultant device of …
FIG. 23C schematically illustrates a top view showing the cut lines for FIG s. 23A and 23B, in accordance with an exemplary embodiment. The resultant device of …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: providing a silicon on insulator (SOI) wafer comprising a [l 1] crystal orientation silicon (Si) handle wafer, a buried oxide (BOX) layer, and a top Si layer; forming a complimentary metal-oxide semiconductor (CMOS) device over the top Si layer of the SO I wafer; [[and]] forming a Bragg reflector over the [1 I I] crystal orientation Si handle wafer, the Bragg reflector comprising a gallium nitride (GaN) stack with alternating layers of high/low acoustic impedance; forming a sacrificial (SAC) layer over and around the thin-film acoustic filter; forming an encapsulation layer over the SOI wafer; forming a via through the encapsulation layer on opposite sides of the thin-film acoustic filter; removing the SAC layer throu g h the via, a cavity formed over and around the thin-film acoustic filter; forming a sealing layer over the encapsulation layer; and forming a metal contact through the sealing layer and the encapsulation layer down to a portion of the thin-film acoustic filter. Currently amended
The method according to claim 1, comprising forming GaN stack by: forming a buffer layer over the [1 1] crystal orientation Si handle wafer; forming a GaN channel layer over the buffer layer; forming an AlGaN/A l N barrier layer over the GaN channel layer; and forming a silicon nitride (S i N) or silicon dioxide (SiO 2) passivation layer over the AlGaN/A l N barrier layer. Original
The method according to claim 1, further comprising forming a GaN high- electron-mobility transistor power amplifier (GaN H EMT PA) in and over respective portions of the GaN stack. Original
The method according to claim I, comprising forming the GaN stack by: forming a buffer layer over the [l II] crystal orientation Si handle wafer; forming a GaN channel layer over the buffer layer; and forming an aluminum gallium nitride (A I GaN)/aluminum nitride (A L N) barrier layer over the GaN channel layer. Original
The method according to claim 2, further comprising forming a thin-film acoustic filter over the GaN stack by: forming a first molybdenum (Mo) or tungsten (W) layer over the A I GaN/AIN barrier layer; forming an aluminum nitride (A I N), scandium aluminum nitride (ScA l N), zinc oxide (ZnO), lithium niobate (LiNbO 3), lithium tantalite (LiTaO 3), lead zirconate titanate (PZT), or polyvinylidene fluoride (PVDF) layer over the first Mo or W layer; forming a second Mo or W layer over the A l N, S cAl N, ZnO, LiNb O 3, LiTa G 3, PZT, or PVDF layer; forming a via through the first Mo or W layer and the GaN stack on opposite sides of the thin-film acoustic filter; and forming a cavity under the thin-film acoustic filter in the [111] crystal orientation Si handle wafer through the vias. Original
The method according to claim 2, further comprising forming a thin-film acoustic filter over the GaN stack by: forming an A I N, ScA L N, ZnO, LiNbO 3, L iTaO 3, PZT, or PVDF layer over the A l GaN/A iN barrier layer; forming a Mo or W layer over the A I N, S cAI N, ZnO, L i NbO 3, LiTaO 3, PZT, or PVDF layer; patterning the second Mo or W layer down to the A I N, S cAI N, ZnO, LiNb O 3, LiTa O 3, PZT, or PVDF layer; forming a via through the GaN stack on opposite sides of the thin-film acoustic filter; and forming a cavity under the thin-film acoustic filter in the [111] crystal orientation Si handle through the vias. Original
Canceled
A device comprising: a silicon on insulator (SOI) wafer, the SOI wafer comprising a [111] crystal orientation silicon (Si) handle wafer, a buried oxide (BOX) layer, and a top Si layer a complimentary metal-oxide-semiconductor (CMOS) device over the top Si layer; [[and]] a Bragg reflector over the [111] crystal orientation Si handle, the Bragg Reflector comprising a gallium nitride (GaN) stack with alternating layers of high/low acoustic impedance; and a GaN high-electron-mobility transistor power amplifier (GaN H EMT PA) in and over respective portions of the GaN stack. Currently amended
The device according to claim 10, wherein the GaN stack comprises: a buffer layer over the [111] crystal orientation Si handle wafer; a GaN channel layer over the buffer layer; and an aluminum gallium nitride (A l GaN)/aluminum nitride (A l N) barrier layer over the GaN channel layer. Original
The device according to claim 10, wherein the GaN stack comprises: a buffer layer over the [111] crystal orientation Si handle wafer; a GaN channel layer over the buffer layer; an A l GaN/A l N barrier layer over the GaN channel layer; and a silicon nitride (SiN) or silicon dioxide (SiO 2) passivation layer over the AlGaN/A l N barrier layer. Original
Canceled
The device according to claim [[10]] 12, further comprising: an encapsulation layer over the [111] crystal orientation Si handle wafer with a cavity over and around the thin-film acoustic filter; a sealing layer over the encapsulation layer; and a metal contact through the sealing layer and the encapsulation layer down to a portion of the thin-film acoustic filter. Currently amended
A device comprising: a silicon on insulator (SOI) wafer, the SOI wafer comprising a [111] crystal orientation silicon (Si) handle wafer, a buried oxide (BOX) layer, and a top Si layer; a complimentary metal-oxide-semiconductor (CMOS) device over the top Si; a gallium nitride (GaN) stack over the [111] crystal orientation Si handle; a GaN high-electron-mobility transistor power amplifier (GaN H EMT PA) in and over the GaN stack; a thin-film Lamb acoustic wave filter over the GaN stack; a via through the first Mo or W layer on opposite sides of the thin-film Lamb acoustic wave filter; and a cavity under the thin-film Lamb acoustic filter in a passivation layer of the GaN stack. Original
The device according to claim 19, wherein the GaN stack comprises: a buffer layer over the [111] crystal orientation Si handle wafer; a GaN channel layer over the buffer layer; an A l GaN/A l N barrier layer over the GaN channel layer; and the passivation layer of silicon nitride (SiN) or silicon dioxide (SiO 2) over the AlGaN/A lN barrier layer. Original
Layer stacks claimed or described, ordered top of device to substrate.
SOI wafer with GaN stack Bragg reflector and CMOS
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
silicon (Si) [111] crystal orientation handle wafer
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2, an SOI wafer 200 is provided with a top Si layer 201 (device layer) having a [100], [111], or [110] crystal orientation (rotated 45 0 for a p-channel …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN stack buffer layer thickness | 1.5 micrometer | GaN/AlGaN buffer layer |
GaN channel layer thickness |
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US 10,468,454Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 C schematically illustrates a top view showing the cut lines for FIG s. I A and 1B; [0016] FIG s. 2 through 13 schematically illustrate cross-sectional …
FIG. 2, an SOI wafer 200 is provided with a top Si layer 201 (device layer) having a [100], [111], or [110] crystal orientation (rotated 45 0 for a p-channel …
FIG. 3, a CMOS device 301, e.g., a field-effect transistor (F ET), is formed over a portion of the top Si layer 201. The CMOS device 301 may be a FET, a CMOS …
FIG. 4. The protect layer 401 may be formed from one or more layers, such as SiN or SiO 2; or it could be formed from a material such as Si or spin on glass, …
FIG. 5, a region 501 is opened over the [111] crystal orientation Si handle wafer 205 for the subsequent formation of a GaN stack (not shown for illustrative …
FIG. 6. The GaN stack 601 may be formed, e.g., of a buffer layer 603 including a GaN or AlGaN, a GaN channel layer 605, an AlGaN/AlN barrier 607, and a SiN …
FIG. 7, a GaN HEMT PA 701 including a gate electrode 703 and S/D electrodes 705 is formed on the GaN channel layer 605 and the AlGaN/A lN barrier 607 of the …
FIG. 8, an optional protect layer 801 is formed e.g., of one or more layers similar to the protect layer 401, over the GaN H EMT 701. A thin-film acoustic filter …
FIG. 9. [0043] Referring to
FIG. 10, the protective layer 901 is removed and a Si sacrificial (SAC) layer 1001 is formed, e.g., by chemical vapor deposition (CVD), plasma enhanced chemical …
FIG. 11, a thin-film encapsulation layer 1101 is formed, e.g., of oxide/nitride by deposition and optional planarization, over the [111] crystal orientation Si …
FIG. 12. Referring to FIG s. 14A, 14B, and 14C, a contact 1401 is formed, e.g., of Al, on the Mo or W layer 809 (top electrode) of the thin-film acoustic filter …
FIG. 13. A pad (not shown for illustrative convenience) may also be opened through the sealing layer 1301 and the encapsulation layer 1101 and an Al contact …
FIG. 14C schematically illustrates a top view showing the cut lines for FIG s. 14A and 14B, in accordance with an exemplary embodiment. Specifically,
FIG. 15 schematically illustrates a cross-sectional view of a resultant thin- film piezoelectric Lamb acoustic wave filter, a GaN-channel/buffer Bragg reflector, …
FIG. 16 schematically illustrates a cross-sectional view of a thin-film piezoelectric B AW filter, a GaN-channel/buffer Bragg reflector, an AlGaN/A lN barrier seed …
FIG. 17 schematically illustrates a cross-sectional view of a thin-film piezoelectric Lamb acoustic wave filter, GaN-channel/buffer Bragg reflector, and a …
FIG. 18 schematically illustrates a cross-sectional view of a thin-film piezoelectric B AW filter, a Si O 2/GaN-channel/buffer Bragg reflector, and a …
FIG. 19 schematically illustrates a cross-sectional view of a thin-film piezoelectric B AW filter, a SiN/GaN-channel/buffer Bragg reflector, and a monolithically …
FIG. 20 schematically illustrates a cross-sectional view of a thin-film piezoelectric Lamb acoustic wave filter, a SiN/Si₀ 2 barrier seed layer, and a …
FIG. 21C schematically illustrates a top view showing the cut lines for FIG s. 21A and 21B, in accordance with an exemplary embodiment. Referring to FIG s. …
FIG. 22C schematically illustrates a top view showing the cut lines for FIG s. 22A and 22B, in accordance with an exemplary embodiment. The resultant device of …
FIG. 23C schematically illustrates a top view showing the cut lines for FIG s. 23A and 23B, in accordance with an exemplary embodiment. The resultant device of …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: providing a silicon on insulator (SOI) wafer comprising a [l 1] crystal orientation silicon (Si) handle wafer, a buried oxide (BOX) layer, and a top Si layer; forming a complimentary metal-oxide semiconductor (CMOS) device over the top Si layer of the SO I wafer; [[and]] forming a Bragg reflector over the [1 I I] crystal orientation Si handle wafer, the Bragg reflector comprising a gallium nitride (GaN) stack with alternating layers of high/low acoustic impedance; forming a sacrificial (SAC) layer over and around the thin-film acoustic filter; forming an encapsulation layer over the SOI wafer; forming a via through the encapsulation layer on opposite sides of the thin-film acoustic filter; removing the SAC layer throu g h the via, a cavity formed over and around the thin-film acoustic filter; forming a sealing layer over the encapsulation layer; and forming a metal contact through the sealing layer and the encapsulation layer down to a portion of the thin-film acoustic filter. Currently amended
The method according to claim 1, comprising forming GaN stack by: forming a buffer layer over the [1 1] crystal orientation Si handle wafer; forming a GaN channel layer over the buffer layer; forming an AlGaN/A l N barrier layer over the GaN channel layer; and forming a silicon nitride (S i N) or silicon dioxide (SiO 2) passivation layer over the AlGaN/A l N barrier layer. Original
The method according to claim 1, further comprising forming a GaN high- electron-mobility transistor power amplifier (GaN H EMT PA) in and over respective portions of the GaN stack. Original
The method according to claim I, comprising forming the GaN stack by: forming a buffer layer over the [l II] crystal orientation Si handle wafer; forming a GaN channel layer over the buffer layer; and forming an aluminum gallium nitride (A I GaN)/aluminum nitride (A L N) barrier layer over the GaN channel layer. Original
The method according to claim 2, further comprising forming a thin-film acoustic filter over the GaN stack by: forming a first molybdenum (Mo) or tungsten (W) layer over the A I GaN/AIN barrier layer; forming an aluminum nitride (A I N), scandium aluminum nitride (ScA l N), zinc oxide (ZnO), lithium niobate (LiNbO 3), lithium tantalite (LiTaO 3), lead zirconate titanate (PZT), or polyvinylidene fluoride (PVDF) layer over the first Mo or W layer; forming a second Mo or W layer over the A l N, S cAl N, ZnO, LiNb O 3, LiTa G 3, PZT, or PVDF layer; forming a via through the first Mo or W layer and the GaN stack on opposite sides of the thin-film acoustic filter; and forming a cavity under the thin-film acoustic filter in the [111] crystal orientation Si handle wafer through the vias. Original
The method according to claim 2, further comprising forming a thin-film acoustic filter over the GaN stack by: forming an A I N, ScA L N, ZnO, LiNbO 3, L iTaO 3, PZT, or PVDF layer over the A l GaN/A iN barrier layer; forming a Mo or W layer over the A I N, S cAI N, ZnO, L i NbO 3, LiTaO 3, PZT, or PVDF layer; patterning the second Mo or W layer down to the A I N, S cAI N, ZnO, LiNb O 3, LiTa O 3, PZT, or PVDF layer; forming a via through the GaN stack on opposite sides of the thin-film acoustic filter; and forming a cavity under the thin-film acoustic filter in the [111] crystal orientation Si handle through the vias. Original
Canceled
A device comprising: a silicon on insulator (SOI) wafer, the SOI wafer comprising a [111] crystal orientation silicon (Si) handle wafer, a buried oxide (BOX) layer, and a top Si layer a complimentary metal-oxide-semiconductor (CMOS) device over the top Si layer; [[and]] a Bragg reflector over the [111] crystal orientation Si handle, the Bragg Reflector comprising a gallium nitride (GaN) stack with alternating layers of high/low acoustic impedance; and a GaN high-electron-mobility transistor power amplifier (GaN H EMT PA) in and over respective portions of the GaN stack. Currently amended
The device according to claim 10, wherein the GaN stack comprises: a buffer layer over the [111] crystal orientation Si handle wafer; a GaN channel layer over the buffer layer; and an aluminum gallium nitride (A l GaN)/aluminum nitride (A l N) barrier layer over the GaN channel layer. Original
The device according to claim 10, wherein the GaN stack comprises: a buffer layer over the [111] crystal orientation Si handle wafer; a GaN channel layer over the buffer layer; an A l GaN/A l N barrier layer over the GaN channel layer; and a silicon nitride (SiN) or silicon dioxide (SiO 2) passivation layer over the AlGaN/A l N barrier layer. Original
Canceled
The device according to claim [[10]] 12, further comprising: an encapsulation layer over the [111] crystal orientation Si handle wafer with a cavity over and around the thin-film acoustic filter; a sealing layer over the encapsulation layer; and a metal contact through the sealing layer and the encapsulation layer down to a portion of the thin-film acoustic filter. Currently amended
A device comprising: a silicon on insulator (SOI) wafer, the SOI wafer comprising a [111] crystal orientation silicon (Si) handle wafer, a buried oxide (BOX) layer, and a top Si layer; a complimentary metal-oxide-semiconductor (CMOS) device over the top Si; a gallium nitride (GaN) stack over the [111] crystal orientation Si handle; a GaN high-electron-mobility transistor power amplifier (GaN H EMT PA) in and over the GaN stack; a thin-film Lamb acoustic wave filter over the GaN stack; a via through the first Mo or W layer on opposite sides of the thin-film Lamb acoustic wave filter; and a cavity under the thin-film Lamb acoustic filter in a passivation layer of the GaN stack. Original
The device according to claim 19, wherein the GaN stack comprises: a buffer layer over the [111] crystal orientation Si handle wafer; a GaN channel layer over the buffer layer; an A l GaN/A l N barrier layer over the GaN channel layer; and the passivation layer of silicon nitride (SiN) or silicon dioxide (SiO 2) over the AlGaN/A lN barrier layer. Original
Layer stacks claimed or described, ordered top of device to substrate.
SOI wafer with GaN stack Bragg reflector and CMOS
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
silicon (Si) [111] crystal orientation handle wafer
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2, an SOI wafer 200 is provided with a top Si layer 201 (device layer) having a [100], [111], or [110] crystal orientation (rotated 45 0 for a p-channel …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN stack buffer layer thickness | 1.5 micrometer | GaN/AlGaN buffer layer |
GaN channel layer thickness |
Related documents with shared materials, methods, properties, or citations.
thin-film bulk acoustic wave (BAW) filter on GaN stack
thin-film Lamb acoustic wave filter on GaN stack
GaN high-electron-mobility transistor power amplifier (GaN HEMT PA)
encapsulated thin-film acoustic filter with metal contacts
buried oxide (BOX) layer
SiO₂
GaN/AlGaN buffer layer
AlGaN/AlN barrier layer
molybdenum (Mo)
Mo
tungsten (W)
W
aluminum nitride (AlN)
AlN
scandium aluminum nitride (ScAlN)
ScAlN
zinc oxide (ZnO)
ZnO
lithium niobate (LiNbO₃)
LiNbO₃
lithium tantalate (LiTaO₃)
LiTaO₃
lead zirconate titanate (PZT) or polyvinylidene fluoride (PVDF)
silicon nitride (SiN)
Si₃N₄
FIG. 3, a CMOS device 301, e.g., a field-effect transistor (F ET), is formed over a portion of the top Si layer 201. The CMOS device 301 may be a FET, a CMOS …
FIG. 21C schematically illustrates a top view showing the cut lines for FIG s. 21A and 21B, in accordance with an exemplary embodiment. Referring to FIG s. …
| 0.35–1.05 micrometer |
GaN |
AlGaN/AlN barrier layer thickness | 4–30 nm | AlGaN/AlN barrier layer |
SiN passivation layer thickness | 480 nm | Si₃N₄ |
Thickness | 5–25 nm | — |
thin-film bulk acoustic wave (BAW) filter on GaN stack
thin-film Lamb acoustic wave filter on GaN stack
GaN high-electron-mobility transistor power amplifier (GaN HEMT PA)
encapsulated thin-film acoustic filter with metal contacts
buried oxide (BOX) layer
SiO₂
GaN/AlGaN buffer layer
AlGaN/AlN barrier layer
molybdenum (Mo)
Mo
tungsten (W)
W
aluminum nitride (AlN)
AlN
scandium aluminum nitride (ScAlN)
ScAlN
zinc oxide (ZnO)
ZnO
lithium niobate (LiNbO₃)
LiNbO₃
lithium tantalate (LiTaO₃)
LiTaO₃
lead zirconate titanate (PZT) or polyvinylidene fluoride (PVDF)
silicon nitride (SiN)
Si₃N₄
FIG. 3, a CMOS device 301, e.g., a field-effect transistor (F ET), is formed over a portion of the top Si layer 201. The CMOS device 301 may be a FET, a CMOS …
FIG. 21C schematically illustrates a top view showing the cut lines for FIG s. 21A and 21B, in accordance with an exemplary embodiment. Referring to FIG s. …
| 0.35–1.05 micrometer |
GaN |
AlGaN/AlN barrier layer thickness | 4–30 nm | AlGaN/AlN barrier layer |
SiN passivation layer thickness | 480 nm | Si₃N₄ |
Thickness | 5–25 nm | — |
thin-film bulk acoustic wave (BAW) filter on GaN stack
thin-film Lamb acoustic wave filter on GaN stack
GaN high-electron-mobility transistor power amplifier (GaN HEMT PA)
encapsulated thin-film acoustic filter with metal contacts
buried oxide (BOX) layer
SiO₂
GaN/AlGaN buffer layer
AlGaN/AlN barrier layer
molybdenum (Mo)
Mo
tungsten (W)
W
aluminum nitride (AlN)
AlN
scandium aluminum nitride (ScAlN)
ScAlN
zinc oxide (ZnO)
ZnO
lithium niobate (LiNbO₃)
LiNbO₃
lithium tantalate (LiTaO₃)
LiTaO₃
lead zirconate titanate (PZT) or polyvinylidene fluoride (PVDF)
silicon nitride (SiN)
Si₃N₄
FIG. 3, a CMOS device 301, e.g., a field-effect transistor (F ET), is formed over a portion of the top Si layer 201. The CMOS device 301 may be a FET, a CMOS …
FIG. 21C schematically illustrates a top view showing the cut lines for FIG s. 21A and 21B, in accordance with an exemplary embodiment. Referring to FIG s. …
| 0.35–1.05 micrometer |
GaN |
AlGaN/AlN barrier layer thickness | 4–30 nm | AlGaN/AlN barrier layer |
SiN passivation layer thickness | 480 nm | Si₃N₄ |
Thickness | 5–25 nm | — |
thin-film bulk acoustic wave (BAW) filter on GaN stack
thin-film Lamb acoustic wave filter on GaN stack
GaN high-electron-mobility transistor power amplifier (GaN HEMT PA)
encapsulated thin-film acoustic filter with metal contacts
buried oxide (BOX) layer
SiO₂
GaN/AlGaN buffer layer
AlGaN/AlN barrier layer
molybdenum (Mo)
Mo
tungsten (W)
W
aluminum nitride (AlN)
AlN
scandium aluminum nitride (ScAlN)
ScAlN
zinc oxide (ZnO)
ZnO
lithium niobate (LiNbO₃)
LiNbO₃
lithium tantalate (LiTaO₃)
LiTaO₃
lead zirconate titanate (PZT) or polyvinylidene fluoride (PVDF)
silicon nitride (SiN)
Si₃N₄
FIG. 3, a CMOS device 301, e.g., a field-effect transistor (F ET), is formed over a portion of the top Si layer 201. The CMOS device 301 may be a FET, a CMOS …
FIG. 21C schematically illustrates a top view showing the cut lines for FIG s. 21A and 21B, in accordance with an exemplary embodiment. Referring to FIG s. …
| 0.35–1.05 micrometer |
GaN |
AlGaN/AlN barrier layer thickness | 4–30 nm | AlGaN/AlN barrier layer |
SiN passivation layer thickness | 480 nm | Si₃N₄ |
Thickness | 5–25 nm | — |