Patent
US 9,496,197Apparatus and methods for heat removal and spreading from a field effect transistor
Miroslav Micovic
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,496,197Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 2 shows a process diagram to form near junction cooling for a device in accordance with the present disclosure.(In step 1) a SiO₂ mask 61 is deposited on …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-14. Cancelled canceled
A method of providing heat spreading from a field effect transistor (FET) comprising: depositing a Si O 2 mask on a substrate to define source and drain areas; forming n+ G aN ohmic regrowth by molecular beam epitaxy (MBE) in the source and drain areas; forming poly G aN on the Si O 2 mask; removing the poly G aN and the Si O 2 mask; depositing a SiN layer for passivation of a remaining surface; defining sacrificial source, drain, and gate contacts by depositing and patterning a first sacrificial material; depositing a first poly-diamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD) on the patterned first sacrificial material; planarizing the first poly-diamond dielectric and the first sacrificial material using chemical mechanical polishing (CMP), wherein the planarizing substantially reduces a first polydiamond dielectric thickness, and wherein the planarizin g substantially reduces a first sacrificial material thickness; depositing a second sacrificial material and patterning the second sacrificial material to form openings in the second sacrificial material aligned with the first poly-diamond dielectric, wherein a width of the patterned second sacrificial material is greater than a width of the patterned first sacrificial material; depositing a second poly-diamond dielectric on the first poly-diamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD); and U. S. App l n. No. 14/495,755 Pa g e 3 planarizing the second poly-diamond dielectric and the second sacrificial material using chemical mechanical polishing (CMP) so that the second poly-diamond dielectric remains only in the openings; selectively removing the patterned first sacrificial material and the patterned second sacrificial material by wet etching; selectively removing the SiN by inductively coupled plasma reactive ion etching (I CP- RIE); metalizing source and drain ohmic contacts and gate Schottky contacts by plasma-atomic layer deposition (ALD) and electro-plating; depositing a first benzocyclobutene (BCB) coating; patterning the first BCB coating; forming a plated metal bridge of Cu, Ag, or Au over the patterned first BCB coating; plating a thermal via to the metal bridge; and forming a heat sink on the thermal via.
The method of claim 15 wherein the SiN layer is approximately SOO A thick.
The method of claim 15 wherein defining sacrificial source, drain, and gate contacts by depositing and patterning the first sacrificial material comprises using 2000 A thick sacrificial material.
The method of claim 15 wherein depositing the first poly-diamond dielectric by hot-wire chemical vapor deposition (CVD) is at a temperature of 800 °C.
The method of claim 15 wherein depositing a first benzocyclobutene (BCB) coating comprises depositing a 1 0 m thick BCB coating.
The method of claim 15 further comprising: coupling a SiC substrate to the substrate; forming a metal via through the SiC substrate thermally coupled to the substrate; and U. S. App l n. No. 14/495,755 Pa g e 4 coupling a heat sink to the metal via.
The method of claim 15 wherein the substrate comprises GaN, A l GaN or AlN.
The method of claim 15 further comprising: depositing a second BCB coating; and patterning the second BCB coating.
The method of claim 15 wherein the first sacrificial material is not a stopping layer.
A method of making a providing heat spreading from a field effect transistor (F ET) comprising: defining sacrificial source, drain, and gate contacts by depositing and patterning a first sacrificial material on a substrate; depositing a first poly-diamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD) on the patterned first sacrificial material; planarizing the first poly-diamond dielectric and the first sacrificial material using chemical mechanical polishing (CMP), wherein the planarizing substantially reduces a first poly- diamond dielectric thickness, and wherein the planarizing substantially reduces a first sacrificial material thickness; depositing a second sacrificial material and patterning the second sacrificial material to form openings in the second sacrificial material aligned with the first poly-diamond dielectric, wherein a width of the patterned second sacrificial material is greater than a width of the patterned first sacrificial material; depositing a second poly-diamond dielectric on the first polydiamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD); planarizing the second poly-diamond dielectric and the second sacrificial material using chemical mechanical polishing (CMP) so that the second poly-diamond dielectric remains only in the openings; and selectively removing the patterned first sacrificial material and the patterned second sacrificial material by wet etching. U. S. App l n. No. 14/495,755 Pa g e
The method of claim 23 wherein defining sacrificial source, drain, and gate contacts a by depositing and patterning the first sacrificial material comprises using 2000 A thick sacrificial material.
The method of claim 23 wherein: depositing the first poly-diamond dielectric by hot-wire chemical vapor deposition (CVD) is at a temperature of 800 ° C; and depositing the second polydiamond dielectric by hot-wire chemical vapor deposition (CVD) is at a temperature of 800 °C.
The method of claim 23 further comprising: forming a benzocyclobutene (BCB) coating on the second poly-diamond dielectric; forming a plated metal bridge of Cu, Ag, or Au over the BCB coating; and forming a heat sink on the plated metal bridge.
The method of claim 23 further comprising: coupling a SiC substrate to the substrate; forming a metal via through the SiC substrate thermally coupled to the substrate; and coupling a heat sink to the metal via.
The method of claim 23 wherein the first sacrificial material is not a stopping layer.
Layer stacks claimed or described, ordered top of device to substrate.
field-effect transistor (FET) with poly-diamond heat spreading
Materials described outside the worked examples.
SiO₂ mask
SiO₂
n+ GaN ohmic regrowth
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,496,197Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 2 shows a process diagram to form near junction cooling for a device in accordance with the present disclosure.(In step 1) a SiO₂ mask 61 is deposited on …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-14. Cancelled canceled
A method of providing heat spreading from a field effect transistor (FET) comprising: depositing a Si O 2 mask on a substrate to define source and drain areas; forming n+ G aN ohmic regrowth by molecular beam epitaxy (MBE) in the source and drain areas; forming poly G aN on the Si O 2 mask; removing the poly G aN and the Si O 2 mask; depositing a SiN layer for passivation of a remaining surface; defining sacrificial source, drain, and gate contacts by depositing and patterning a first sacrificial material; depositing a first poly-diamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD) on the patterned first sacrificial material; planarizing the first poly-diamond dielectric and the first sacrificial material using chemical mechanical polishing (CMP), wherein the planarizing substantially reduces a first polydiamond dielectric thickness, and wherein the planarizin g substantially reduces a first sacrificial material thickness; depositing a second sacrificial material and patterning the second sacrificial material to form openings in the second sacrificial material aligned with the first poly-diamond dielectric, wherein a width of the patterned second sacrificial material is greater than a width of the patterned first sacrificial material; depositing a second poly-diamond dielectric on the first poly-diamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD); and U. S. App l n. No. 14/495,755 Pa g e 3 planarizing the second poly-diamond dielectric and the second sacrificial material using chemical mechanical polishing (CMP) so that the second poly-diamond dielectric remains only in the openings; selectively removing the patterned first sacrificial material and the patterned second sacrificial material by wet etching; selectively removing the SiN by inductively coupled plasma reactive ion etching (I CP- RIE); metalizing source and drain ohmic contacts and gate Schottky contacts by plasma-atomic layer deposition (ALD) and electro-plating; depositing a first benzocyclobutene (BCB) coating; patterning the first BCB coating; forming a plated metal bridge of Cu, Ag, or Au over the patterned first BCB coating; plating a thermal via to the metal bridge; and forming a heat sink on the thermal via.
The method of claim 15 wherein the SiN layer is approximately SOO A thick.
The method of claim 15 wherein defining sacrificial source, drain, and gate contacts by depositing and patterning the first sacrificial material comprises using 2000 A thick sacrificial material.
The method of claim 15 wherein depositing the first poly-diamond dielectric by hot-wire chemical vapor deposition (CVD) is at a temperature of 800 °C.
The method of claim 15 wherein depositing a first benzocyclobutene (BCB) coating comprises depositing a 1 0 m thick BCB coating.
The method of claim 15 further comprising: coupling a SiC substrate to the substrate; forming a metal via through the SiC substrate thermally coupled to the substrate; and U. S. App l n. No. 14/495,755 Pa g e 4 coupling a heat sink to the metal via.
The method of claim 15 wherein the substrate comprises GaN, A l GaN or AlN.
The method of claim 15 further comprising: depositing a second BCB coating; and patterning the second BCB coating.
The method of claim 15 wherein the first sacrificial material is not a stopping layer.
A method of making a providing heat spreading from a field effect transistor (F ET) comprising: defining sacrificial source, drain, and gate contacts by depositing and patterning a first sacrificial material on a substrate; depositing a first poly-diamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD) on the patterned first sacrificial material; planarizing the first poly-diamond dielectric and the first sacrificial material using chemical mechanical polishing (CMP), wherein the planarizing substantially reduces a first poly- diamond dielectric thickness, and wherein the planarizing substantially reduces a first sacrificial material thickness; depositing a second sacrificial material and patterning the second sacrificial material to form openings in the second sacrificial material aligned with the first poly-diamond dielectric, wherein a width of the patterned second sacrificial material is greater than a width of the patterned first sacrificial material; depositing a second poly-diamond dielectric on the first polydiamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD); planarizing the second poly-diamond dielectric and the second sacrificial material using chemical mechanical polishing (CMP) so that the second poly-diamond dielectric remains only in the openings; and selectively removing the patterned first sacrificial material and the patterned second sacrificial material by wet etching. U. S. App l n. No. 14/495,755 Pa g e
The method of claim 23 wherein defining sacrificial source, drain, and gate contacts a by depositing and patterning the first sacrificial material comprises using 2000 A thick sacrificial material.
The method of claim 23 wherein: depositing the first poly-diamond dielectric by hot-wire chemical vapor deposition (CVD) is at a temperature of 800 ° C; and depositing the second polydiamond dielectric by hot-wire chemical vapor deposition (CVD) is at a temperature of 800 °C.
The method of claim 23 further comprising: forming a benzocyclobutene (BCB) coating on the second poly-diamond dielectric; forming a plated metal bridge of Cu, Ag, or Au over the BCB coating; and forming a heat sink on the plated metal bridge.
The method of claim 23 further comprising: coupling a SiC substrate to the substrate; forming a metal via through the SiC substrate thermally coupled to the substrate; and coupling a heat sink to the metal via.
The method of claim 23 wherein the first sacrificial material is not a stopping layer.
Layer stacks claimed or described, ordered top of device to substrate.
field-effect transistor (FET) with poly-diamond heat spreading
Materials described outside the worked examples.
SiO₂ mask
SiO₂
n+ GaN ohmic regrowth
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,496,197Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 2 shows a process diagram to form near junction cooling for a device in accordance with the present disclosure.(In step 1) a SiO₂ mask 61 is deposited on …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-14. Cancelled canceled
A method of providing heat spreading from a field effect transistor (FET) comprising: depositing a Si O 2 mask on a substrate to define source and drain areas; forming n+ G aN ohmic regrowth by molecular beam epitaxy (MBE) in the source and drain areas; forming poly G aN on the Si O 2 mask; removing the poly G aN and the Si O 2 mask; depositing a SiN layer for passivation of a remaining surface; defining sacrificial source, drain, and gate contacts by depositing and patterning a first sacrificial material; depositing a first poly-diamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD) on the patterned first sacrificial material; planarizing the first poly-diamond dielectric and the first sacrificial material using chemical mechanical polishing (CMP), wherein the planarizing substantially reduces a first polydiamond dielectric thickness, and wherein the planarizin g substantially reduces a first sacrificial material thickness; depositing a second sacrificial material and patterning the second sacrificial material to form openings in the second sacrificial material aligned with the first poly-diamond dielectric, wherein a width of the patterned second sacrificial material is greater than a width of the patterned first sacrificial material; depositing a second poly-diamond dielectric on the first poly-diamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD); and U. S. App l n. No. 14/495,755 Pa g e 3 planarizing the second poly-diamond dielectric and the second sacrificial material using chemical mechanical polishing (CMP) so that the second poly-diamond dielectric remains only in the openings; selectively removing the patterned first sacrificial material and the patterned second sacrificial material by wet etching; selectively removing the SiN by inductively coupled plasma reactive ion etching (I CP- RIE); metalizing source and drain ohmic contacts and gate Schottky contacts by plasma-atomic layer deposition (ALD) and electro-plating; depositing a first benzocyclobutene (BCB) coating; patterning the first BCB coating; forming a plated metal bridge of Cu, Ag, or Au over the patterned first BCB coating; plating a thermal via to the metal bridge; and forming a heat sink on the thermal via.
The method of claim 15 wherein the SiN layer is approximately SOO A thick.
The method of claim 15 wherein defining sacrificial source, drain, and gate contacts by depositing and patterning the first sacrificial material comprises using 2000 A thick sacrificial material.
The method of claim 15 wherein depositing the first poly-diamond dielectric by hot-wire chemical vapor deposition (CVD) is at a temperature of 800 °C.
The method of claim 15 wherein depositing a first benzocyclobutene (BCB) coating comprises depositing a 1 0 m thick BCB coating.
The method of claim 15 further comprising: coupling a SiC substrate to the substrate; forming a metal via through the SiC substrate thermally coupled to the substrate; and U. S. App l n. No. 14/495,755 Pa g e 4 coupling a heat sink to the metal via.
The method of claim 15 wherein the substrate comprises GaN, A l GaN or AlN.
The method of claim 15 further comprising: depositing a second BCB coating; and patterning the second BCB coating.
The method of claim 15 wherein the first sacrificial material is not a stopping layer.
A method of making a providing heat spreading from a field effect transistor (F ET) comprising: defining sacrificial source, drain, and gate contacts by depositing and patterning a first sacrificial material on a substrate; depositing a first poly-diamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD) on the patterned first sacrificial material; planarizing the first poly-diamond dielectric and the first sacrificial material using chemical mechanical polishing (CMP), wherein the planarizing substantially reduces a first poly- diamond dielectric thickness, and wherein the planarizing substantially reduces a first sacrificial material thickness; depositing a second sacrificial material and patterning the second sacrificial material to form openings in the second sacrificial material aligned with the first poly-diamond dielectric, wherein a width of the patterned second sacrificial material is greater than a width of the patterned first sacrificial material; depositing a second poly-diamond dielectric on the first polydiamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD); planarizing the second poly-diamond dielectric and the second sacrificial material using chemical mechanical polishing (CMP) so that the second poly-diamond dielectric remains only in the openings; and selectively removing the patterned first sacrificial material and the patterned second sacrificial material by wet etching. U. S. App l n. No. 14/495,755 Pa g e
The method of claim 23 wherein defining sacrificial source, drain, and gate contacts a by depositing and patterning the first sacrificial material comprises using 2000 A thick sacrificial material.
The method of claim 23 wherein: depositing the first poly-diamond dielectric by hot-wire chemical vapor deposition (CVD) is at a temperature of 800 ° C; and depositing the second polydiamond dielectric by hot-wire chemical vapor deposition (CVD) is at a temperature of 800 °C.
The method of claim 23 further comprising: forming a benzocyclobutene (BCB) coating on the second poly-diamond dielectric; forming a plated metal bridge of Cu, Ag, or Au over the BCB coating; and forming a heat sink on the plated metal bridge.
The method of claim 23 further comprising: coupling a SiC substrate to the substrate; forming a metal via through the SiC substrate thermally coupled to the substrate; and coupling a heat sink to the metal via.
The method of claim 23 wherein the first sacrificial material is not a stopping layer.
Layer stacks claimed or described, ordered top of device to substrate.
field-effect transistor (FET) with poly-diamond heat spreading
Materials described outside the worked examples.
SiO₂ mask
SiO₂
n+ GaN ohmic regrowth
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,496,197Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 2 shows a process diagram to form near junction cooling for a device in accordance with the present disclosure.(In step 1) a SiO₂ mask 61 is deposited on …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-14. Cancelled canceled
A method of providing heat spreading from a field effect transistor (FET) comprising: depositing a Si O 2 mask on a substrate to define source and drain areas; forming n+ G aN ohmic regrowth by molecular beam epitaxy (MBE) in the source and drain areas; forming poly G aN on the Si O 2 mask; removing the poly G aN and the Si O 2 mask; depositing a SiN layer for passivation of a remaining surface; defining sacrificial source, drain, and gate contacts by depositing and patterning a first sacrificial material; depositing a first poly-diamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD) on the patterned first sacrificial material; planarizing the first poly-diamond dielectric and the first sacrificial material using chemical mechanical polishing (CMP), wherein the planarizing substantially reduces a first polydiamond dielectric thickness, and wherein the planarizin g substantially reduces a first sacrificial material thickness; depositing a second sacrificial material and patterning the second sacrificial material to form openings in the second sacrificial material aligned with the first poly-diamond dielectric, wherein a width of the patterned second sacrificial material is greater than a width of the patterned first sacrificial material; depositing a second poly-diamond dielectric on the first poly-diamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD); and U. S. App l n. No. 14/495,755 Pa g e 3 planarizing the second poly-diamond dielectric and the second sacrificial material using chemical mechanical polishing (CMP) so that the second poly-diamond dielectric remains only in the openings; selectively removing the patterned first sacrificial material and the patterned second sacrificial material by wet etching; selectively removing the SiN by inductively coupled plasma reactive ion etching (I CP- RIE); metalizing source and drain ohmic contacts and gate Schottky contacts by plasma-atomic layer deposition (ALD) and electro-plating; depositing a first benzocyclobutene (BCB) coating; patterning the first BCB coating; forming a plated metal bridge of Cu, Ag, or Au over the patterned first BCB coating; plating a thermal via to the metal bridge; and forming a heat sink on the thermal via.
The method of claim 15 wherein the SiN layer is approximately SOO A thick.
The method of claim 15 wherein defining sacrificial source, drain, and gate contacts by depositing and patterning the first sacrificial material comprises using 2000 A thick sacrificial material.
The method of claim 15 wherein depositing the first poly-diamond dielectric by hot-wire chemical vapor deposition (CVD) is at a temperature of 800 °C.
The method of claim 15 wherein depositing a first benzocyclobutene (BCB) coating comprises depositing a 1 0 m thick BCB coating.
The method of claim 15 further comprising: coupling a SiC substrate to the substrate; forming a metal via through the SiC substrate thermally coupled to the substrate; and U. S. App l n. No. 14/495,755 Pa g e 4 coupling a heat sink to the metal via.
The method of claim 15 wherein the substrate comprises GaN, A l GaN or AlN.
The method of claim 15 further comprising: depositing a second BCB coating; and patterning the second BCB coating.
The method of claim 15 wherein the first sacrificial material is not a stopping layer.
A method of making a providing heat spreading from a field effect transistor (F ET) comprising: defining sacrificial source, drain, and gate contacts by depositing and patterning a first sacrificial material on a substrate; depositing a first poly-diamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD) on the patterned first sacrificial material; planarizing the first poly-diamond dielectric and the first sacrificial material using chemical mechanical polishing (CMP), wherein the planarizing substantially reduces a first poly- diamond dielectric thickness, and wherein the planarizing substantially reduces a first sacrificial material thickness; depositing a second sacrificial material and patterning the second sacrificial material to form openings in the second sacrificial material aligned with the first poly-diamond dielectric, wherein a width of the patterned second sacrificial material is greater than a width of the patterned first sacrificial material; depositing a second poly-diamond dielectric on the first polydiamond dielectric at a temperature by hot-wire chemical vapor deposition (CVD); planarizing the second poly-diamond dielectric and the second sacrificial material using chemical mechanical polishing (CMP) so that the second poly-diamond dielectric remains only in the openings; and selectively removing the patterned first sacrificial material and the patterned second sacrificial material by wet etching. U. S. App l n. No. 14/495,755 Pa g e
The method of claim 23 wherein defining sacrificial source, drain, and gate contacts a by depositing and patterning the first sacrificial material comprises using 2000 A thick sacrificial material.
The method of claim 23 wherein: depositing the first poly-diamond dielectric by hot-wire chemical vapor deposition (CVD) is at a temperature of 800 ° C; and depositing the second polydiamond dielectric by hot-wire chemical vapor deposition (CVD) is at a temperature of 800 °C.
The method of claim 23 further comprising: forming a benzocyclobutene (BCB) coating on the second poly-diamond dielectric; forming a plated metal bridge of Cu, Ag, or Au over the BCB coating; and forming a heat sink on the plated metal bridge.
The method of claim 23 further comprising: coupling a SiC substrate to the substrate; forming a metal via through the SiC substrate thermally coupled to the substrate; and coupling a heat sink to the metal via.
The method of claim 23 wherein the first sacrificial material is not a stopping layer.
Layer stacks claimed or described, ordered top of device to substrate.
field-effect transistor (FET) with poly-diamond heat spreading
Materials described outside the worked examples.
SiO₂ mask
SiO₂
n+ GaN ohmic regrowth
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
SiN passivation layer
SiN
first poly-diamond dielectric
second poly-diamond dielectric
benzocyclobutene (BCB) coating
plated metal bridge
SiC substrate
SiC
AlGaN substrate
AlGaN
AlN substrate
AlN
SiN passivation layer
SiN
first poly-diamond dielectric
second poly-diamond dielectric
benzocyclobutene (BCB) coating
plated metal bridge
SiC substrate
SiC
AlGaN substrate
AlGaN
AlN substrate
AlN
SiN passivation layer
SiN
first poly-diamond dielectric
second poly-diamond dielectric
benzocyclobutene (BCB) coating
plated metal bridge
SiC substrate
SiC
AlGaN substrate
AlGaN
AlN substrate
AlN
SiN passivation layer
SiN
first poly-diamond dielectric
second poly-diamond dielectric
benzocyclobutene (BCB) coating
plated metal bridge
SiC substrate
SiC
AlGaN substrate
AlGaN
AlN substrate
AlN