Patent
US 9,117,738SEMICONDUCTOR DEVICE
Makoto WADA
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,117,738Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cr o ss-sectional view showing the schematic structure of a semiconductor device according 20 to a first embodiment.
FIGS. 2A to 2E are cross-sectional views showing manufacturing steps of a semiconductor device according to a second embodiment. FI G. 3 is a cross-sectional …
FIG. 3.
FIGS. 4A, 4B are cross-sectional views showing-3-manufacturing steps of the semiconductor device of
FIG. 5 is a cross-sectional view for illustrating a manufacturing process of a semiconductor device 5 according to a fourth embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a substrate having semiconductor elements formed therein, 5 a first graphene wire formed above the substrate, the first graphene wire including a multilayered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the 10 substrate, the second graphene wire including a multi- layered graphene layer into which the impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire,.and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.
The device according to claim 1, wherein each of the first and second multi-layered graphene wires is 20 formed by sequentially laminating a catalytic underlying layer, catalytic metal layer and the multi- layered graphene layer from the lower-layer side.
The device according to claim 1, wherein the impurity is one of Br, I, F and Cl.
25 4. The device according to claim 1, wherein the lower-layer contact is connected to the semiconductor element via a wire on the lower-layer side of the-20-multi-layered graphene wire and the upper-layer contact is connected to a wire on the upper-layer side of the multilayered graphene wire.
The device according to claim 1, wherein the 5 first multi-layered graphene wire is arranged in a memory cell region and the second multi-layered graphene wire is arranged in a peripheral circuit region.
A semiconductor device comprising: 10 a substrate having semiconductor elements formed therein, a first multi-layered graphene wire formed above the substrate, the first multi-layered graphene wire including a multi-layered graphene layer having a 15 preset impurity doped therein, a second multi-layered graphene wire formed o n the same layer as the first multi-layered graphene wire above the substrate, the second multi-layered graphene wire being formed wider than the first multi-layered 20 graphene wire and including a multi-layered graphene layer in an edge portion of which the impurity is selectively doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene 25 wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.-21 -
The device according to claim 6, wherein each of the first and second multi-layered graphene wires is formed by sequentially laminating a catalytic underlying layer, catalytic metal layer and the multi- 5 layered graphene layer from the lower-layer side.
The device according to claim 6, wherein the impurity is one of Br, I, F and Cl.
The device according to claim 6, wherein the lower-layer contact is connected to the semiconductor 10 element via a wire on the lower-layer side of the multi-layered graphene wire and the upper-layer contact is connected to a wire on the upper-layer side of the multi-layered graphene wire.
The device according to claim 6, wherein the 15 first multi-layered graphene wire is arranged in a memory cell region and the second multi-layered graphene wire is arranged in a peripheral circuit region.
A semiconductor device manufacturing method 20 comprising: forming an interlayer insulating film and lower- layer contact on a substrate having semiconductor elements formed therein, forming a multi-layered graphene wiring structure 25 including a multi-layered graphene layer on the interlayer insulating film and lower-layer contact, forming a first multi-layered graphene wire-22-connected to the lower-layer contact and a second multi-layered graphene wire that is not connected to the lower-layer contact by processing the multi-layered graphene wiring structure to a wiring pattern, a doping 5 amount of a halogen-series element in the first multi- layered graphene wire being set larger than a doping amount of a halogen-series element in the second multi- layered graphene wire, and forming an upper-layer contact connected to the 10 second multi-layered graphene wire.
The method according to claim 11, wherein setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to mask the 15, second multi-layered graphene wire after the first and second multi-layered graphene wires are f o rmed and, in this state, dope a halogen-series element into the first multilayered graphene wire.
The method according to claim 11, wherein 20 setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to set the second multi-layered graphene wire wider than the first multi- layered graphene wire when the first and second multi- 25 layered graphene wires are formed, and dope a wh ole portion of the multi-layered graphene layer of the first multi-layered graphene wire and selectively dope-23-an edge portion of the multi-layered graphene layer of the second multilayered graphene wire by doping the halogen-series element from the side surfaces of the first and second multi-layered graphene wires.
5 14. The method according to claim 11, wherein setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to form the first multi-layered graphene wire by use of an R IE method 10 using halogen-series gas with respect to the multi- layered graphene wiring structure and forming the second multilayered graphene wire by use of an RIE method that does not use the halogen-series gas.
The method according to claim 11, wherein 15 setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to form the first multi-layered graphene wire and the second multi- layered graphene wire that is wider than the first 20 multi-layered graphene wire by processing the multi- layered graphene wiring structure into a wiring pattern by use of an RIE method using halogen-series gas.
The method according to claim 11, wherein forming the m ulti-layered graphene wiring structure is 25 to sequentially laminate a catalytic underlying layer, catalytic metal layer and the multi-layered graphene layer from the lower-layer side.-24 -
The method according to claim 11, wherein one of Br, I, F and Cl is used as the halogen-series element.
18. The method according to claim 11, wherein the 5 lower-layer contact is connected to the semiconductor element v i a w ir e on the lower-layer side of the multi-layered graphene wire and the upper-layer contact is connected to a wire on the upper-layer side of the multi-layered graphene wire.
10 19. The method according to claim 11, wherein the first multi-layered graphene wire is arranged in a memory cell region and the second multi-layered graphene wire is arranged in a peripheral circuit region.
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with dual multi-layered graphene wires (doped/undoped, same layer)
Materials described outside the worked examples.
multi-layered graphene (impurity-doped)
multi-layered graphene (undoped)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 0.5 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,117,738Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cr o ss-sectional view showing the schematic structure of a semiconductor device according 20 to a first embodiment.
FIGS. 2A to 2E are cross-sectional views showing manufacturing steps of a semiconductor device according to a second embodiment. FI G. 3 is a cross-sectional …
FIG. 3.
FIGS. 4A, 4B are cross-sectional views showing-3-manufacturing steps of the semiconductor device of
FIG. 5 is a cross-sectional view for illustrating a manufacturing process of a semiconductor device 5 according to a fourth embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a substrate having semiconductor elements formed therein, 5 a first graphene wire formed above the substrate, the first graphene wire including a multilayered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the 10 substrate, the second graphene wire including a multi- layered graphene layer into which the impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire,.and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.
The device according to claim 1, wherein each of the first and second multi-layered graphene wires is 20 formed by sequentially laminating a catalytic underlying layer, catalytic metal layer and the multi- layered graphene layer from the lower-layer side.
The device according to claim 1, wherein the impurity is one of Br, I, F and Cl.
25 4. The device according to claim 1, wherein the lower-layer contact is connected to the semiconductor element via a wire on the lower-layer side of the-20-multi-layered graphene wire and the upper-layer contact is connected to a wire on the upper-layer side of the multilayered graphene wire.
The device according to claim 1, wherein the 5 first multi-layered graphene wire is arranged in a memory cell region and the second multi-layered graphene wire is arranged in a peripheral circuit region.
A semiconductor device comprising: 10 a substrate having semiconductor elements formed therein, a first multi-layered graphene wire formed above the substrate, the first multi-layered graphene wire including a multi-layered graphene layer having a 15 preset impurity doped therein, a second multi-layered graphene wire formed o n the same layer as the first multi-layered graphene wire above the substrate, the second multi-layered graphene wire being formed wider than the first multi-layered 20 graphene wire and including a multi-layered graphene layer in an edge portion of which the impurity is selectively doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene 25 wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.-21 -
The device according to claim 6, wherein each of the first and second multi-layered graphene wires is formed by sequentially laminating a catalytic underlying layer, catalytic metal layer and the multi- 5 layered graphene layer from the lower-layer side.
The device according to claim 6, wherein the impurity is one of Br, I, F and Cl.
The device according to claim 6, wherein the lower-layer contact is connected to the semiconductor 10 element via a wire on the lower-layer side of the multi-layered graphene wire and the upper-layer contact is connected to a wire on the upper-layer side of the multi-layered graphene wire.
The device according to claim 6, wherein the 15 first multi-layered graphene wire is arranged in a memory cell region and the second multi-layered graphene wire is arranged in a peripheral circuit region.
A semiconductor device manufacturing method 20 comprising: forming an interlayer insulating film and lower- layer contact on a substrate having semiconductor elements formed therein, forming a multi-layered graphene wiring structure 25 including a multi-layered graphene layer on the interlayer insulating film and lower-layer contact, forming a first multi-layered graphene wire-22-connected to the lower-layer contact and a second multi-layered graphene wire that is not connected to the lower-layer contact by processing the multi-layered graphene wiring structure to a wiring pattern, a doping 5 amount of a halogen-series element in the first multi- layered graphene wire being set larger than a doping amount of a halogen-series element in the second multi- layered graphene wire, and forming an upper-layer contact connected to the 10 second multi-layered graphene wire.
The method according to claim 11, wherein setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to mask the 15, second multi-layered graphene wire after the first and second multi-layered graphene wires are f o rmed and, in this state, dope a halogen-series element into the first multilayered graphene wire.
The method according to claim 11, wherein 20 setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to set the second multi-layered graphene wire wider than the first multi- layered graphene wire when the first and second multi- 25 layered graphene wires are formed, and dope a wh ole portion of the multi-layered graphene layer of the first multi-layered graphene wire and selectively dope-23-an edge portion of the multi-layered graphene layer of the second multilayered graphene wire by doping the halogen-series element from the side surfaces of the first and second multi-layered graphene wires.
5 14. The method according to claim 11, wherein setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to form the first multi-layered graphene wire by use of an R IE method 10 using halogen-series gas with respect to the multi- layered graphene wiring structure and forming the second multilayered graphene wire by use of an RIE method that does not use the halogen-series gas.
The method according to claim 11, wherein 15 setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to form the first multi-layered graphene wire and the second multi- layered graphene wire that is wider than the first 20 multi-layered graphene wire by processing the multi- layered graphene wiring structure into a wiring pattern by use of an RIE method using halogen-series gas.
The method according to claim 11, wherein forming the m ulti-layered graphene wiring structure is 25 to sequentially laminate a catalytic underlying layer, catalytic metal layer and the multi-layered graphene layer from the lower-layer side.-24 -
The method according to claim 11, wherein one of Br, I, F and Cl is used as the halogen-series element.
18. The method according to claim 11, wherein the 5 lower-layer contact is connected to the semiconductor element v i a w ir e on the lower-layer side of the multi-layered graphene wire and the upper-layer contact is connected to a wire on the upper-layer side of the multi-layered graphene wire.
10 19. The method according to claim 11, wherein the first multi-layered graphene wire is arranged in a memory cell region and the second multi-layered graphene wire is arranged in a peripheral circuit region.
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with dual multi-layered graphene wires (doped/undoped, same layer)
Materials described outside the worked examples.
multi-layered graphene (impurity-doped)
multi-layered graphene (undoped)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 0.5 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,117,738Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cr o ss-sectional view showing the schematic structure of a semiconductor device according 20 to a first embodiment.
FIGS. 2A to 2E are cross-sectional views showing manufacturing steps of a semiconductor device according to a second embodiment. FI G. 3 is a cross-sectional …
FIG. 3.
FIGS. 4A, 4B are cross-sectional views showing-3-manufacturing steps of the semiconductor device of
FIG. 5 is a cross-sectional view for illustrating a manufacturing process of a semiconductor device 5 according to a fourth embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a substrate having semiconductor elements formed therein, 5 a first graphene wire formed above the substrate, the first graphene wire including a multilayered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the 10 substrate, the second graphene wire including a multi- layered graphene layer into which the impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire,.and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.
The device according to claim 1, wherein each of the first and second multi-layered graphene wires is 20 formed by sequentially laminating a catalytic underlying layer, catalytic metal layer and the multi- layered graphene layer from the lower-layer side.
The device according to claim 1, wherein the impurity is one of Br, I, F and Cl.
25 4. The device according to claim 1, wherein the lower-layer contact is connected to the semiconductor element via a wire on the lower-layer side of the-20-multi-layered graphene wire and the upper-layer contact is connected to a wire on the upper-layer side of the multilayered graphene wire.
The device according to claim 1, wherein the 5 first multi-layered graphene wire is arranged in a memory cell region and the second multi-layered graphene wire is arranged in a peripheral circuit region.
A semiconductor device comprising: 10 a substrate having semiconductor elements formed therein, a first multi-layered graphene wire formed above the substrate, the first multi-layered graphene wire including a multi-layered graphene layer having a 15 preset impurity doped therein, a second multi-layered graphene wire formed o n the same layer as the first multi-layered graphene wire above the substrate, the second multi-layered graphene wire being formed wider than the first multi-layered 20 graphene wire and including a multi-layered graphene layer in an edge portion of which the impurity is selectively doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene 25 wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.-21 -
The device according to claim 6, wherein each of the first and second multi-layered graphene wires is formed by sequentially laminating a catalytic underlying layer, catalytic metal layer and the multi- 5 layered graphene layer from the lower-layer side.
The device according to claim 6, wherein the impurity is one of Br, I, F and Cl.
The device according to claim 6, wherein the lower-layer contact is connected to the semiconductor 10 element via a wire on the lower-layer side of the multi-layered graphene wire and the upper-layer contact is connected to a wire on the upper-layer side of the multi-layered graphene wire.
The device according to claim 6, wherein the 15 first multi-layered graphene wire is arranged in a memory cell region and the second multi-layered graphene wire is arranged in a peripheral circuit region.
A semiconductor device manufacturing method 20 comprising: forming an interlayer insulating film and lower- layer contact on a substrate having semiconductor elements formed therein, forming a multi-layered graphene wiring structure 25 including a multi-layered graphene layer on the interlayer insulating film and lower-layer contact, forming a first multi-layered graphene wire-22-connected to the lower-layer contact and a second multi-layered graphene wire that is not connected to the lower-layer contact by processing the multi-layered graphene wiring structure to a wiring pattern, a doping 5 amount of a halogen-series element in the first multi- layered graphene wire being set larger than a doping amount of a halogen-series element in the second multi- layered graphene wire, and forming an upper-layer contact connected to the 10 second multi-layered graphene wire.
The method according to claim 11, wherein setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to mask the 15, second multi-layered graphene wire after the first and second multi-layered graphene wires are f o rmed and, in this state, dope a halogen-series element into the first multilayered graphene wire.
The method according to claim 11, wherein 20 setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to set the second multi-layered graphene wire wider than the first multi- layered graphene wire when the first and second multi- 25 layered graphene wires are formed, and dope a wh ole portion of the multi-layered graphene layer of the first multi-layered graphene wire and selectively dope-23-an edge portion of the multi-layered graphene layer of the second multilayered graphene wire by doping the halogen-series element from the side surfaces of the first and second multi-layered graphene wires.
5 14. The method according to claim 11, wherein setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to form the first multi-layered graphene wire by use of an R IE method 10 using halogen-series gas with respect to the multi- layered graphene wiring structure and forming the second multilayered graphene wire by use of an RIE method that does not use the halogen-series gas.
The method according to claim 11, wherein 15 setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to form the first multi-layered graphene wire and the second multi- layered graphene wire that is wider than the first 20 multi-layered graphene wire by processing the multi- layered graphene wiring structure into a wiring pattern by use of an RIE method using halogen-series gas.
The method according to claim 11, wherein forming the m ulti-layered graphene wiring structure is 25 to sequentially laminate a catalytic underlying layer, catalytic metal layer and the multi-layered graphene layer from the lower-layer side.-24 -
The method according to claim 11, wherein one of Br, I, F and Cl is used as the halogen-series element.
18. The method according to claim 11, wherein the 5 lower-layer contact is connected to the semiconductor element v i a w ir e on the lower-layer side of the multi-layered graphene wire and the upper-layer contact is connected to a wire on the upper-layer side of the multi-layered graphene wire.
10 19. The method according to claim 11, wherein the first multi-layered graphene wire is arranged in a memory cell region and the second multi-layered graphene wire is arranged in a peripheral circuit region.
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with dual multi-layered graphene wires (doped/undoped, same layer)
Materials described outside the worked examples.
multi-layered graphene (impurity-doped)
multi-layered graphene (undoped)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 0.5 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,117,738Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cr o ss-sectional view showing the schematic structure of a semiconductor device according 20 to a first embodiment.
FIGS. 2A to 2E are cross-sectional views showing manufacturing steps of a semiconductor device according to a second embodiment. FI G. 3 is a cross-sectional …
FIG. 3.
FIGS. 4A, 4B are cross-sectional views showing-3-manufacturing steps of the semiconductor device of
FIG. 5 is a cross-sectional view for illustrating a manufacturing process of a semiconductor device 5 according to a fourth embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a substrate having semiconductor elements formed therein, 5 a first graphene wire formed above the substrate, the first graphene wire including a multilayered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the 10 substrate, the second graphene wire including a multi- layered graphene layer into which the impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire,.and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.
The device according to claim 1, wherein each of the first and second multi-layered graphene wires is 20 formed by sequentially laminating a catalytic underlying layer, catalytic metal layer and the multi- layered graphene layer from the lower-layer side.
The device according to claim 1, wherein the impurity is one of Br, I, F and Cl.
25 4. The device according to claim 1, wherein the lower-layer contact is connected to the semiconductor element via a wire on the lower-layer side of the-20-multi-layered graphene wire and the upper-layer contact is connected to a wire on the upper-layer side of the multilayered graphene wire.
The device according to claim 1, wherein the 5 first multi-layered graphene wire is arranged in a memory cell region and the second multi-layered graphene wire is arranged in a peripheral circuit region.
A semiconductor device comprising: 10 a substrate having semiconductor elements formed therein, a first multi-layered graphene wire formed above the substrate, the first multi-layered graphene wire including a multi-layered graphene layer having a 15 preset impurity doped therein, a second multi-layered graphene wire formed o n the same layer as the first multi-layered graphene wire above the substrate, the second multi-layered graphene wire being formed wider than the first multi-layered 20 graphene wire and including a multi-layered graphene layer in an edge portion of which the impurity is selectively doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene 25 wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.-21 -
The device according to claim 6, wherein each of the first and second multi-layered graphene wires is formed by sequentially laminating a catalytic underlying layer, catalytic metal layer and the multi- 5 layered graphene layer from the lower-layer side.
The device according to claim 6, wherein the impurity is one of Br, I, F and Cl.
The device according to claim 6, wherein the lower-layer contact is connected to the semiconductor 10 element via a wire on the lower-layer side of the multi-layered graphene wire and the upper-layer contact is connected to a wire on the upper-layer side of the multi-layered graphene wire.
The device according to claim 6, wherein the 15 first multi-layered graphene wire is arranged in a memory cell region and the second multi-layered graphene wire is arranged in a peripheral circuit region.
A semiconductor device manufacturing method 20 comprising: forming an interlayer insulating film and lower- layer contact on a substrate having semiconductor elements formed therein, forming a multi-layered graphene wiring structure 25 including a multi-layered graphene layer on the interlayer insulating film and lower-layer contact, forming a first multi-layered graphene wire-22-connected to the lower-layer contact and a second multi-layered graphene wire that is not connected to the lower-layer contact by processing the multi-layered graphene wiring structure to a wiring pattern, a doping 5 amount of a halogen-series element in the first multi- layered graphene wire being set larger than a doping amount of a halogen-series element in the second multi- layered graphene wire, and forming an upper-layer contact connected to the 10 second multi-layered graphene wire.
The method according to claim 11, wherein setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to mask the 15, second multi-layered graphene wire after the first and second multi-layered graphene wires are f o rmed and, in this state, dope a halogen-series element into the first multilayered graphene wire.
The method according to claim 11, wherein 20 setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to set the second multi-layered graphene wire wider than the first multi- layered graphene wire when the first and second multi- 25 layered graphene wires are formed, and dope a wh ole portion of the multi-layered graphene layer of the first multi-layered graphene wire and selectively dope-23-an edge portion of the multi-layered graphene layer of the second multilayered graphene wire by doping the halogen-series element from the side surfaces of the first and second multi-layered graphene wires.
5 14. The method according to claim 11, wherein setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to form the first multi-layered graphene wire by use of an R IE method 10 using halogen-series gas with respect to the multi- layered graphene wiring structure and forming the second multilayered graphene wire by use of an RIE method that does not use the halogen-series gas.
The method according to claim 11, wherein 15 setting the doping amount in the first multilayered graphene wire larger than the doping amount in the second multi-layered graphene wire is to form the first multi-layered graphene wire and the second multi- layered graphene wire that is wider than the first 20 multi-layered graphene wire by processing the multi- layered graphene wiring structure into a wiring pattern by use of an RIE method using halogen-series gas.
The method according to claim 11, wherein forming the m ulti-layered graphene wiring structure is 25 to sequentially laminate a catalytic underlying layer, catalytic metal layer and the multi-layered graphene layer from the lower-layer side.-24 -
The method according to claim 11, wherein one of Br, I, F and Cl is used as the halogen-series element.
18. The method according to claim 11, wherein the 5 lower-layer contact is connected to the semiconductor element v i a w ir e on the lower-layer side of the multi-layered graphene wire and the upper-layer contact is connected to a wire on the upper-layer side of the multi-layered graphene wire.
10 19. The method according to claim 11, wherein the first multi-layered graphene wire is arranged in a memory cell region and the second multi-layered graphene wire is arranged in a peripheral circuit region.
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with dual multi-layered graphene wires (doped/undoped, same layer)
Materials described outside the worked examples.
multi-layered graphene (impurity-doped)
multi-layered graphene (undoped)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 0.5 nm | — |
Related documents with shared materials, methods, properties, or citations.
semiconductor device with dual multi-layered graphene wires (fully doped narrow/edge-doped wide)
catalytic underlying layer
catalytic metal layer
Br
I
F
Cl
halogen-series element (generic)
Ti, Ta, Ru, W and nitrides thereof (catalytic underlying layer materials)
Co, Ni, Fe, Ru, Cu and alloys/carbides thereof (catalytic metal materials)
SiN surface protection layer
SiN
SiO₂ surface protection layer
SiO₂
METHOD OF FABRICATING GRAPHENE NANO-MESH
semiconductor device with dual multi-layered graphene wires (fully doped narrow/edge-doped wide)
catalytic underlying layer
catalytic metal layer
Br
I
F
Cl
halogen-series element (generic)
Ti, Ta, Ru, W and nitrides thereof (catalytic underlying layer materials)
Co, Ni, Fe, Ru, Cu and alloys/carbides thereof (catalytic metal materials)
SiN surface protection layer
SiN
SiO₂ surface protection layer
SiO₂
METHOD OF FABRICATING GRAPHENE NANO-MESH
semiconductor device with dual multi-layered graphene wires (fully doped narrow/edge-doped wide)
catalytic underlying layer
catalytic metal layer
Br
I
F
Cl
halogen-series element (generic)
Ti, Ta, Ru, W and nitrides thereof (catalytic underlying layer materials)
Co, Ni, Fe, Ru, Cu and alloys/carbides thereof (catalytic metal materials)
SiN surface protection layer
SiN
SiO₂ surface protection layer
SiO₂
METHOD OF FABRICATING GRAPHENE NANO-MESH
semiconductor device with dual multi-layered graphene wires (fully doped narrow/edge-doped wide)
catalytic underlying layer
catalytic metal layer
Br
I
F
Cl
halogen-series element (generic)
Ti, Ta, Ru, W and nitrides thereof (catalytic underlying layer materials)
Co, Ni, Fe, Ru, Cu and alloys/carbides thereof (catalytic metal materials)
SiN surface protection layer
SiN
SiO₂ surface protection layer
SiO₂
METHOD OF FABRICATING GRAPHENE NANO-MESH