Patent
US 9,923,060GALLIUM NITRIDE APPARATUS WITH A TRAP RICH REGION
Shrenik Deliwala
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,923,060Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device having an inversion layer with reduced parasitic effects, the electronic device comprising: a silicon substrate; a GaN layer above the silicon substrate, the GaN layer forming a circuit device; an interface between the GaN layer and the silicon substrate; and a semiconductor trap region extending from the interface and into the silicon substrate, the trap region including traps respectively comprising one or more broken bonds in a crystalline lattice structure of the semiconductor trap region of the silicon substrate and the traps being configured to substantially immobilize charge carriers in the trap region. Currently amended
The electronic device according to claim 1, further comprising: a buffer layer between the GaN layer and the silicon substrate, wherein the interface is between the buffer layer and the silicon substrate. Previously presented
The electronic device according to claim 1, wherein the silicon substrate comprises high resistivity silicon. Original
The electronic device according to claim 1, wherein the semiconductor trap region is formed globally across a wafer providing the silicon substrate. Previously presented
The electronic device according to claim 1, wherein the semiconductor trap region provides a higher sheet resistance than a region of the silicon substrate underlying the semiconductor trap region. Previously presented
The electronic device of claim 1, wherein the semiconductor trap region extends at least micrometers into the silicon substrate from the interface between the GaN layer and the silicon substrate. Previously presented
Canceled
The electronic device according to clai m 2, wherein the buffer layer comprises a plurality of layers. Original
A method of forming an electronic device with reduced parasitic effects in an inversion layer, the method comprising: forming a buffer on a silicon substrate; epitaxially growing a GaN layer on the buffer and silicon substrate; and forming a semiconductor trap region between the GaN and the silicon substrate by cold melting a portion of the silicon substrate using a laser, the semiconductor trap region extending into the silicon substrate from an interface between the GaN layer and the silicon substrate. Currently amended
The method according to claim 10, wherein forming the semiconductor trap region comprises: breaking one or more bonds in a crystalline lattice structure of the semiconductor trap region to form traps configured to substantially immobilize charge carriers in the trap region. Currently amended
The method according to claim 10, wherein the silicon substrate comprises a high resistivity silicon wafer. Previously presented
The method according to claim 10, wherein forming [[a]] the semiconductor trap region extending into the silicon substrate comprises using a laser providing a fluence of between 1 and 100 mJ/cm2. Currently amended
An electronic device having an inversion layer with reduced parasitic effects, the electronic device comprising: a silicon substrate; a GaN layer above the silicon substrate, the GaN layer forming a circuit device; an interface between the GaN layer and the silicon substrate; and a means for using traps respectively including one or more broken bonds in the crystalline lattice structure of a semiconductor trap region and substantially immobilizing charge carriers and mitigating an inversion layer on at least the interface. Currently amended
The electronic device according to claim 16, further comprising: a buffer layer between the GaN layer and the silicon substrate, wherein the interface is between the buffer layer and the silicon substrate. Previously presented
The electronic device according to claim 16 wherein the means for substantially immobilizing charge carriers extends into the silicon substrate. Previously presented
The electronic device according to claim 16, wherein the silicon substrate comprises high resistivity silicon. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si electronic device with trap rich region
Materials described outside the worked examples.
high resistivity silicon substrate
Si
GaN layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
sheet resistance of trap region at least 50 Ohms/square higher than underlying Si substrate | ≥ 50 Ohms/square | semiconductor trap region |
sheet resistance of trap region at least 225 Ohms/square higher than underlying Si substrate |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,923,060Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device having an inversion layer with reduced parasitic effects, the electronic device comprising: a silicon substrate; a GaN layer above the silicon substrate, the GaN layer forming a circuit device; an interface between the GaN layer and the silicon substrate; and a semiconductor trap region extending from the interface and into the silicon substrate, the trap region including traps respectively comprising one or more broken bonds in a crystalline lattice structure of the semiconductor trap region of the silicon substrate and the traps being configured to substantially immobilize charge carriers in the trap region. Currently amended
The electronic device according to claim 1, further comprising: a buffer layer between the GaN layer and the silicon substrate, wherein the interface is between the buffer layer and the silicon substrate. Previously presented
The electronic device according to claim 1, wherein the silicon substrate comprises high resistivity silicon. Original
The electronic device according to claim 1, wherein the semiconductor trap region is formed globally across a wafer providing the silicon substrate. Previously presented
The electronic device according to claim 1, wherein the semiconductor trap region provides a higher sheet resistance than a region of the silicon substrate underlying the semiconductor trap region. Previously presented
The electronic device of claim 1, wherein the semiconductor trap region extends at least micrometers into the silicon substrate from the interface between the GaN layer and the silicon substrate. Previously presented
Canceled
The electronic device according to clai m 2, wherein the buffer layer comprises a plurality of layers. Original
A method of forming an electronic device with reduced parasitic effects in an inversion layer, the method comprising: forming a buffer on a silicon substrate; epitaxially growing a GaN layer on the buffer and silicon substrate; and forming a semiconductor trap region between the GaN and the silicon substrate by cold melting a portion of the silicon substrate using a laser, the semiconductor trap region extending into the silicon substrate from an interface between the GaN layer and the silicon substrate. Currently amended
The method according to claim 10, wherein forming the semiconductor trap region comprises: breaking one or more bonds in a crystalline lattice structure of the semiconductor trap region to form traps configured to substantially immobilize charge carriers in the trap region. Currently amended
The method according to claim 10, wherein the silicon substrate comprises a high resistivity silicon wafer. Previously presented
The method according to claim 10, wherein forming [[a]] the semiconductor trap region extending into the silicon substrate comprises using a laser providing a fluence of between 1 and 100 mJ/cm2. Currently amended
An electronic device having an inversion layer with reduced parasitic effects, the electronic device comprising: a silicon substrate; a GaN layer above the silicon substrate, the GaN layer forming a circuit device; an interface between the GaN layer and the silicon substrate; and a means for using traps respectively including one or more broken bonds in the crystalline lattice structure of a semiconductor trap region and substantially immobilizing charge carriers and mitigating an inversion layer on at least the interface. Currently amended
The electronic device according to claim 16, further comprising: a buffer layer between the GaN layer and the silicon substrate, wherein the interface is between the buffer layer and the silicon substrate. Previously presented
The electronic device according to claim 16 wherein the means for substantially immobilizing charge carriers extends into the silicon substrate. Previously presented
The electronic device according to claim 16, wherein the silicon substrate comprises high resistivity silicon. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si electronic device with trap rich region
Materials described outside the worked examples.
high resistivity silicon substrate
Si
GaN layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
sheet resistance of trap region at least 50 Ohms/square higher than underlying Si substrate | ≥ 50 Ohms/square | semiconductor trap region |
sheet resistance of trap region at least 225 Ohms/square higher than underlying Si substrate |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,923,060Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device having an inversion layer with reduced parasitic effects, the electronic device comprising: a silicon substrate; a GaN layer above the silicon substrate, the GaN layer forming a circuit device; an interface between the GaN layer and the silicon substrate; and a semiconductor trap region extending from the interface and into the silicon substrate, the trap region including traps respectively comprising one or more broken bonds in a crystalline lattice structure of the semiconductor trap region of the silicon substrate and the traps being configured to substantially immobilize charge carriers in the trap region. Currently amended
The electronic device according to claim 1, further comprising: a buffer layer between the GaN layer and the silicon substrate, wherein the interface is between the buffer layer and the silicon substrate. Previously presented
The electronic device according to claim 1, wherein the silicon substrate comprises high resistivity silicon. Original
The electronic device according to claim 1, wherein the semiconductor trap region is formed globally across a wafer providing the silicon substrate. Previously presented
The electronic device according to claim 1, wherein the semiconductor trap region provides a higher sheet resistance than a region of the silicon substrate underlying the semiconductor trap region. Previously presented
The electronic device of claim 1, wherein the semiconductor trap region extends at least micrometers into the silicon substrate from the interface between the GaN layer and the silicon substrate. Previously presented
Canceled
The electronic device according to clai m 2, wherein the buffer layer comprises a plurality of layers. Original
A method of forming an electronic device with reduced parasitic effects in an inversion layer, the method comprising: forming a buffer on a silicon substrate; epitaxially growing a GaN layer on the buffer and silicon substrate; and forming a semiconductor trap region between the GaN and the silicon substrate by cold melting a portion of the silicon substrate using a laser, the semiconductor trap region extending into the silicon substrate from an interface between the GaN layer and the silicon substrate. Currently amended
The method according to claim 10, wherein forming the semiconductor trap region comprises: breaking one or more bonds in a crystalline lattice structure of the semiconductor trap region to form traps configured to substantially immobilize charge carriers in the trap region. Currently amended
The method according to claim 10, wherein the silicon substrate comprises a high resistivity silicon wafer. Previously presented
The method according to claim 10, wherein forming [[a]] the semiconductor trap region extending into the silicon substrate comprises using a laser providing a fluence of between 1 and 100 mJ/cm2. Currently amended
An electronic device having an inversion layer with reduced parasitic effects, the electronic device comprising: a silicon substrate; a GaN layer above the silicon substrate, the GaN layer forming a circuit device; an interface between the GaN layer and the silicon substrate; and a means for using traps respectively including one or more broken bonds in the crystalline lattice structure of a semiconductor trap region and substantially immobilizing charge carriers and mitigating an inversion layer on at least the interface. Currently amended
The electronic device according to claim 16, further comprising: a buffer layer between the GaN layer and the silicon substrate, wherein the interface is between the buffer layer and the silicon substrate. Previously presented
The electronic device according to claim 16 wherein the means for substantially immobilizing charge carriers extends into the silicon substrate. Previously presented
The electronic device according to claim 16, wherein the silicon substrate comprises high resistivity silicon. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si electronic device with trap rich region
Materials described outside the worked examples.
high resistivity silicon substrate
Si
GaN layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
sheet resistance of trap region at least 50 Ohms/square higher than underlying Si substrate | ≥ 50 Ohms/square | semiconductor trap region |
sheet resistance of trap region at least 225 Ohms/square higher than underlying Si substrate |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,923,060Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device having an inversion layer with reduced parasitic effects, the electronic device comprising: a silicon substrate; a GaN layer above the silicon substrate, the GaN layer forming a circuit device; an interface between the GaN layer and the silicon substrate; and a semiconductor trap region extending from the interface and into the silicon substrate, the trap region including traps respectively comprising one or more broken bonds in a crystalline lattice structure of the semiconductor trap region of the silicon substrate and the traps being configured to substantially immobilize charge carriers in the trap region. Currently amended
The electronic device according to claim 1, further comprising: a buffer layer between the GaN layer and the silicon substrate, wherein the interface is between the buffer layer and the silicon substrate. Previously presented
The electronic device according to claim 1, wherein the silicon substrate comprises high resistivity silicon. Original
The electronic device according to claim 1, wherein the semiconductor trap region is formed globally across a wafer providing the silicon substrate. Previously presented
The electronic device according to claim 1, wherein the semiconductor trap region provides a higher sheet resistance than a region of the silicon substrate underlying the semiconductor trap region. Previously presented
The electronic device of claim 1, wherein the semiconductor trap region extends at least micrometers into the silicon substrate from the interface between the GaN layer and the silicon substrate. Previously presented
Canceled
The electronic device according to clai m 2, wherein the buffer layer comprises a plurality of layers. Original
A method of forming an electronic device with reduced parasitic effects in an inversion layer, the method comprising: forming a buffer on a silicon substrate; epitaxially growing a GaN layer on the buffer and silicon substrate; and forming a semiconductor trap region between the GaN and the silicon substrate by cold melting a portion of the silicon substrate using a laser, the semiconductor trap region extending into the silicon substrate from an interface between the GaN layer and the silicon substrate. Currently amended
The method according to claim 10, wherein forming the semiconductor trap region comprises: breaking one or more bonds in a crystalline lattice structure of the semiconductor trap region to form traps configured to substantially immobilize charge carriers in the trap region. Currently amended
The method according to claim 10, wherein the silicon substrate comprises a high resistivity silicon wafer. Previously presented
The method according to claim 10, wherein forming [[a]] the semiconductor trap region extending into the silicon substrate comprises using a laser providing a fluence of between 1 and 100 mJ/cm2. Currently amended
An electronic device having an inversion layer with reduced parasitic effects, the electronic device comprising: a silicon substrate; a GaN layer above the silicon substrate, the GaN layer forming a circuit device; an interface between the GaN layer and the silicon substrate; and a means for using traps respectively including one or more broken bonds in the crystalline lattice structure of a semiconductor trap region and substantially immobilizing charge carriers and mitigating an inversion layer on at least the interface. Currently amended
The electronic device according to claim 16, further comprising: a buffer layer between the GaN layer and the silicon substrate, wherein the interface is between the buffer layer and the silicon substrate. Previously presented
The electronic device according to claim 16 wherein the means for substantially immobilizing charge carriers extends into the silicon substrate. Previously presented
The electronic device according to claim 16, wherein the silicon substrate comprises high resistivity silicon. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si electronic device with trap rich region
Materials described outside the worked examples.
high resistivity silicon substrate
Si
GaN layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
sheet resistance of trap region at least 50 Ohms/square higher than underlying Si substrate | ≥ 50 Ohms/square | semiconductor trap region |
sheet resistance of trap region at least 225 Ohms/square higher than underlying Si substrate |
Related documents with shared materials, methods, properties, or citations.
semiconductor trap region
buffer layer
AlN buffer layer
AlN
AlGaN
AlGaN/GaN superlattice buffer
semiconductor trap region |
sheet resistance of trap region between 50–225 Ohms/square higher than underlying Si substrate | 50–225 Ohms/square | semiconductor trap region |
Temperature | ≤ 1 K | — |
Thickness | ≥ 380 nm | — |
Thickness | ≥ 50 µm | — |
Thickness | ≤ 380 nm | — |
Thickness | ≥ 400 nm | — |
semiconductor trap region
buffer layer
AlN buffer layer
AlN
AlGaN
AlGaN/GaN superlattice buffer
semiconductor trap region |
sheet resistance of trap region between 50–225 Ohms/square higher than underlying Si substrate | 50–225 Ohms/square | semiconductor trap region |
Temperature | ≤ 1 K | — |
Thickness | ≥ 380 nm | — |
Thickness | ≥ 50 µm | — |
Thickness | ≤ 380 nm | — |
Thickness | ≥ 400 nm | — |
semiconductor trap region
buffer layer
AlN buffer layer
AlN
AlGaN
AlGaN/GaN superlattice buffer
semiconductor trap region |
sheet resistance of trap region between 50–225 Ohms/square higher than underlying Si substrate | 50–225 Ohms/square | semiconductor trap region |
Temperature | ≤ 1 K | — |
Thickness | ≥ 380 nm | — |
Thickness | ≥ 50 µm | — |
Thickness | ≤ 380 nm | — |
Thickness | ≥ 400 nm | — |
semiconductor trap region
buffer layer
AlN buffer layer
AlN
AlGaN
AlGaN/GaN superlattice buffer
semiconductor trap region |
sheet resistance of trap region between 50–225 Ohms/square higher than underlying Si substrate | 50–225 Ohms/square | semiconductor trap region |
Temperature | ≤ 1 K | — |
Thickness | ≥ 380 nm | — |
Thickness | ≥ 50 µm | — |
Thickness | ≤ 380 nm | — |
Thickness | ≥ 400 nm | — |