Patent
US 8,987,722SELF-ALIGNED BOTTOM-GATED GRAPHENE DEVICES
Damon FARMER
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,987,722Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional diagram i llustrating a carbon-based gate electrode layer having been deposited or grown on a substrate according to one embodiment …
FIG. 2 is a cross-sectional diagram i llustrating a gate dielect n c layer having been formed on the carbon-based gate electrode layer according to one …
FIG. 3 is a cross-sectional diagram i llustrating a graphene channel material having been formed on the gate dielect n c layer according to one embodiment of …
FIG. 4 is a cross-sectional diagram i llustrating a masking mate n al patterned over the graphene channel material according to one embodiment of the present …
FIG. 5 is a cross-sectional diagram i llustrating a gate stack having been formed on the substrate according to one embodiment of the present invention; [0013]
FIG. 6 is a cross-sectional diagram i llustrating an i nsulating material having been conformally deposited on the gate stack and the surface of the substrate …
FIG. 7 i s a cross-sectional diagram i llustrating a set of spacers having been formed from the i nsulating mate n al according to one embodiment of the …
FIG. 8 is a cross-sectional diagram i llustrating another structure where the spacers of
FIG. 9 i s a cross-sectional diagram i llustrating a conductive mate n al having been conformally deposited onto and over the surface of the substrate, the …
FIG. 10 is a cross-sectional diagram i llustrating a conductive mate n al having been conformally deposited onto and over the surface of the oxide layer, the …
FIG. 11 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 12 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 13 is a cross-sectional diagram i llustrating another structure where a planarizing mate n al has been formed over the structure shown in
FIG. 14 is a cross-sectional diagram i llustrating another structure where a planarizing mate n al has been formed over the structure shown in
FIG. 15 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 16 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 17 i s an operational flow diagram i llustrating one example of a process for fabricating a carbon-based semiconductor structure; and [0025]
FIG. 18 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
The carbon-based semiconductor structure of claim [[1]]5, further comprising: a set of spacers formed on at least a vertical portion of the gate stack.
The carbon-based semiconductor structure of claim 2, wherein the set of spacers comprises a height that is below a bottom surface of the carbon-based channel and above top surface of the carbon-based gate electrode.
The carbon-based semiconductor structure of claim 2 --furher SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.1.svg 1.02 6.48 Black and white and a second portion of the carbon-based channel.
5. T carn ase seicondutor strucur of cli 1,frte SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.2.svg 0.16 6.41 Black and white com p risin g: a substrate; and a g ate stack, the g ate stack comprising a carbon-based g ate electrode formed on the substrate; a g ate dielectric formed on the carbon-based g ate electrode; a carbon-based channel on the g ate dielectric; a source electrode contacting a first portion of the substrate, a first [[a]] portion of the gate dielectric, and a first portion of the carbon-based channel; and 2 of 13 App l. No. 14/031,126 Docket No. Y O R₉₂₀₁₃₀₁₉₀US₂ Reply to Office Action of a drain electrode contacting a second portion of the substrate, a second a portion of the gate dielectric, and a second portion of the carbon-based channel.
The carbon-based semiconductor structure of claim [[1]]5, further comprising: an oxide layer formed on the substrate.
The carbon-based semiconductor structure of claim 6, further SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.3.svg 1.59 6.5 Black and white a- program pr oduct for fabricating an integrated circuit structure, the computer program pr oduct comprising a computer readable storage medium havin g progr am instructions embodied therewith, wherein the computer readable storage medium is not a transitory si gn al p er se, the p rogram instructions executable by an information p rocessin g system to cause the information p rocessin g s ystem eenfgured to perform a method comprising: forming a carbon-based gate electrode layer on a substrate; forming a gate dielectric layer on the carbon-based gate electrode layer; [[and]] forming a carbon-based channel layer on the gate dielectric layer[[.]]; p atternin g a mask on the carbon-based channe l; and removing p ortions of the carbon-based g ate electrode layer, the g ate dielectric layer, and the carbon-based channel layer unprotected by the mask, wherein the removing forms a gate stack under the mask com p risin g remaining p ortions of the carbon-based g ate electrode layer, the g ate dielectric layer, and the carbon-based channel layer.
3 of 13 App l. No. 14/031,126 Docket No. Y O R₉₂₀₁₃₀₁₉₀US₂ Reply to Office Action of SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.4.svg 0.16 6.48 Black and white progra m product of claim [[9]]8, the method further comprising: forming an insulating layer over the substrate, the gate stack, and the mask; and removing a portion of the insulating layer, the removing forming a set of spacers on at least a vertical portion of the gate stack. SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.5.svg 0.16 6.17 Black and white canceled
progra m product of claim 10, the method further comprising: forming a conductive layer over the substrate, the spacers, the gate stack, and the mask; removing the mask; and removing a horizontal portion of the conductive layer over the gate stack, the removing defining and separating a source electrode and a drain electrode.
An integrated circuit comprising: a carbon-based semiconductor device, the carbon-based semiconductor device comprising: a substrate; and a gate stack, the gate stack comprising at least a carbon-based gate electrode formed on the substrate; a gate dielectric formed on the carbon-based gate electrode; [[and]] a carbon-based channel on the gate dielectric[[.]]; a source electrode contactin g a first portion of the substrate, a first a portion of the g ate dielectric, and a first portion of the carbon-based channe l; and a drain electrode contacting a second portion of the substrate, a second a portion of the g ate dielectric, and a second portion of the carbon-based channel.
The integrated circuit of claim 12, wherein the carbon-based semiconductor device further comprises: a set of spacers formed on at least a vertical portion of the gate stack.
The integrated circuit of claim 12, wherein the carbon-based semiconductor device further comprises: an oxide layer formed on the substrate.
Layer stacks claimed or described, ordered top of device to substrate.
carbon-based semiconductor structure (bottom-gated)
integrated circuit with carbon-based semiconductor device (bottom-gated)
Materials described outside the worked examples.
carbon-based gate electrode (graphene or graphite)
gate dielectric
carbon-based channel (graphene)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 3–500 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,987,722Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional diagram i llustrating a carbon-based gate electrode layer having been deposited or grown on a substrate according to one embodiment …
FIG. 2 is a cross-sectional diagram i llustrating a gate dielect n c layer having been formed on the carbon-based gate electrode layer according to one …
FIG. 3 is a cross-sectional diagram i llustrating a graphene channel material having been formed on the gate dielect n c layer according to one embodiment of …
FIG. 4 is a cross-sectional diagram i llustrating a masking mate n al patterned over the graphene channel material according to one embodiment of the present …
FIG. 5 is a cross-sectional diagram i llustrating a gate stack having been formed on the substrate according to one embodiment of the present invention; [0013]
FIG. 6 is a cross-sectional diagram i llustrating an i nsulating material having been conformally deposited on the gate stack and the surface of the substrate …
FIG. 7 i s a cross-sectional diagram i llustrating a set of spacers having been formed from the i nsulating mate n al according to one embodiment of the …
FIG. 8 is a cross-sectional diagram i llustrating another structure where the spacers of
FIG. 9 i s a cross-sectional diagram i llustrating a conductive mate n al having been conformally deposited onto and over the surface of the substrate, the …
FIG. 10 is a cross-sectional diagram i llustrating a conductive mate n al having been conformally deposited onto and over the surface of the oxide layer, the …
FIG. 11 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 12 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 13 is a cross-sectional diagram i llustrating another structure where a planarizing mate n al has been formed over the structure shown in
FIG. 14 is a cross-sectional diagram i llustrating another structure where a planarizing mate n al has been formed over the structure shown in
FIG. 15 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 16 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 17 i s an operational flow diagram i llustrating one example of a process for fabricating a carbon-based semiconductor structure; and [0025]
FIG. 18 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
The carbon-based semiconductor structure of claim [[1]]5, further comprising: a set of spacers formed on at least a vertical portion of the gate stack.
The carbon-based semiconductor structure of claim 2, wherein the set of spacers comprises a height that is below a bottom surface of the carbon-based channel and above top surface of the carbon-based gate electrode.
The carbon-based semiconductor structure of claim 2 --furher SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.1.svg 1.02 6.48 Black and white and a second portion of the carbon-based channel.
5. T carn ase seicondutor strucur of cli 1,frte SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.2.svg 0.16 6.41 Black and white com p risin g: a substrate; and a g ate stack, the g ate stack comprising a carbon-based g ate electrode formed on the substrate; a g ate dielectric formed on the carbon-based g ate electrode; a carbon-based channel on the g ate dielectric; a source electrode contacting a first portion of the substrate, a first [[a]] portion of the gate dielectric, and a first portion of the carbon-based channel; and 2 of 13 App l. No. 14/031,126 Docket No. Y O R₉₂₀₁₃₀₁₉₀US₂ Reply to Office Action of a drain electrode contacting a second portion of the substrate, a second a portion of the gate dielectric, and a second portion of the carbon-based channel.
The carbon-based semiconductor structure of claim [[1]]5, further comprising: an oxide layer formed on the substrate.
The carbon-based semiconductor structure of claim 6, further SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.3.svg 1.59 6.5 Black and white a- program pr oduct for fabricating an integrated circuit structure, the computer program pr oduct comprising a computer readable storage medium havin g progr am instructions embodied therewith, wherein the computer readable storage medium is not a transitory si gn al p er se, the p rogram instructions executable by an information p rocessin g system to cause the information p rocessin g s ystem eenfgured to perform a method comprising: forming a carbon-based gate electrode layer on a substrate; forming a gate dielectric layer on the carbon-based gate electrode layer; [[and]] forming a carbon-based channel layer on the gate dielectric layer[[.]]; p atternin g a mask on the carbon-based channe l; and removing p ortions of the carbon-based g ate electrode layer, the g ate dielectric layer, and the carbon-based channel layer unprotected by the mask, wherein the removing forms a gate stack under the mask com p risin g remaining p ortions of the carbon-based g ate electrode layer, the g ate dielectric layer, and the carbon-based channel layer.
3 of 13 App l. No. 14/031,126 Docket No. Y O R₉₂₀₁₃₀₁₉₀US₂ Reply to Office Action of SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.4.svg 0.16 6.48 Black and white progra m product of claim [[9]]8, the method further comprising: forming an insulating layer over the substrate, the gate stack, and the mask; and removing a portion of the insulating layer, the removing forming a set of spacers on at least a vertical portion of the gate stack. SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.5.svg 0.16 6.17 Black and white canceled
progra m product of claim 10, the method further comprising: forming a conductive layer over the substrate, the spacers, the gate stack, and the mask; removing the mask; and removing a horizontal portion of the conductive layer over the gate stack, the removing defining and separating a source electrode and a drain electrode.
An integrated circuit comprising: a carbon-based semiconductor device, the carbon-based semiconductor device comprising: a substrate; and a gate stack, the gate stack comprising at least a carbon-based gate electrode formed on the substrate; a gate dielectric formed on the carbon-based gate electrode; [[and]] a carbon-based channel on the gate dielectric[[.]]; a source electrode contactin g a first portion of the substrate, a first a portion of the g ate dielectric, and a first portion of the carbon-based channe l; and a drain electrode contacting a second portion of the substrate, a second a portion of the g ate dielectric, and a second portion of the carbon-based channel.
The integrated circuit of claim 12, wherein the carbon-based semiconductor device further comprises: a set of spacers formed on at least a vertical portion of the gate stack.
The integrated circuit of claim 12, wherein the carbon-based semiconductor device further comprises: an oxide layer formed on the substrate.
Layer stacks claimed or described, ordered top of device to substrate.
carbon-based semiconductor structure (bottom-gated)
integrated circuit with carbon-based semiconductor device (bottom-gated)
Materials described outside the worked examples.
carbon-based gate electrode (graphene or graphite)
gate dielectric
carbon-based channel (graphene)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 3–500 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,987,722Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional diagram i llustrating a carbon-based gate electrode layer having been deposited or grown on a substrate according to one embodiment …
FIG. 2 is a cross-sectional diagram i llustrating a gate dielect n c layer having been formed on the carbon-based gate electrode layer according to one …
FIG. 3 is a cross-sectional diagram i llustrating a graphene channel material having been formed on the gate dielect n c layer according to one embodiment of …
FIG. 4 is a cross-sectional diagram i llustrating a masking mate n al patterned over the graphene channel material according to one embodiment of the present …
FIG. 5 is a cross-sectional diagram i llustrating a gate stack having been formed on the substrate according to one embodiment of the present invention; [0013]
FIG. 6 is a cross-sectional diagram i llustrating an i nsulating material having been conformally deposited on the gate stack and the surface of the substrate …
FIG. 7 i s a cross-sectional diagram i llustrating a set of spacers having been formed from the i nsulating mate n al according to one embodiment of the …
FIG. 8 is a cross-sectional diagram i llustrating another structure where the spacers of
FIG. 9 i s a cross-sectional diagram i llustrating a conductive mate n al having been conformally deposited onto and over the surface of the substrate, the …
FIG. 10 is a cross-sectional diagram i llustrating a conductive mate n al having been conformally deposited onto and over the surface of the oxide layer, the …
FIG. 11 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 12 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 13 is a cross-sectional diagram i llustrating another structure where a planarizing mate n al has been formed over the structure shown in
FIG. 14 is a cross-sectional diagram i llustrating another structure where a planarizing mate n al has been formed over the structure shown in
FIG. 15 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 16 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 17 i s an operational flow diagram i llustrating one example of a process for fabricating a carbon-based semiconductor structure; and [0025]
FIG. 18 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
The carbon-based semiconductor structure of claim [[1]]5, further comprising: a set of spacers formed on at least a vertical portion of the gate stack.
The carbon-based semiconductor structure of claim 2, wherein the set of spacers comprises a height that is below a bottom surface of the carbon-based channel and above top surface of the carbon-based gate electrode.
The carbon-based semiconductor structure of claim 2 --furher SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.1.svg 1.02 6.48 Black and white and a second portion of the carbon-based channel.
5. T carn ase seicondutor strucur of cli 1,frte SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.2.svg 0.16 6.41 Black and white com p risin g: a substrate; and a g ate stack, the g ate stack comprising a carbon-based g ate electrode formed on the substrate; a g ate dielectric formed on the carbon-based g ate electrode; a carbon-based channel on the g ate dielectric; a source electrode contacting a first portion of the substrate, a first [[a]] portion of the gate dielectric, and a first portion of the carbon-based channel; and 2 of 13 App l. No. 14/031,126 Docket No. Y O R₉₂₀₁₃₀₁₉₀US₂ Reply to Office Action of a drain electrode contacting a second portion of the substrate, a second a portion of the gate dielectric, and a second portion of the carbon-based channel.
The carbon-based semiconductor structure of claim [[1]]5, further comprising: an oxide layer formed on the substrate.
The carbon-based semiconductor structure of claim 6, further SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.3.svg 1.59 6.5 Black and white a- program pr oduct for fabricating an integrated circuit structure, the computer program pr oduct comprising a computer readable storage medium havin g progr am instructions embodied therewith, wherein the computer readable storage medium is not a transitory si gn al p er se, the p rogram instructions executable by an information p rocessin g system to cause the information p rocessin g s ystem eenfgured to perform a method comprising: forming a carbon-based gate electrode layer on a substrate; forming a gate dielectric layer on the carbon-based gate electrode layer; [[and]] forming a carbon-based channel layer on the gate dielectric layer[[.]]; p atternin g a mask on the carbon-based channe l; and removing p ortions of the carbon-based g ate electrode layer, the g ate dielectric layer, and the carbon-based channel layer unprotected by the mask, wherein the removing forms a gate stack under the mask com p risin g remaining p ortions of the carbon-based g ate electrode layer, the g ate dielectric layer, and the carbon-based channel layer.
3 of 13 App l. No. 14/031,126 Docket No. Y O R₉₂₀₁₃₀₁₉₀US₂ Reply to Office Action of SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.4.svg 0.16 6.48 Black and white progra m product of claim [[9]]8, the method further comprising: forming an insulating layer over the substrate, the gate stack, and the mask; and removing a portion of the insulating layer, the removing forming a set of spacers on at least a vertical portion of the gate stack. SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.5.svg 0.16 6.17 Black and white canceled
progra m product of claim 10, the method further comprising: forming a conductive layer over the substrate, the spacers, the gate stack, and the mask; removing the mask; and removing a horizontal portion of the conductive layer over the gate stack, the removing defining and separating a source electrode and a drain electrode.
An integrated circuit comprising: a carbon-based semiconductor device, the carbon-based semiconductor device comprising: a substrate; and a gate stack, the gate stack comprising at least a carbon-based gate electrode formed on the substrate; a gate dielectric formed on the carbon-based gate electrode; [[and]] a carbon-based channel on the gate dielectric[[.]]; a source electrode contactin g a first portion of the substrate, a first a portion of the g ate dielectric, and a first portion of the carbon-based channe l; and a drain electrode contacting a second portion of the substrate, a second a portion of the g ate dielectric, and a second portion of the carbon-based channel.
The integrated circuit of claim 12, wherein the carbon-based semiconductor device further comprises: a set of spacers formed on at least a vertical portion of the gate stack.
The integrated circuit of claim 12, wherein the carbon-based semiconductor device further comprises: an oxide layer formed on the substrate.
Layer stacks claimed or described, ordered top of device to substrate.
carbon-based semiconductor structure (bottom-gated)
integrated circuit with carbon-based semiconductor device (bottom-gated)
Materials described outside the worked examples.
carbon-based gate electrode (graphene or graphite)
gate dielectric
carbon-based channel (graphene)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 3–500 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,987,722Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional diagram i llustrating a carbon-based gate electrode layer having been deposited or grown on a substrate according to one embodiment …
FIG. 2 is a cross-sectional diagram i llustrating a gate dielect n c layer having been formed on the carbon-based gate electrode layer according to one …
FIG. 3 is a cross-sectional diagram i llustrating a graphene channel material having been formed on the gate dielect n c layer according to one embodiment of …
FIG. 4 is a cross-sectional diagram i llustrating a masking mate n al patterned over the graphene channel material according to one embodiment of the present …
FIG. 5 is a cross-sectional diagram i llustrating a gate stack having been formed on the substrate according to one embodiment of the present invention; [0013]
FIG. 6 is a cross-sectional diagram i llustrating an i nsulating material having been conformally deposited on the gate stack and the surface of the substrate …
FIG. 7 i s a cross-sectional diagram i llustrating a set of spacers having been formed from the i nsulating mate n al according to one embodiment of the …
FIG. 8 is a cross-sectional diagram i llustrating another structure where the spacers of
FIG. 9 i s a cross-sectional diagram i llustrating a conductive mate n al having been conformally deposited onto and over the surface of the substrate, the …
FIG. 10 is a cross-sectional diagram i llustrating a conductive mate n al having been conformally deposited onto and over the surface of the oxide layer, the …
FIG. 11 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 12 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 13 is a cross-sectional diagram i llustrating another structure where a planarizing mate n al has been formed over the structure shown in
FIG. 14 is a cross-sectional diagram i llustrating another structure where a planarizing mate n al has been formed over the structure shown in
FIG. 15 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 16 is a cross-sectional diagram i llustrating source and drain electrodes having been formed based on the structure illustrated in
FIG. 17 i s an operational flow diagram i llustrating one example of a process for fabricating a carbon-based semiconductor structure; and [0025]
FIG. 18 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
The carbon-based semiconductor structure of claim [[1]]5, further comprising: a set of spacers formed on at least a vertical portion of the gate stack.
The carbon-based semiconductor structure of claim 2, wherein the set of spacers comprises a height that is below a bottom surface of the carbon-based channel and above top surface of the carbon-based gate electrode.
The carbon-based semiconductor structure of claim 2 --furher SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.1.svg 1.02 6.48 Black and white and a second portion of the carbon-based channel.
5. T carn ase seicondutor strucur of cli 1,frte SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.2.svg 0.16 6.41 Black and white com p risin g: a substrate; and a g ate stack, the g ate stack comprising a carbon-based g ate electrode formed on the substrate; a g ate dielectric formed on the carbon-based g ate electrode; a carbon-based channel on the g ate dielectric; a source electrode contacting a first portion of the substrate, a first [[a]] portion of the gate dielectric, and a first portion of the carbon-based channel; and 2 of 13 App l. No. 14/031,126 Docket No. Y O R₉₂₀₁₃₀₁₉₀US₂ Reply to Office Action of a drain electrode contacting a second portion of the substrate, a second a portion of the gate dielectric, and a second portion of the carbon-based channel.
The carbon-based semiconductor structure of claim [[1]]5, further comprising: an oxide layer formed on the substrate.
The carbon-based semiconductor structure of claim 6, further SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.3.svg 1.59 6.5 Black and white a- program pr oduct for fabricating an integrated circuit structure, the computer program pr oduct comprising a computer readable storage medium havin g progr am instructions embodied therewith, wherein the computer readable storage medium is not a transitory si gn al p er se, the p rogram instructions executable by an information p rocessin g system to cause the information p rocessin g s ystem eenfgured to perform a method comprising: forming a carbon-based gate electrode layer on a substrate; forming a gate dielectric layer on the carbon-based gate electrode layer; [[and]] forming a carbon-based channel layer on the gate dielectric layer[[.]]; p atternin g a mask on the carbon-based channe l; and removing p ortions of the carbon-based g ate electrode layer, the g ate dielectric layer, and the carbon-based channel layer unprotected by the mask, wherein the removing forms a gate stack under the mask com p risin g remaining p ortions of the carbon-based g ate electrode layer, the g ate dielectric layer, and the carbon-based channel layer.
3 of 13 App l. No. 14/031,126 Docket No. Y O R₉₂₀₁₃₀₁₉₀US₂ Reply to Office Action of SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.4.svg 0.16 6.48 Black and white progra m product of claim [[9]]8, the method further comprising: forming an insulating layer over the substrate, the gate stack, and the mask; and removing a portion of the insulating layer, the removing forming a set of spacers on at least a vertical portion of the gate stack. SVG 14031126.10-03-2014.I₀ZH₈₄UGPXXIFW2.CLM.5.svg 0.16 6.17 Black and white canceled
progra m product of claim 10, the method further comprising: forming a conductive layer over the substrate, the spacers, the gate stack, and the mask; removing the mask; and removing a horizontal portion of the conductive layer over the gate stack, the removing defining and separating a source electrode and a drain electrode.
An integrated circuit comprising: a carbon-based semiconductor device, the carbon-based semiconductor device comprising: a substrate; and a gate stack, the gate stack comprising at least a carbon-based gate electrode formed on the substrate; a gate dielectric formed on the carbon-based gate electrode; [[and]] a carbon-based channel on the gate dielectric[[.]]; a source electrode contactin g a first portion of the substrate, a first a portion of the g ate dielectric, and a first portion of the carbon-based channe l; and a drain electrode contacting a second portion of the substrate, a second a portion of the g ate dielectric, and a second portion of the carbon-based channel.
The integrated circuit of claim 12, wherein the carbon-based semiconductor device further comprises: a set of spacers formed on at least a vertical portion of the gate stack.
The integrated circuit of claim 12, wherein the carbon-based semiconductor device further comprises: an oxide layer formed on the substrate.
Layer stacks claimed or described, ordered top of device to substrate.
carbon-based semiconductor structure (bottom-gated)
integrated circuit with carbon-based semiconductor device (bottom-gated)
Materials described outside the worked examples.
carbon-based gate electrode (graphene or graphite)
gate dielectric
carbon-based channel (graphene)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 3–500 nm | — |
Related documents with shared materials, methods, properties, or citations.
oxide layer
boron nitride
BN
diamond-like carbon
silicon nitride
Si₃N₄
gold
Au
PMMA (poly(methyl methacrylate))
silicon dioxide
SiO₂
silicon carbide substrate
SiC
oxide layer
boron nitride
BN
diamond-like carbon
silicon nitride
Si₃N₄
gold
Au
PMMA (poly(methyl methacrylate))
silicon dioxide
SiO₂
silicon carbide substrate
SiC
oxide layer
boron nitride
BN
diamond-like carbon
silicon nitride
Si₃N₄
gold
Au
PMMA (poly(methyl methacrylate))
silicon dioxide
SiO₂
silicon carbide substrate
SiC
oxide layer
boron nitride
BN
diamond-like carbon
silicon nitride
Si₃N₄
gold
Au
PMMA (poly(methyl methacrylate))
silicon dioxide
SiO₂
silicon carbide substrate
SiC