Patent
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Patent
US 12,439,682 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a circuit including a monolithic high side GaN device according to an embodiment of the disclosure;
FIG. 2 illustrates a buffer circuit according to an embodi- ment of the disclosure;
FIG. 3 illustrates a DC voltage level conversion circuit 15 according to an embodiment of the disclosure;
FIG. 4 illustrates a comparator circuit according to an embodiment of the disclosure;
FIG. 5 illustrates a latch circuit according to an embodi- ment of the disclosure; 20
FIG. 6 illustrates a circuit that can mitigate effects of dV/dt events on a noisy substrate according to an embodi- ment of the disclosure; and
FIG. 7 illustrates a circuit that can transmit a signal during a dV/dt event to turn on the high side GaN power transistor 25 according to an embodiment of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power converter comprising: a GaN-based die; 11 12 a switch formed on the GaN-based die and having a gate 9. The circuit of claim 8, wherein the input signal is a terminal, a source terminal and a drain terminal, pulse width modulated (PWM) signal. wherein the switch is arranged to be selectively con- 10. The circuit of claim 8, further comprising a compara-ductive according to a driver signal applied to the gate tor formed on the GaN-based die and coupled between the terminal; 5 voltage level converter and the gate terminal. a buffer circuit formed on the GaN-based die and arranged
The circuit of claim 10, further comprising a latch to receive an input signal and generate a corresponding circuit formed on the GaN-based die and coupled between differential output signal at a first output terminal and the comparator and the gate terminal. at a second output terminal; and
The circuit of claim 8, wherein the capacitor is a voltage level converter formed on the GaN-based die 10 metal-insulator-metal capacitor. and having a first input terminal coupled to the first
The circuit of claim 8, wherein the switch, the buffer output terminal via a first capacitor and having a second circuit, the voltage level converter and the capacitor are input terminal coupled to the second output terminal formed monolithically. via a second capacitor, and wherein the first and second
A power converter comprising: capacitors are formed on the GaN-based die, and 15 a GaN-based die; wherein an output terminal of the voltage level con-a switch formed on the GaN-based die and having a gate verter is coupled to the gate terminal and arranged to terminal, a source terminal and a drain terminal, generate the driver signal. wherein the switch is arranged to be selectively con-
The power converter of claim 14, wherein the input ductive according to a driver signal applied to the gate 40 signal is a pulse width modulated (PWM) signal. terminal;
The power converter of claim 14, further comprising a buffer circuit formed on the GaN-based die and having a comparator formed on the GaN-based die and coupled an input terminal and an first output terminal, the buffer between the voltage level converter and the gate terminal. circuit arranged to receive an input signal at the input
The power converter of claim 14, wherein the first and first input terminal and a second output terminal, the second capacitors are metal-insulator-metal capacitors. first input terminal coupled to the first output terminal
The power converter of claim 14, wherein the switch, and arranged to receive the first output signal and 50 the buffer circuit, the voltage level converter and the first and generate a second output signal at the second output second capacitors are formed monolithically. terminal, wherein the first output signal is referenced to
The power converter of claim 14, further comprising a ground at the second output signal is referenced to a positive dV/dt detector circuit coupled to the source floating voltage; and terminal and a negative dV/dt detector circuit coupled to the a voltage level converter formed on the GaN-based die 55 drain terminal. and coupled to the second output terminal and arranged to generate the driver signal. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
monolithic high side GaN circuit with capacitive level shifter (single-ended buffer)
monolithic high side GaN power converter with differential capacitive level shifter
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
metal-insulator-metal capacitor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 illustrates a circuit that can transmit a signal during a dV/dt event to turn on the high side GaN power transistor 25 according to an embodiment of the …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 12
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,439,682 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a circuit including a monolithic high side GaN device according to an embodiment of the disclosure;
FIG. 2 illustrates a buffer circuit according to an embodi- ment of the disclosure;
FIG. 3 illustrates a DC voltage level conversion circuit 15 according to an embodiment of the disclosure;
FIG. 4 illustrates a comparator circuit according to an embodiment of the disclosure;
FIG. 5 illustrates a latch circuit according to an embodi- ment of the disclosure; 20
FIG. 6 illustrates a circuit that can mitigate effects of dV/dt events on a noisy substrate according to an embodi- ment of the disclosure; and
FIG. 7 illustrates a circuit that can transmit a signal during a dV/dt event to turn on the high side GaN power transistor 25 according to an embodiment of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power converter comprising: a GaN-based die; 11 12 a switch formed on the GaN-based die and having a gate 9. The circuit of claim 8, wherein the input signal is a terminal, a source terminal and a drain terminal, pulse width modulated (PWM) signal. wherein the switch is arranged to be selectively con- 10. The circuit of claim 8, further comprising a compara-ductive according to a driver signal applied to the gate tor formed on the GaN-based die and coupled between the terminal; 5 voltage level converter and the gate terminal. a buffer circuit formed on the GaN-based die and arranged
The circuit of claim 10, further comprising a latch to receive an input signal and generate a corresponding circuit formed on the GaN-based die and coupled between differential output signal at a first output terminal and the comparator and the gate terminal. at a second output terminal; and
The circuit of claim 8, wherein the capacitor is a voltage level converter formed on the GaN-based die 10 metal-insulator-metal capacitor. and having a first input terminal coupled to the first
The circuit of claim 8, wherein the switch, the buffer output terminal via a first capacitor and having a second circuit, the voltage level converter and the capacitor are input terminal coupled to the second output terminal formed monolithically. via a second capacitor, and wherein the first and second
A power converter comprising: capacitors are formed on the GaN-based die, and 15 a GaN-based die; wherein an output terminal of the voltage level con-a switch formed on the GaN-based die and having a gate verter is coupled to the gate terminal and arranged to terminal, a source terminal and a drain terminal, generate the driver signal. wherein the switch is arranged to be selectively con-
The power converter of claim 14, wherein the input ductive according to a driver signal applied to the gate 40 signal is a pulse width modulated (PWM) signal. terminal;
The power converter of claim 14, further comprising a buffer circuit formed on the GaN-based die and having a comparator formed on the GaN-based die and coupled an input terminal and an first output terminal, the buffer between the voltage level converter and the gate terminal. circuit arranged to receive an input signal at the input
The power converter of claim 14, wherein the first and first input terminal and a second output terminal, the second capacitors are metal-insulator-metal capacitors. first input terminal coupled to the first output terminal
The power converter of claim 14, wherein the switch, and arranged to receive the first output signal and 50 the buffer circuit, the voltage level converter and the first and generate a second output signal at the second output second capacitors are formed monolithically. terminal, wherein the first output signal is referenced to
The power converter of claim 14, further comprising a ground at the second output signal is referenced to a positive dV/dt detector circuit coupled to the source floating voltage; and terminal and a negative dV/dt detector circuit coupled to the a voltage level converter formed on the GaN-based die 55 drain terminal. and coupled to the second output terminal and arranged to generate the driver signal. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
monolithic high side GaN circuit with capacitive level shifter (single-ended buffer)
monolithic high side GaN power converter with differential capacitive level shifter
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
metal-insulator-metal capacitor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 illustrates a circuit that can transmit a signal during a dV/dt event to turn on the high side GaN power transistor 25 according to an embodiment of the …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 12
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,439,682 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a circuit including a monolithic high side GaN device according to an embodiment of the disclosure;
FIG. 2 illustrates a buffer circuit according to an embodi- ment of the disclosure;
FIG. 3 illustrates a DC voltage level conversion circuit 15 according to an embodiment of the disclosure;
FIG. 4 illustrates a comparator circuit according to an embodiment of the disclosure;
FIG. 5 illustrates a latch circuit according to an embodi- ment of the disclosure; 20
FIG. 6 illustrates a circuit that can mitigate effects of dV/dt events on a noisy substrate according to an embodi- ment of the disclosure; and
FIG. 7 illustrates a circuit that can transmit a signal during a dV/dt event to turn on the high side GaN power transistor 25 according to an embodiment of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power converter comprising: a GaN-based die; 11 12 a switch formed on the GaN-based die and having a gate 9. The circuit of claim 8, wherein the input signal is a terminal, a source terminal and a drain terminal, pulse width modulated (PWM) signal. wherein the switch is arranged to be selectively con- 10. The circuit of claim 8, further comprising a compara-ductive according to a driver signal applied to the gate tor formed on the GaN-based die and coupled between the terminal; 5 voltage level converter and the gate terminal. a buffer circuit formed on the GaN-based die and arranged
The circuit of claim 10, further comprising a latch to receive an input signal and generate a corresponding circuit formed on the GaN-based die and coupled between differential output signal at a first output terminal and the comparator and the gate terminal. at a second output terminal; and
The circuit of claim 8, wherein the capacitor is a voltage level converter formed on the GaN-based die 10 metal-insulator-metal capacitor. and having a first input terminal coupled to the first
The circuit of claim 8, wherein the switch, the buffer output terminal via a first capacitor and having a second circuit, the voltage level converter and the capacitor are input terminal coupled to the second output terminal formed monolithically. via a second capacitor, and wherein the first and second
A power converter comprising: capacitors are formed on the GaN-based die, and 15 a GaN-based die; wherein an output terminal of the voltage level con-a switch formed on the GaN-based die and having a gate verter is coupled to the gate terminal and arranged to terminal, a source terminal and a drain terminal, generate the driver signal. wherein the switch is arranged to be selectively con-
The power converter of claim 14, wherein the input ductive according to a driver signal applied to the gate 40 signal is a pulse width modulated (PWM) signal. terminal;
The power converter of claim 14, further comprising a buffer circuit formed on the GaN-based die and having a comparator formed on the GaN-based die and coupled an input terminal and an first output terminal, the buffer between the voltage level converter and the gate terminal. circuit arranged to receive an input signal at the input
The power converter of claim 14, wherein the first and first input terminal and a second output terminal, the second capacitors are metal-insulator-metal capacitors. first input terminal coupled to the first output terminal
The power converter of claim 14, wherein the switch, and arranged to receive the first output signal and 50 the buffer circuit, the voltage level converter and the first and generate a second output signal at the second output second capacitors are formed monolithically. terminal, wherein the first output signal is referenced to
The power converter of claim 14, further comprising a ground at the second output signal is referenced to a positive dV/dt detector circuit coupled to the source floating voltage; and terminal and a negative dV/dt detector circuit coupled to the a voltage level converter formed on the GaN-based die 55 drain terminal. and coupled to the second output terminal and arranged to generate the driver signal. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
monolithic high side GaN circuit with capacitive level shifter (single-ended buffer)
monolithic high side GaN power converter with differential capacitive level shifter
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
metal-insulator-metal capacitor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 illustrates a circuit that can transmit a signal during a dV/dt event to turn on the high side GaN power transistor 25 according to an embodiment of the …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 12
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,439,682 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a circuit including a monolithic high side GaN device according to an embodiment of the disclosure;
FIG. 2 illustrates a buffer circuit according to an embodi- ment of the disclosure;
FIG. 3 illustrates a DC voltage level conversion circuit 15 according to an embodiment of the disclosure;
FIG. 4 illustrates a comparator circuit according to an embodiment of the disclosure;
FIG. 5 illustrates a latch circuit according to an embodi- ment of the disclosure; 20
FIG. 6 illustrates a circuit that can mitigate effects of dV/dt events on a noisy substrate according to an embodi- ment of the disclosure; and
FIG. 7 illustrates a circuit that can transmit a signal during a dV/dt event to turn on the high side GaN power transistor 25 according to an embodiment of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power converter comprising: a GaN-based die; 11 12 a switch formed on the GaN-based die and having a gate 9. The circuit of claim 8, wherein the input signal is a terminal, a source terminal and a drain terminal, pulse width modulated (PWM) signal. wherein the switch is arranged to be selectively con- 10. The circuit of claim 8, further comprising a compara-ductive according to a driver signal applied to the gate tor formed on the GaN-based die and coupled between the terminal; 5 voltage level converter and the gate terminal. a buffer circuit formed on the GaN-based die and arranged
The circuit of claim 10, further comprising a latch to receive an input signal and generate a corresponding circuit formed on the GaN-based die and coupled between differential output signal at a first output terminal and the comparator and the gate terminal. at a second output terminal; and
The circuit of claim 8, wherein the capacitor is a voltage level converter formed on the GaN-based die 10 metal-insulator-metal capacitor. and having a first input terminal coupled to the first
The circuit of claim 8, wherein the switch, the buffer output terminal via a first capacitor and having a second circuit, the voltage level converter and the capacitor are input terminal coupled to the second output terminal formed monolithically. via a second capacitor, and wherein the first and second
A power converter comprising: capacitors are formed on the GaN-based die, and 15 a GaN-based die; wherein an output terminal of the voltage level con-a switch formed on the GaN-based die and having a gate verter is coupled to the gate terminal and arranged to terminal, a source terminal and a drain terminal, generate the driver signal. wherein the switch is arranged to be selectively con-
The power converter of claim 14, wherein the input ductive according to a driver signal applied to the gate 40 signal is a pulse width modulated (PWM) signal. terminal;
The power converter of claim 14, further comprising a buffer circuit formed on the GaN-based die and having a comparator formed on the GaN-based die and coupled an input terminal and an first output terminal, the buffer between the voltage level converter and the gate terminal. circuit arranged to receive an input signal at the input
The power converter of claim 14, wherein the first and first input terminal and a second output terminal, the second capacitors are metal-insulator-metal capacitors. first input terminal coupled to the first output terminal
The power converter of claim 14, wherein the switch, and arranged to receive the first output signal and 50 the buffer circuit, the voltage level converter and the first and generate a second output signal at the second output second capacitors are formed monolithically. terminal, wherein the first output signal is referenced to
The power converter of claim 14, further comprising a ground at the second output signal is referenced to a positive dV/dt detector circuit coupled to the source floating voltage; and terminal and a negative dV/dt detector circuit coupled to the a voltage level converter formed on the GaN-based die 55 drain terminal. and coupled to the second output terminal and arranged to generate the driver signal. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
monolithic high side GaN circuit with capacitive level shifter (single-ended buffer)
monolithic high side GaN power converter with differential capacitive level shifter
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
metal-insulator-metal capacitor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 illustrates a circuit that can transmit a signal during a dV/dt event to turn on the high side GaN power transistor 25 according to an embodiment of the …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 12
Related documents with shared materials, methods, properties, or citations.
monolithic high side GaN device (described embodiment)
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